From a96b816a30c0f538f48ecb231c0a6fedb5393e7d Mon Sep 17 00:00:00 2001 From: Long Yu Date: Mon, 15 Apr 2019 16:40:25 +0800 Subject: [PATCH] emmc: Clear the value of txdelay in legacy mode on the resume process [1/1] PD#SWPL-7181 Problem: switch to high-speed from hs200 failed for resume process. Solution: set tx_delay as 0 for legacy mode. clear cfg_cmd_setup Verify: verify by TL1 Change-Id: I5dbb1bbc391da864464bf137837a2b0f54ccda42 Signed-off-by: Long Yu Conflicts: arch/arm/boot/dts/amlogic/mesontl1.dtsi arch/arm64/boot/dts/amlogic/mesontl1.dtsi --- drivers/amlogic/mmc/aml_sd_emmc_v3.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 56e3871ddddd..c00fcb4b3853 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -392,6 +392,11 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, clkc->tx_phase = para->sdr104.tx_phase; } else { ctrl->ddr = 0; + clkc->tx_delay = 0; + clkc->core_phase = para->init.core_phase; + clkc->tx_phase = para->init.tx_phase; + irq_en &= ~(1<<17); + writel(irq_en, host->base + SD_EMMC_IRQ_EN); /* timing == MMC_TIMING_LEGACY */ if (pdata->calc_f) { clkc->core_phase = para->calc.core_phase;