From aa34d0fe717d26c298595b083458099bc27e4560 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 14 Jan 2019 14:52:07 +0800 Subject: [PATCH] clk: rockchip: Modify uart frac divider rule Because uart does not have high requirements for the clk Jitter, the fractional frequency divider does not need to meet the 20-fold relationship. (If uart clk rate < 24M,Use 24M as the fractional clock source.) Change-Id: I3f55f8a4ba5dc4c950c2742dc914c41e7b6e4ee6 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index ddb9669167fd..a2cf1d39e450 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -179,6 +179,19 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, u32 div; p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); + + if (strstr(clk_hw_get_name(hw), "uart")) { + if (rate <= 24000000) { + *parent_rate = 24000000; + } else { + if (fd->max_prate) + *parent_rate = fd->max_prate; + else + *parent_rate = 480000000; + } + goto frac_ration; + } + if (((rate * 20 > p_rate) && (p_rate % rate != 0)) || (fd->max_prate && fd->max_prate < p_rate)) { p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); @@ -203,6 +216,7 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, } } +frac_ration: /* * Get rate closer to *parent_rate to guarantee there is no overflow * for m and n. In the result it will be the nearest rate left shifted