diff --git a/Documentation/devicetree/bindings/video/rockchip_dp.txt b/Documentation/devicetree/bindings/video/rockchip_dp.txt deleted file mode 100644 index 52c079743e99..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_dp.txt +++ /dev/null @@ -1,50 +0,0 @@ -Rockchip RK3399 specific extensions to the cdn Display Port with rkfb -================================ - -Required properties: -- compatible: must be "rockchip,rk3399-cdn-dp-fb" - -- reg: physical base address of the controller and length - -- clocks: from common clock binding: handle to dp clock. - -- clock-names: from common clock binding: - Required elements: "core-clk" "pclk" "spdif" - -- resets : a list of phandle + reset specifier pairs -- reset-names : string reset name, must be: - "spdif" -- power-domains : power-domain property defined with a phandle - to respective power domain. -- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> -- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 - -- rockchip,grf: this soc should set GRF regs, so need get grf here. - -- phys: from general PHY binding: the phandle for the PHY device. - -- extcon: extcon specifier for the Power Delivery - -- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF - -------------------------------------------------------------------------------- - -Example: - cdn_dp_fb: dp-fb@fec00000 { - compatible = "rockchip,rk3399-cdn-dp-fb"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>; - clock-names = "core-clk", "pclk", "spdif"; - assigned-clocks = <&cru SCLK_DP_CORE>; - assigned-clock-rates = <100000000>; - power-domains = <&power RK3399_PD_HDCP>; - phys = <&tcphy0 0>, <&tcphy1 0>; - resets = <&cru SRST_DPTX_SPDIF_REC>; - reset-names = "spdif"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/video/rockchip_fb.txt b/Documentation/devicetree/bindings/video/rockchip_fb.txt deleted file mode 100755 index 4b86bb657086..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_fb.txt +++ /dev/null @@ -1,65 +0,0 @@ -Device-Tree bindings for Rockchip framebuffer. - -Required properties: -- compatible: value should be "rockchip,rk-fb". -- rockchip,disp-mode: DUAL :for dual lcdc and dual display; - ONE_DUAL : for one lcdc and dual display. - -Example: - -DT entry: - fb: fb{ - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = ; - }; - -Device-Tree bindings for RockChip screen driver - -Required properties: -- compatible: value should be "rockchip,screen" -- display-timings: value should be disp_timings, which defined in - lcd-xxx.dtsi file,the file should include by your board dts - -Example: - creen: rk_screen{ - compatible = "rockchip,screen"; - display-timings = <&disp_timings>; - }; - -/* - * RockChip. LCD_B101ew05 lcd-b101ew05.dtsi - * - */ - -/ { - - disp_timings: display-timings { - native-mode = <&timing0>; - timing0: timing0 { - screen-type = ; - lvds-format = ; - out-face = ; - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <100>; - hfront-porch = <18>; - vback-porch = <8>; - vfront-porch = <6>; - hsync-len = <10>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - swap-rb = <0>; - swap-rg = <0>; - swap-gb = <0>; - }; - }; -}; - - - - -note: reference for display-timing.txt for display-timing bindings diff --git a/Documentation/devicetree/bindings/video/rockchip_lcdc.txt b/Documentation/devicetree/bindings/video/rockchip_lcdc.txt deleted file mode 100755 index acf879042ab2..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_lcdc.txt +++ /dev/null @@ -1,69 +0,0 @@ -Device-Tree bindings for Rockchip SoC display controller (VOP / LCDC) -VOP (Video Output Process) / LCDC is the Display Controller for the -ROCKCHIP series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3288-lcdc"; /* for RK3288 SoCs */ - "rockchip,rk3368-lcdc"; /* for RK3368 SoCs */ - "rockchip,rk322x-lcdc"; /* for RK322X SoCs */ - "rockchip,rk3399-lcdc"; /* for RK3399 SoCs */ -- rockchip,prop: set the lcdc as primary or extend display. -- rochchip,pwr18: set the controller IO voltage,0 is 3.3v,1 is 1.8v. -- reg: physical base address and length of the LCDC registers set. -- interrupts: interrupt number to the cpu and interrupt proterties. -- pinctrl-names: must contain a "default" entry. -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-1: pin control group to be used for gpio. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: list of clock names sorted in the same order as the clocks - property.. - -Optional Properties: -- rockchip,debug: printk debug message. -- rockchip,mirror: the lcdc mirror function. -- lcd_en:lcd_en: contain power control for lcd. - - rockchip,power_type: power type,GPIO or REGULATOR. - - gpios: pin number for gpio. - - rockchip,delay: delay time after set power. - -Example: - -SoC specific DT entry: - lcdc1: lcdc@ff940000 { - compatible = "rockchip,rk3288-lcdc"; - rockchip,prop = ; - rochchip,pwr18 = <0>; - reg = <0xff940000 0x10000>; - interrupts = ; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&lcdc0_lcdc>; - pinctrl-1 = <&lcdc0_gpio>; - status = "disabled"; - clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc"; - }; - - -Board specific DT entry: - -&lcdc1 { - status = "okay"; - power_ctr: power_ctr { - rockchip,debug = <0>; - rockchip,mirror = ; - lcd_en:lcd_en { - rockchip,power_type = ; - gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; - rockchip,delay = <10>; - }; - lcd_cs:lcd_cs { - rockchip,power_type = ; - gpios = <&gpio7 GPIO_A4 GPIO_ACTIVE_HIGH>; - rockchip,delay = <10>; - }; - }; -}; - diff --git a/Documentation/devicetree/bindings/video/rockchip_lvds.txt b/Documentation/devicetree/bindings/video/rockchip_lvds.txt deleted file mode 100644 index d7f6f08b2cdf..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_lvds.txt +++ /dev/null @@ -1,22 +0,0 @@ -The Rockchip display port interface should be configured based on -the type of panel connected to it. - -Required properties: -- compatible: value should be "rockchip,rk32-lvds". -- reg: physical base address and length of the LVDS registers set. -- interrupts: interrupt number to the cpu and interrupt proterties. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: list of clock names sorted in the same order as the clocks - property.. - -Example: - -SoC specific DT entry: - lvds: lvds@ff96c000 { - compatible = "rockchip,rk32-lvds"; - reg = <0xff96c000 0x4000>; - clocks = <&clk_gates16 7>; - clock-names = "pclk_lvds"; - }; - diff --git a/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt b/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt deleted file mode 100755 index bf571279392e..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt +++ /dev/null @@ -1,39 +0,0 @@ -Device-Tree bindings for rockchip mipi dsi driver - -Required properties: -- compatible: value should be "rockchip,rk32-dsi". -- rockchip,prop: dsi number. -- reg: physical base address of the hdmi and length of memory mapped - region. -- interrupts: interrupt number to the cpu. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clocks-names: list of clock names sorted in the same order as the clocks - property. Must contain "pclk_hdmi" and "hdcp_clk_hdmi". -- status: the dsi host status; - : open the dsi host; - :close the dsi host; - -Example: - - dsihost0: mipi@ff960000{ - compatible = "rockchip,rk32-dsi"; - rockchip,prop = <0>; - reg = <0xff960000 0x4000>; - interrupts = ; - clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>; - clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi"; - status = "okay"; - }; - - dsihost1: mipi@ff964000{ - compatible = "rockchip,rk32-dsi"; - rockchip,prop = <1>; - reg = <0xff964000 0x4000>; - interrupts = ; - clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>; - clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi"; - status = "okay"; - }; - diff --git a/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt b/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt deleted file mode 100755 index 837a3bd76b7f..000000000000 --- a/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt +++ /dev/null @@ -1,173 +0,0 @@ -Device-Tree bindings for rockchip mipi dsi lcd driver - -Required properties: - - rockchip,screen_init: Whether you need this screen initialization. - <0>: Don't need to be initialized. - <1>: Do need to be initialized. - - - rockchip,dsi_lane: mipi lcd data lane number. - - - rockchip,dsi_hs_clk: mipi lcd high speed clock. - - - rockchip,mipi_dsi_num: mipi lcd dsi number. - - - mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd. - - - mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd. - - - rockchip,gpios: gpio pin - - - rockchip,delay: delay the millisecond. - - - rockchip,cmd_debug : debug the cammands. - <0>: close the debug; - <1>: open the debug; - - - rockchip,on-cmds1: write cammand to mipi lcd. - -- rockchip,cmd_type: - : close the debug; - : open the debug; - - - rockchip,dsi_id: write cammand to mipi lcd(left and right). - <0>: left dsi; - <1>: right dsi; - <2>: left and right dsis; - - - rockchip,cmd: cammand context. - The first parameter was data type; - The second parameter was index(register); - The third and ... parameter are cammand context; - - - rockchip,cmd_delay: delay the millisecond. - - - screen-type: mipi lcd type. - : Dual channel mipi lcd. - : single channel mipi lcd. - - - lvds-format:No relationship. - - - out-face: DPI color coding as follows: - :24bit - :18bit - :16bit - - - hactive, vactive: display resolution - - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters - in pixels - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in - lines - - clock-frequency: display clock in Hz - - - swap-rb :exchange of red and blue. - - swap-rg :exchange of red and green. - - swap-gb :exchange of green and blue. - - - hsync-active: hsync pulse is active low/high/ignored - - vsync-active: vsync pulse is active low/high/ignored - - de-active: data-enable pulse is active low/high/ignored - - pixelclk-active: with - - active high = drive pixel data on rising edge/ - sample data on falling edge - - active low = drive pixel data on falling edge/ - sample data on rising edge - - ignored = ignored - - interlaced (bool): boolean to enable interlaced mode - - doublescan (bool): boolean to enable doublescan mode - -All the optional properties that are not bool follow the following logic: - <1>: high active - <0>: low active - omitted: not used on hardware - -There are different ways of describing the capabilities of a display. The -devicetree representation corresponds to the one commonly found in datasheets -for displays. If a display supports multiple signal timings, the native-mode -can be specified. - -The parameters are defined as: - - +----------+-------------------------------------+----------+-------+ - | | | | | - | | |vback_porch | | | - | | | | | - +----------#######################################----------+-------+ - | # # | | - | # | # | | - | hback # | # hfront | hsync | - | porch # | hactive # porch | len | - |<-------->#<-------+--------------------------->#<-------->|<----->| - | # | # | | - | # |vactive # | | - | # | # | | - | # # | | - +----------#######################################----------+-------+ - | | | | | - | | |vfront_porch | | | - | | | | | - +----------+-------------------------------------+----------+-------+ - | | | | | - | | |vsync_len | | | - | | | | | - +----------+-------------------------------------+----------+-------+ - - -Example: - -{ - /* about mipi */ - disp_mipi_init: mipi_dsi_init{ - rockchip,screen_init = <1>; - rockchip,dsi_lane = <4>; - rockchip,dsi_hs_clk = <1020>; - rockchip,mipi_dsi_num = <2>; - }; - disp_mipi_power_ctr: mipi_power_ctr { - mipi_lcd_rst:mipi_lcd_rst{ - rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>; - rockchip,delay = <10>; - }; - /*mipi_lcd_en:mipi_lcd_en { - rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>; - rockchip,delay = <10>; - };*/ - }; - disp_mipi_init_cmds: screen-on-cmds { - rockchip,cmd_debug = <0>; - rockchip,on-cmds1 { - rockchip,cmd_type = ; - rockchip,dsi_id = <2>; - rockchip,cmd = <0x05 0x01>; //set soft reset - rockchip,cmd_delay = <10>; - }; - }; - - disp_timings: display-timings { - native-mode = <&timing0>; - timing0: timing0 { - screen-type = ; - lvds-format = ; - out-face = ; - clock-frequency = <285000000>; - hactive = <2560>; - vactive = <1600>; - - hsync-len = <38>;//19 - hback-porch = <80>;//40 - hfront-porch = <246>;//123 - - vsync-len = <4>; - vback-porch = <4>; - vfront-porch = <12>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - swap-rb = <0>; - swap-rg = <0>; - swap-gb = <0>; - }; - }; -}; - diff --git a/arch/arm/boot/dts/rk3502.dtsi b/arch/arm/boot/dts/rk3502.dtsi index 039fd5ff9bd6..ac795287b5b0 100644 --- a/arch/arm/boot/dts/rk3502.dtsi +++ b/arch/arm/boot/dts/rk3502.dtsi @@ -1452,9 +1452,15 @@ #reset-cells = <1>; assigned-clocks = + <&cru CLK_32K_FRAC_MUX>, + <&cru CLK_32K_FRAC>, <&cru CLK_FRAC_UART_MATRIX0>, <&cru CLK_FRAC_UART_MATRIX1>; + assigned-clock-parents = + <&cru PLL_V0PLL>; assigned-clock-rates = + <0>, + <32768>, <96000000>, <128000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts index 3e5f82852660..f934c3126b86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts @@ -542,8 +542,8 @@ vccio_acodec: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts index e483e0cc34aa..4f3e218b59df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts @@ -396,8 +396,8 @@ vccio_acodec: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts index f00714e39511..dfcf9a2b4f54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts @@ -724,8 +724,8 @@ vccio_acodec: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts index 323471509afd..4578517486dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts @@ -542,8 +542,8 @@ vccio_acodec: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts index b1629d722493..b71f170cafcd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts @@ -656,8 +656,8 @@ vccio_acodec: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vccio_acodec"; regulator-state-mem { regulator-off-in-suspend; diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c index d7e5fc6661ff..639ff439aa6c 100644 --- a/drivers/clk/rockchip/clk-rk3506.c +++ b/drivers/clk/rockchip/clk-rk3506.c @@ -742,9 +742,10 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = { COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0, RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS), - COMPOSITE_DIV_OFFSET(CLK_32K_FRAC, "clk_32k_frac", clk_32k_frac_parents_p, CLK_IGNORE_UNUSED, - RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS, - RK3506_PMU_CLKSEL_CON(2), 0, 32, DFLAGS, + MUX(CLK_32K_FRAC_MUX, "clk_32k_frac_mux", clk_32k_frac_parents_p, 0, + RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_32K_FRAC, "clk_32k_frac", "clk_32k_frac_mux", 0, + RK3506_PMU_CLKSEL_CON(2), 0, RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS), COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL, RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS, diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index e05b61cea886..0b00c6a3562b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -197,6 +197,7 @@ #define HDMI_EARC_MODE BIT(29) #define DATA_RATE_MASK 0xFFFFFFF +#define HDMI14_MAX_RATE 340000 #define HDMI20_MAX_RATE 600000 #define HDMI_8K60_RATE 2376000 @@ -2382,12 +2383,12 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, *color_format = RK_IF_FORMAT_YCBCR422; else if (conn_state->connector->ycbcr_420_allowed && drm_mode_is_420(info, &mode) && - (pixclock >= 594000 && !hdmi->is_hdmi_qp)) + (pixclock > HDMI14_MAX_RATE && !hdmi->is_hdmi_qp)) *color_format = RK_IF_FORMAT_YCBCR420; break; case RK_IF_FORMAT_YCBCR_LQ: if (conn_state->connector->ycbcr_420_allowed && - drm_mode_is_420(info, &mode) && pixclock >= 594000) + drm_mode_is_420(info, &mode) && pixclock > HDMI14_MAX_RATE) *color_format = RK_IF_FORMAT_YCBCR420; else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) *color_format = RK_IF_FORMAT_YCBCR422; @@ -2396,7 +2397,7 @@ dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, break; case RK_IF_FORMAT_YCBCR420: if (conn_state->connector->ycbcr_420_allowed && - drm_mode_is_420(info, &mode) && pixclock >= 594000) + drm_mode_is_420(info, &mode) && pixclock > HDMI14_MAX_RATE) *color_format = RK_IF_FORMAT_YCBCR420; break; case RK_IF_FORMAT_YCBCR422: diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c index 8d71df1d4cbf..7b5e3c2bbe2f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c @@ -351,3 +351,49 @@ int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *ro return 0; } + +static int rockchip_drm_debugfs_dclk_rate_show(struct seq_file *s, void *data) +{ + struct drm_crtc *crtc = s->private; + struct rockchip_drm_private *priv = crtc->dev->dev_private; + int pipe = drm_crtc_index(crtc); + unsigned long rate; + + if (!priv->crtc_funcs[pipe]->crtc_get_dclk_rate) { + seq_puts(s, "Not support get rate\n"); + return 0; + } + + rate = priv->crtc_funcs[pipe]->crtc_get_dclk_rate(crtc); + + seq_printf(s, "%lu\n", rate); + return 0; +} + +static int rockchip_drm_debugfs_dclk_rate_open(struct inode *inode, struct file *file) +{ + struct drm_crtc *crtc = inode->i_private; + + return single_open(file, rockchip_drm_debugfs_dclk_rate_show, crtc); +} + +static const struct file_operations rockchip_drm_debugfs_dclk_rate_ops = { + .owner = THIS_MODULE, + .open = rockchip_drm_debugfs_dclk_rate_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root) +{ + struct dentry *ent; + + ent = debugfs_create_file("calculated_dclk_rate", 0644, root, crtc, + &rockchip_drm_debugfs_dclk_rate_ops); + if (!ent) + DRM_ERROR("Failed to add dclk_rate for debugfs\n"); + + return 0; +} + diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h index 2f8ec1677245..bb7290146427 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h @@ -37,6 +37,7 @@ rockchip_drm_crtc_dump_plane_buffer(struct drm_crtc *crtc) #endif int rockchip_drm_debugfs_add_color_bar(struct drm_crtc *crtc, struct dentry *root); int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root); +int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root); #else static inline int rockchip_drm_add_dump_buffer(struct drm_crtc *crtc, struct dentry *root) @@ -61,6 +62,12 @@ rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root) { return 0; } + +static inline int +rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root) +{ + return 0; +} #endif #endif diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index c28e84f7a2b1..1dc25364eed7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -527,6 +527,7 @@ struct rockchip_crtc_funcs { void (*crtc_output_post_enable)(struct drm_crtc *crtc, int intf); void (*crtc_output_pre_disable)(struct drm_crtc *crtc, int intf); int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode); + unsigned long (*crtc_get_dclk_rate)(struct drm_crtc *crtc); int (*set_aclk)(struct drm_crtc *crtc, enum rockchip_drm_vop_aclk_mode aclk_mode, struct dmcfreq_vop_info *vop_bw_info); int (*get_crc)(struct drm_crtc *crtc); void (*iommu_fault_handler)(struct drm_crtc *crtc, struct iommu_domain *iommu); diff --git a/drivers/iio/adc/gpio_muxadc.c b/drivers/iio/adc/gpio_muxadc.c index bf5e2d4b504c..3e8deb53c82c 100644 --- a/drivers/iio/adc/gpio_muxadc.c +++ b/drivers/iio/adc/gpio_muxadc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2018 Rockchip Electronics Co. Ltd. + * Copyright (c) 2018 Rockchip Electronics Co., Ltd. * * Author: Ziyuan Xu */ diff --git a/drivers/misc/rk628/rk628_dsi.c b/drivers/misc/rk628/rk628_dsi.c index 3d0681855c37..28182b99df58 100644 --- a/drivers/misc/rk628/rk628_dsi.c +++ b/drivers/misc/rk628/rk628_dsi.c @@ -950,6 +950,17 @@ static void testif_write(struct rk628 *rk628, const struct rk628_dsi *dsi, dev_info(rk628->dev, "monitor_data: 0x%x\n", monitor_data); } +static u8 testif_read(struct rk628 *rk628, const struct rk628_dsi *dsi, u8 reg) +{ + u8 value = 0; + + testif_test_code_write(rk628, dsi, reg); + value = testif_get_data(rk628, dsi); + testif_test_data_write(rk628, dsi, value); + + return value; +} + static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr, u8 max, u8 val) { @@ -961,6 +972,126 @@ static void testif_set_timing(const struct rk628_dsi *dsi, u8 addr, testif_write(rk628, dsi, addr, (max + 1) | val); } +static const struct { + char *name; + u8 reg; + u8 max; +} dphy_timing_table[] = { + { "clk_lp", 0x60, 0x3f }, + { "clk_hs_prepare", 0x61, 0x7f }, + { "clk_hs_zero", 0x62, 0x3f }, + { "clk_hs_trail", 0x63, 0x7f }, + { "clk_post", 0x65, 0x0f }, + { "data_lp", 0x70, 0x3f }, + { "data_hs_prepare", 0x71, 0x7f }, + { "data_hs_zero", 0x72, 0x3f }, + { "data_hs_trail", 0x73, 0x7f }, +}; + +static int rk628_dphy_timing_show(struct seq_file *s, void *v) +{ + struct rk628 *rk628 = s->private; + u8 val; + + seq_printf(s, "%-29sdphy0 dphy1\n", ""); + for (int i = 0; i < ARRAY_SIZE(dphy_timing_table); i++) { + seq_printf(s, "%-15s(0x%02x ~ 0x%02x): ", dphy_timing_table[i].name, 0, + dphy_timing_table[i].max); + + val = testif_read(rk628, &rk628->dsi0, dphy_timing_table[i].reg); + if (val & (dphy_timing_table[i].max + 1)) + seq_printf(s, "0x%02x ", val & dphy_timing_table[i].max); + else + seq_puts(s, "auto "); + + val = testif_read(rk628, &rk628->dsi1, dphy_timing_table[i].reg); + if (val & (dphy_timing_table[i].max + 1)) + seq_printf(s, "0x%02x ", val & dphy_timing_table[i].max); + else + seq_puts(s, "auto "); + + seq_puts(s, "\n"); + } + + seq_puts(s, "\n"); + seq_puts(s, "example of modify single configuration:\n"); + seq_puts(s, " echo dphy0.data_hs_prepare 0x40 > dphy_timing\n"); + seq_puts(s, "example of modify multiple configurations:\n"); + seq_puts(s, " echo dphy0 0x7 0x30 0x25 0x3c 0xf 0x7 0x40 0x9 0x40 > dphy_timing\n"); + + return 0; +} + +static ssize_t rk628_dphy_timing_write(struct file *file, const char __user *buf, size_t count, + loff_t *ppos) +{ + struct rk628 *rk628 = file->f_path.dentry->d_inode->i_private; + struct rk628_dsi *dsi; + char kbuf[51], *p; + u32 val; + int ret; + + if (count >= sizeof(kbuf)) + return -ENOSPC; + + if (copy_from_user(kbuf, buf, count)) + return -EFAULT; + + kbuf[count] = '\0'; + + if (strstr(kbuf, "dphy0") == kbuf) + dsi = &rk628->dsi0; + else if (strstr(kbuf, "dphy1") == kbuf) + dsi = &rk628->dsi1; + else + return -EINVAL; + + p = kbuf + 5; + if (*(p++) == '.') { + char name[51]; + + ret = sscanf(p, "%s %x", name, &val); + if (ret != 2) + return -EINVAL; + + for (int i = 0; i < ARRAY_SIZE(dphy_timing_table); i++) { + if (strcmp(name, dphy_timing_table[i].name) == 0) { + testif_set_timing(dsi, dphy_timing_table[i].reg, + dphy_timing_table[i].max, val); + return count; + } + } + } else { + int i = 0; + + while (i < ARRAY_SIZE(dphy_timing_table) && sscanf(p, "%x%n", &val, &ret) == 1) { + testif_set_timing(dsi, dphy_timing_table[i].reg, + dphy_timing_table[i].max, val); + i++; + p += ret; + } + return count; + } + + return -EINVAL; +} + +static int rk628_dphy_timing_open(struct inode *inode, struct file *file) +{ + struct rk628 *rk628 = inode->i_private; + + return single_open(file, rk628_dphy_timing_show, rk628); +} + +static const struct file_operations rk628_dphy_timing_fops = { + .owner = THIS_MODULE, + .open = rk628_dphy_timing_open, + .read = seq_read, + .write = rk628_dphy_timing_write, + .llseek = seq_lseek, + .release = single_release, +}; + static void mipi_dphy_set_timing(const struct rk628_dsi *dsi) { const struct { @@ -1363,9 +1494,12 @@ static const struct file_operations rk628_dsi_color_bar_fops = { void rk628_mipi_dsi_create_debugfs_file(struct rk628 *rk628) { - if (rk628_output_is_dsi(rk628)) + if (rk628_output_is_dsi(rk628)) { debugfs_create_file("dsi_color_bar", 0600, rk628->debug_dir, rk628, &rk628_dsi_color_bar_fops); + debugfs_create_file("dphy_timing", 0600, rk628->debug_dir, + rk628, &rk628_dphy_timing_fops); + } } void rk628_mipi_dsi_pre_enable(struct rk628 *rk628) diff --git a/drivers/misc/rk628/rk628_hdmitx.c b/drivers/misc/rk628/rk628_hdmitx.c index f44371bba2b7..19b05981441f 100644 --- a/drivers/misc/rk628/rk628_hdmitx.c +++ b/drivers/misc/rk628/rk628_hdmitx.c @@ -511,9 +511,9 @@ static int rk628_hdmi_config_video_timing(struct rk628_hdmi *hdmi, value = mode->vsync_end - mode->vsync_start; hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); - hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); - hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); - hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); + hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x02); + hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_LOW, 0x14); + hdmi_writeb(hdmi, PHY_FEEDBACK_DIV_RATIO_HIGH, 0x00); return 0; } diff --git a/drivers/mtd/nand/bbt_store.c b/drivers/mtd/nand/bbt_store.c index 8687861bf3b4..2f9807138e0e 100644 --- a/drivers/mtd/nand/bbt_store.c +++ b/drivers/mtd/nand/bbt_store.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * */ diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mtd/nand/raw/rockchip-nand-controller.c index 2a2f0b9fc9b9..4b121fdad8b5 100644 --- a/drivers/mtd/nand/raw/rockchip-nand-controller.c +++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 OR MIT /* * Rockchip NAND Flash controller driver. - * Copyright (C) 2020 Rockchip Inc. + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. * Author: Yifeng Zhao */ diff --git a/drivers/mtd/rknand/rknand_base.h b/drivers/mtd/rknand/rknand_base.h index 6460e9eace46..eeb1e1228444 100644 --- a/drivers/mtd/rknand/rknand_base.h +++ b/drivers/mtd/rknand/rknand_base.h @@ -2,7 +2,7 @@ /* * linux/drivers/mtd/rknand/rknand_base.c * - * Copyright (C) 2005-2009 Fuzhou Rockchip Electronics + * Copyright (C) 2005-2009 Rockchip Electronics Co., Ltd. * ZYF * * diff --git a/drivers/mtd/rknand/rknand_base_ko.c b/drivers/mtd/rknand/rknand_base_ko.c index 5a462b76dc42..928ab8b7b3a8 100644 --- a/drivers/mtd/rknand/rknand_base_ko.c +++ b/drivers/mtd/rknand/rknand_base_ko.c @@ -2,7 +2,7 @@ /* * linux/drivers/mtd/rknand/rknand_base.c * - * Copyright (C) 2005-2009 Fuzhou Rockchip Electronics + * Copyright (C) 2005-2009 Rockchip Electronics Co., Ltd. * ZYF * * diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_uio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_uio.c index 11ec4b787da4..0db6d50cc542 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_uio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_uio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /** - * Copyright 2023 ROCKCHIP + * Copyright 2023 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c index a4abd835c9e1..b345aba78044 100644 --- a/drivers/net/phy/rk630phy.c +++ b/drivers/net/phy/rk630phy.c @@ -3,7 +3,7 @@ * * Driver for ROCKCHIP RK630 Ethernet PHYs * - * Copyright (c) 2020, Rockchip Electronics Co., Ltd + * Copyright (c) 2020, Rockchip Electronics Co., Ltd. * * David Wu * diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 5841a41a6703..bc8c2cb3cd01 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -200,7 +200,7 @@ static const struct rockchip_p3phy_ops rk3588_ops = { .phy_calibrate = rockchip_p3phy_rk3588_calibrate, }; -static int rochchip_p3phy_init(struct phy *phy) +static int rockchip_p3phy_init(struct phy *phy) { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); int ret; @@ -223,7 +223,7 @@ static int rochchip_p3phy_init(struct phy *phy) return ret; } -static int rochchip_p3phy_exit(struct phy *phy) +static int rockchip_p3phy_exit(struct phy *phy) { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); @@ -232,9 +232,9 @@ static int rochchip_p3phy_exit(struct phy *phy) return 0; } -static const struct phy_ops rochchip_p3phy_ops = { - .init = rochchip_p3phy_init, - .exit = rochchip_p3phy_exit, +static const struct phy_ops rockchip_p3phy_ops = { + .init = rockchip_p3phy_init, + .exit = rockchip_p3phy_exit, .set_mode = rockchip_p3phy_set_mode, .owner = THIS_MODULE, }; @@ -294,7 +294,7 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) (reg << 16) | reg); }; - priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops); if (IS_ERR(priv->phy)) { dev_err(dev, "failed to create combphy\n"); return PTR_ERR(priv->phy); diff --git a/drivers/pinctrl/pinctrl-max96745.c b/drivers/pinctrl/pinctrl-max96745.c index e5e2c6772f27..5ee29bddab7b 100644 --- a/drivers/pinctrl/pinctrl-max96745.c +++ b/drivers/pinctrl/pinctrl-max96745.c @@ -2,7 +2,7 @@ /* * Maxim MAX96745 pin control driver * - * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/pinctrl/pinctrl-max96755f.c b/drivers/pinctrl/pinctrl-max96755f.c index cf1708e8f06c..93472d5edb71 100644 --- a/drivers/pinctrl/pinctrl-max96755f.c +++ b/drivers/pinctrl/pinctrl-max96755f.c @@ -2,7 +2,7 @@ /* * Maxim max96755f pin control driver. * - * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index c8478816095d..8e1173f60d73 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. * * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner diff --git a/drivers/power/ec_battery.c b/drivers/power/ec_battery.c index 9627cd1a0a11..38db43507bee 100644 --- a/drivers/power/ec_battery.c +++ b/drivers/power/ec_battery.c @@ -1,7 +1,7 @@ /* * ec battery driver * - * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. * Shunqing Chen * * This program is free software; you can redistribute it and/or modify it diff --git a/drivers/power/supply/cw2015_battery.c b/drivers/power/supply/cw2015_battery.c index cdd6e028f461..d797974994c8 100644 --- a/drivers/power/supply/cw2015_battery.c +++ b/drivers/power/supply/cw2015_battery.c @@ -2,7 +2,7 @@ /* * Fuel gauge driver for CellWise 2013 / 2015 * - * Copyright (C) 2012, RockChip + * Copyright (C) 2012, Rockchip Electronics Co., Ltd. * Copyright (C) 2020, Tobias Schramm * * Authors: xuhuicong diff --git a/drivers/power/supply/rk817_charger.c b/drivers/power/supply/rk817_charger.c index d3c4e56828e9..852002437e94 100644 --- a/drivers/power/supply/rk817_charger.c +++ b/drivers/power/supply/rk817_charger.c @@ -1,7 +1,7 @@ /* * rk817 charger driver * - * Copyright (C) 2018 Rockchip Electronics Co., Ltd + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. * xsf * * This program is free software; you can redistribute it and/or modify it diff --git a/drivers/pwm/pwm-rockchip-i2s.c b/drivers/pwm/pwm-rockchip-i2s.c index 0888f62ab60a..391ebf1d755d 100644 --- a/drivers/pwm/pwm-rockchip-i2s.c +++ b/drivers/pwm/pwm-rockchip-i2s.c @@ -3,7 +3,7 @@ /* * PWM-I2S driver for Rockchip SoCs * - * Copyright (c) 2018 Rockchip Electronics Co. Ltd. + * Copyright (c) 2018 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 26a7986b6157..1808b1ddf6bb 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -3,7 +3,7 @@ * PWM driver for Rockchip SoCs * * Copyright (C) 2014 Beniamino Galvani - * Copyright (C) 2014 ROCKCHIP, Inc. + * Copyright (C) 2014 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/rtc/rtc-hym8563.c b/drivers/rtc/rtc-hym8563.c index 417c4ccc79e4..59759e26d476 100644 --- a/drivers/rtc/rtc-hym8563.c +++ b/drivers/rtc/rtc-hym8563.c @@ -6,7 +6,7 @@ * Author: Heiko Stuebner * * based on rtc-HYM8563 - * Copyright (C) 2010 ROCKCHIP, Inc. + * Copyright (C) 2010 Rockchip Electronics Co., Ltd. */ #include diff --git a/drivers/soc/rockchip/rk_dmabuf_procfs.c b/drivers/soc/rockchip/rk_dmabuf_procfs.c index 6d7fb31dfb2a..86c31aeae80d 100644 --- a/drivers/soc/rockchip/rk_dmabuf_procfs.c +++ b/drivers/soc/rockchip/rk_dmabuf_procfs.c @@ -10,6 +10,7 @@ #include #include #include +#include #define K(size) ((unsigned long)((size) >> 10)) static struct device *dmabuf_dev; @@ -59,6 +60,8 @@ static void rk_dmabuf_dump_sgt(const struct dma_buf *dmabuf, void *private) phys_addr_t end, len; int i; + dma_resv_lock(dmabuf->resv, NULL); + list_for_each_entry_safe(a, t, &dmabuf->attachments, node) { if (!a->sgt) continue; @@ -76,8 +79,12 @@ static void rk_dmabuf_dump_sgt(const struct dma_buf *dmabuf, void *private) (len >> 10) ? (K(len)) : (unsigned long)len, (len >> 10) ? "KiB" : "Bytes"); } + dma_resv_unlock(dmabuf->resv); return; } + + dma_resv_unlock(dmabuf->resv); + /* Try to attach and map the dmabufs without sgt. */ if (IS_ENABLED(CONFIG_RK_DMABUF_DEBUG_ADVANCED)) { struct dma_buf *dbuf = (struct dma_buf *)dmabuf; @@ -105,9 +112,11 @@ static int rk_dmabuf_cb3(const struct dma_buf *dmabuf, void *private) seq_printf(s, "%px %-16.16s %-16.16s %10lu KiB", dmabuf, dmabuf->name, dmabuf->exp_name, K(dmabuf->size)); + dma_resv_lock(dmabuf->resv, NULL); list_for_each_entry_safe(a, t, &dmabuf->attachments, node) { seq_printf(s, " %s", dev_name(a->dev)); } + dma_resv_unlock(dmabuf->resv); seq_puts(s, "\n"); return 0; diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index d4567b2e54c4..de41d7bfd566 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -2,7 +2,7 @@ /* * Rockchip Serial Flash Controller Driver * - * Copyright (c) 2017-2021, Rockchip Inc. + * Copyright (c) 2017-2021, Rockchip Electronics Co., Ltd. * Author: Shawn Lin * Chris Morgan * Jon Lin diff --git a/drivers/spi/spi-rockchip-slave.c b/drivers/spi/spi-rockchip-slave.c index 58377839db0f..7b12392b9481 100644 --- a/drivers/spi/spi-rockchip-slave.c +++ b/drivers/spi/spi-rockchip-slave.c @@ -2,7 +2,7 @@ /* * Rockchip SPI Slave Controller Driver * - * Copyright (c) 2023, Rockchip Inc. + * Copyright (c) 2023, Rockchip Electronics Co., Ltd. * Author: Jon Lin */ diff --git a/drivers/thermal/rk_virtual_thermal.c b/drivers/thermal/rk_virtual_thermal.c index d03c466e8b55..68627bd84862 100644 --- a/drivers/thermal/rk_virtual_thermal.c +++ b/drivers/thermal/rk_virtual_thermal.c @@ -1,7 +1,7 @@ /* * rk virtual tsadc driver * - * Copyright (C) 2017 Rockchip Electronics Co., Ltd + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. * Author: Rocky Hao * * This program is free software; you can redistribute it and/or modify it diff --git a/drivers/usb/typec/tcpm/tcpci_et7303.c b/drivers/usb/typec/tcpm/tcpci_et7303.c index f7302d1ed1b7..838329a18d81 100644 --- a/drivers/usb/typec/tcpm/tcpci_et7303.c +++ b/drivers/usb/typec/tcpm/tcpci_et7303.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2022 Rockchip Co.,Ltd. + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. * Author: Wang Jie * * Etek ET7303 Type-C Chip Driver diff --git a/drivers/usb/typec/tcpm/tcpci_husb311.c b/drivers/usb/typec/tcpm/tcpci_husb311.c index 20d91839a1bc..faed6b65fb70 100644 --- a/drivers/usb/typec/tcpm/tcpci_husb311.c +++ b/drivers/usb/typec/tcpm/tcpci_husb311.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2021 Rockchip Co.,Ltd. + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. * Author: Wang Jie * * Hynetek Husb311 Type-C Chip Driver diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c index 57f4c6327322..40061ff82497 100644 --- a/drivers/video/rockchip/rga/rga_drv.c +++ b/drivers/video/rockchip/rga/rga_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 ROCKCHIP, Inc. + * Copyright (C) 2012 Rockchip Electronics Co., Ltd. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/drivers/video/rockchip/rga2/rga2_drv.c b/drivers/video/rockchip/rga2/rga2_drv.c index f1cd65550537..87d185257b72 100644 --- a/drivers/video/rockchip/rga2/rga2_drv.c +++ b/drivers/video/rockchip/rga2/rga2_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 ROCKCHIP, Inc. + * Copyright (C) 2012 Rockchip Electronics Co., Ltd. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/drivers/video/rockchip/vtunnel/rkvtunnel.h b/drivers/video/rockchip/vtunnel/rkvtunnel.h index 1781aa785bc0..d173412115c4 100644 --- a/drivers/video/rockchip/vtunnel/rkvtunnel.h +++ b/drivers/video/rockchip/vtunnel/rkvtunnel.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #ifndef __ROCKCHIP_VIDEO_TUNNEL_H__ #define __ROCKCHIP_VIDEO_TUNNEL_H__ diff --git a/include/dt-bindings/clock/rockchip,rk3506-cru.h b/include/dt-bindings/clock/rockchip,rk3506-cru.h index 6d880fd8339a..9394f34093e3 100644 --- a/include/dt-bindings/clock/rockchip,rk3506-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3506-cru.h @@ -280,8 +280,9 @@ #define CLK_WIFI_OUT 281 #define CLK_V0PLL_REF 282 #define CLK_V1PLL_REF 283 +#define CLK_32K_FRAC_MUX 284 -#define CLK_NR_CLKS (CLK_V1PLL_REF + 1) +#define CLK_NR_CLKS (CLK_32K_FRAC_MUX + 1) /* soft-reset indices */ diff --git a/include/dt-bindings/soc/rockchip-csu.h b/include/dt-bindings/soc/rockchip-csu.h index 8b0442533c3f..1add02bd94e4 100644 --- a/include/dt-bindings/soc/rockchip-csu.h +++ b/include/dt-bindings/soc/rockchip-csu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2023 Rockchip Electronics Co. Ltd. + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. * Author: Finley Xiao */ diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h index 198641d92203..ff3163726fb0 100644 --- a/include/dt-bindings/soc/rockchip-system-status.h +++ b/include/dt-bindings/soc/rockchip-system-status.h @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2017 ROCKCHIP, Inc. + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/include/linux/clk/rockchip.h b/include/linux/clk/rockchip.h index 07c563a42c60..e3ac8322f1ca 100644 --- a/include/linux/clk/rockchip.h +++ b/include/linux/clk/rockchip.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. */ #ifndef __LINUX_CLK_ROCKCHIP_H_ diff --git a/include/linux/dma-buf-cache.h b/include/linux/dma-buf-cache.h index d97545560990..0cf3ec91fe6d 100644 --- a/include/linux/dma-buf-cache.h +++ b/include/linux/dma-buf-cache.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ #ifndef _LINUX_DMA_BUF_CACHE_H #define _LINUX_DMA_BUF_CACHE_H diff --git a/include/linux/mfd/max96745.h b/include/linux/mfd/max96745.h index 7eef5153a760..222dcbaca886 100644 --- a/include/linux/mfd/max96745.h +++ b/include/linux/mfd/max96745.h @@ -2,7 +2,7 @@ /* * Defining registers address and its bit definitions of MAX96745 * - * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #ifndef _MFD_MAX96745_H_ diff --git a/include/linux/mfd/max96755f.h b/include/linux/mfd/max96755f.h index 88bafca9609e..83d200ddb70f 100644 --- a/include/linux/mfd/max96755f.h +++ b/include/linux/mfd/max96755f.h @@ -2,7 +2,7 @@ /* * Defining registers address and its bit definitions of MAX96752F * - * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #ifndef _MFD_MAX96755F_H_ diff --git a/include/linux/mfd/rk618.h b/include/linux/mfd/rk618.h index 94525e1cb137..e957d8ab4c1c 100644 --- a/include/linux/mfd/rk618.h +++ b/include/linux/mfd/rk618.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Copyright (c) 2017 Rockchip Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/linux/mfd/rk630.h b/include/linux/mfd/rk630.h index 53c67e846f7c..e496813945c8 100644 --- a/include/linux/mfd/rk630.h +++ b/include/linux/mfd/rk630.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. * * Author: Algea Cao */ diff --git a/include/linux/mtd/bbt_store.h b/include/linux/mtd/bbt_store.h index 20373ef5c4a6..09b5de593302 100644 --- a/include/linux/mtd/bbt_store.h +++ b/include/linux/mtd/bbt_store.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * */ diff --git a/include/linux/platform_data/spi-rockchip.h b/include/linux/platform_data/spi-rockchip.h index 4b588739b5b6..47a2851e8bbe 100755 --- a/include/linux/platform_data/spi-rockchip.h +++ b/include/linux/platform_data/spi-rockchip.h @@ -1,6 +1,6 @@ /* include/linux/platform_data/spi-rockchip.h * - * Copyright (C) 2014 Rockchip Electronics Ltd. + * Copyright (C) 2014 Rockchip Electronics Co., Ltd. * luowei * * This program is free software; you can redistribute it and/or modify diff --git a/include/linux/power/cw2015_battery.h b/include/linux/power/cw2015_battery.h index 8e6b1fc7e344..87aff015a17a 100644 --- a/include/linux/power/cw2015_battery.h +++ b/include/linux/power/cw2015_battery.h @@ -1,7 +1,7 @@ /* * Fuel gauge driver for CellWise 2013 / 2015 * - * Copyright (C) 2012, RockChip + * Copyright (C) 2012, Rockchip Electronics Co., Ltd. * * Authors: xuhuicong * diff --git a/include/linux/rk-dma-heap.h b/include/linux/rk-dma-heap.h index e42bc227dd04..1d44bf139d72 100644 --- a/include/linux/rk-dma-heap.h +++ b/include/linux/rk-dma-heap.h @@ -4,7 +4,7 @@ * * Copyright (C) 2011 Google, Inc. * Copyright (C) 2019 Linaro Ltd. - * Copyright (C) 2022 Rockchip Electronics Co. Ltd. + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. * Author: Simon Xue */ diff --git a/include/linux/rk_hdmirx_class.h b/include/linux/rk_hdmirx_class.h index d3a3e434b030..780ab3f96919 100644 --- a/include/linux/rk_hdmirx_class.h +++ b/include/linux/rk_hdmirx_class.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * * Author: Dingxian Wen */ diff --git a/include/linux/rockchip-panel-notifier.h b/include/linux/rockchip-panel-notifier.h index 6fb90045ca7e..23bd2403be33 100644 --- a/include/linux/rockchip-panel-notifier.h +++ b/include/linux/rockchip-panel-notifier.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2024 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. * Author: Zhibin Huang */ diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index beaaf923f9ec..0cd6f673c4d9 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Rockchip Electronics Co. Ltd. + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as diff --git a/include/linux/sensor-dev.h b/include/linux/sensor-dev.h index a29d512ec0d1..e64676f2d967 100644 --- a/include/linux/sensor-dev.h +++ b/include/linux/sensor-dev.h @@ -1,6 +1,6 @@ /* include/linux/sensor-dev.h - sensor header file * - * Copyright (C) 2012-2015 ROCKCHIP. + * Copyright (C) 2012-2015 Rockchip Electronics Co., Ltd. * Author: luowei * * This software is licensed under the terms of the GNU General Public diff --git a/include/linux/soc/rockchip/rockchip_decompress.h b/include/linux/soc/rockchip/rockchip_decompress.h index 120ae907c2aa..9eb34f6d4ddd 100644 --- a/include/linux/soc/rockchip/rockchip_decompress.h +++ b/include/linux/soc/rockchip/rockchip_decompress.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright (c) 2020 Rockchip Electronics Co., Ltd */ +/* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */ #ifndef _ROCKCHIP_DECOMPRESS #define _ROCKCHIP_DECOMPRESS diff --git a/include/linux/soc/rockchip/rockchip_thunderboot_crypto.h b/include/linux/soc/rockchip/rockchip_thunderboot_crypto.h index 2fe176649409..166971d45284 100644 --- a/include/linux/soc/rockchip/rockchip_thunderboot_crypto.h +++ b/include/linux/soc/rockchip/rockchip_thunderboot_crypto.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright (c) 2021 Rockchip Electronics Co., Ltd */ +/* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ #ifndef _ROCKCHIP_THUNDERBOOT_CRYPTO_ #define _ROCKCHIP_THUNDERBOOT_CRYPTO_ diff --git a/include/linux/soc/rockchip/rockchip_thunderboot_service.h b/include/linux/soc/rockchip/rockchip_thunderboot_service.h index d0a08a07c21d..00f75f88b688 100644 --- a/include/linux/soc/rockchip/rockchip_thunderboot_service.h +++ b/include/linux/soc/rockchip/rockchip_thunderboot_service.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright (c) 2022 Rockchip Electronics Co., Ltd */ +/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */ #ifndef _ROCKCHIP_THUNDERBOOT_SERVICE_H #define _ROCKCHIP_THUNDERBOOT_SERVICE_H diff --git a/include/misc/rk_scr_api.h b/include/misc/rk_scr_api.h index 535e83a9183c..0b3dbdd6b615 100644 --- a/include/misc/rk_scr_api.h +++ b/include/misc/rk_scr_api.h @@ -1,7 +1,7 @@ /* * Driver for Rockchip Smart Card Reader Controller * - * Copyright (C) 2012-2016 ROCKCHIP, Inc. + * Copyright (C) 2012-2016 Rockchip Electronics Co., Ltd. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/include/uapi/linux/rk-dma-heap.h b/include/uapi/linux/rk-dma-heap.h index 4e83d71811ce..127b5cab6736 100644 --- a/include/uapi/linux/rk-dma-heap.h +++ b/include/uapi/linux/rk-dma-heap.h @@ -4,7 +4,7 @@ * * Copyright (C) 2011 Google, Inc. * Copyright (C) 2019 Linaro Ltd. - * Copyright (C) 2022 Rockchip Electronics Co. Ltd. + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. * Author: Simon Xue */ #ifndef _UAPI_LINUX_DMABUF_POOL_H diff --git a/include/uapi/misc/dw_hdcp2.h b/include/uapi/misc/dw_hdcp2.h index 43d4af3d80d6..b1a82368295c 100644 --- a/include/uapi/misc/dw_hdcp2.h +++ b/include/uapi/misc/dw_hdcp2.h @@ -2,7 +2,7 @@ /* * Rockchip HDCP Host Library driver * - * Copyright (C) 2022 Rockchip Electronics Co., Ltd + * Copyright (C) 2022 Rockchip Electronics Co., Ltd. */ #ifndef _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_ diff --git a/include/uapi/misc/rkflash_vendor_storage.h b/include/uapi/misc/rkflash_vendor_storage.h index c217380d1713..e4d604f81664 100644 --- a/include/uapi/misc/rkflash_vendor_storage.h +++ b/include/uapi/misc/rkflash_vendor_storage.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */ -/* Copyright (c) 2023 Rockchip Electronics Co., Ltd */ +/* Copyright (c) 2023 Rockchip Electronics Co., Ltd. */ #ifndef _RKFLASH_VENDOR_STORAGE #define _RKFLASH_VENDOR_STORAGE