From 5d239fb6bc913ed8ad2e4af12bc19fb5dbabb8e5 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 26 Jun 2025 09:08:29 +0800 Subject: [PATCH 01/25] arm64/configs: enable CONFIG_TOUCHSCREEN_HYN for rockchip_linux_defconfig For rk3576-evb. Change-Id: I229d9d4ba999f0458b4aa6c182376668445c1338 Signed-off-by: Caesar Wang --- arch/arm64/configs/rockchip_linux_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index eedfbfccffe8..6bd10a73cbb4 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -237,6 +237,7 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_GSL3673=y CONFIG_TOUCHSCREEN_GT1X=y +CONFIG_TOUCHSCREEN_HYN=y CONFIG_TOUCHSCREEN_ELAN=y CONFIG_TOUCHSCREEN_USB_COMPOSITE=y CONFIG_ROCKCHIP_REMOTECTL=y From a2f962c89f65425fb8303d4edd26f3abcd5612c5 Mon Sep 17 00:00:00 2001 From: William Wu Date: Thu, 26 Jun 2025 09:07:51 +0800 Subject: [PATCH 02/25] usb: xhci: Fix bogus hs bulk wMaxPacketSize value The commit e4f47e3675e6 ("USB: xHCI: override bogus bulk wMaxPacketSize values") said that some xHCI controllers can't handle a HS bulk endpoint having a wMaxPacketSize value smaller than 512, which is forbidden by the USB spec. And it changes the max_packet value to 512, which allows the controller to use the endpoint properly. Actually, the xHCI version 1.1 can support to handle a HS bulk endpoint having a wMaxPacketSize value smaller than 512, and some HS devices (e.g. USB Printer VID:PID= 0x154F:0x154F) bulk endpoints actually only support a maximum transmission of 64 bytes. If we changes the maximum packet value to 512, these devices are unable to receive data properly. So this patch allows xHCI controller above version 1.0 to support HS bulk max packet smaller than 512. Change-Id: Ic93efb890e1df2b3313d3cfc5dbbe602a7146b2e Signed-off-by: William Wu --- drivers/usb/host/xhci-mem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 88402cf424d1..f2e6f792bb02 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -1472,7 +1472,8 @@ int xhci_endpoint_init(struct xhci_hcd *xhci, err_count = 3; /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */ if (usb_endpoint_xfer_bulk(&ep->desc)) { - if (udev->speed == USB_SPEED_HIGH) + /* xHCI 1.1 can support HS bulk max packet smaller than 512 */ + if (udev->speed == USB_SPEED_HIGH && xhci->hci_version < 0x110) max_packet = 512; if (udev->speed == USB_SPEED_FULL) { max_packet = rounddown_pow_of_two(max_packet); From 8f80e1c7a32a6a3de6e375a1897a902b520d8aa7 Mon Sep 17 00:00:00 2001 From: Leo Sun Date: Wed, 25 Jun 2025 11:06:10 +0800 Subject: [PATCH 03/25] arm64: dts: rockchip: Update rv1126b-evb2-v10 to support dual camera configuration Change-Id: I80a07d6016f93e6245f422e2c6e39f1e9b557e3e Signed-off-by: Leo Sun --- .../dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi index 34e33d61fceb..4a73b4f86bf6 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb-dual-cam-4k.dtsi @@ -25,6 +25,12 @@ remote-endpoint = <&imx415_out0>; data-lanes = <1 2 3 4>; }; + + csi_dphy_input1: endpoint@2 { + reg = <2>; + remote-endpoint = <&sc850sl_out0>; + data-lanes = <1 2 3 4>; + }; }; port@1 { reg = <1>; @@ -55,6 +61,13 @@ remote-endpoint = <&imx415_out1>; data-lanes = <1 2 3 4>; }; + + csi_dphy3_input1: endpoint@2 { + reg = <2>; + remote-endpoint = <&sc850sl_out1>; + data-lanes = <1 2 3 4>; + }; + }; port@1 { reg = <1>; @@ -112,6 +125,55 @@ }; }; }; + + sc850sl_0: sc850sl_0@30 { + compatible = "smartsens,sc850sl"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_MIPI0_OUT2IO>; + clock-names = "xvclk"; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk0_pins>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + port { + sc850sl_out0: endpoint { + remote-endpoint = <&csi_dphy_input1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m3_pins>; + + sc850sl_1: sc850sl_1@30 { + compatible = "smartsens,sc850sl"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_MIPI2_OUT2IO>; + clock-names = "xvclk"; + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio5 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_pins>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + port { + sc850sl_out1: endpoint { + remote-endpoint = <&csi_dphy3_input1>; + data-lanes = <1 2 3 4>; + }; + }; + }; }; &mipi0_csi2 { From 04e18d5d237f55890ed5f3f61392d429ffeb76e1 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 23 Jun 2025 15:06:08 +0800 Subject: [PATCH 04/25] media: i2c: sc132gs fixes some error 1.fixes exposure range 2.add digital again support 3.update init setting 4.fixes testpattern operation error Change-Id: I8f6060965cfc994e555a169e437e106803970470 Signed-off-by: Zefa Chen --- drivers/media/i2c/sc132gs.c | 213 ++++++++++++++++++++++++------------ 1 file changed, 142 insertions(+), 71 deletions(-) diff --git a/drivers/media/i2c/sc132gs.c b/drivers/media/i2c/sc132gs.c index 627d050d5f36..4c9f48999009 100644 --- a/drivers/media/i2c/sc132gs.c +++ b/drivers/media/i2c/sc132gs.c @@ -50,21 +50,23 @@ #define SC132GS_MODE_SW_STANDBY 0x0 #define SC132GS_MODE_STREAMING BIT(0) -#define SC132GS_REG_EXPOSURE 0x3e01 -#define SC132GS_EXPOSURE_MIN 6 +#define SC132GS_REG_EXPOSURE 0x3e00 +#define SC132GS_EXPOSURE_MIN 1 #define SC132GS_EXPOSURE_STEP 1 #define SC132GS_VTS_MAX 0xffff #define SC132GS_REG_COARSE_AGAIN 0x3e08 #define SC132GS_REG_FINE_AGAIN 0x3e09 +#define SC132GS_REG_COARSE_DGAIN 0x3e06 +#define SC132GS_REG_FINE_DGAIN 0x3e07 + #define ANALOG_GAIN_MIN 0x20 -#define ANALOG_GAIN_MAX 0x391 +#define ANALOG_GAIN_MAX 0x6c80 #define ANALOG_GAIN_STEP 1 #define ANALOG_GAIN_DEFAULT 0x20 #define SC132GS_REG_TEST_PATTERN 0x4501 -#define SC132GS_TEST_PATTERN_ENABLE 0xcc -#define SC132GS_TEST_PATTERN_DISABLE 0xc4 +#define SC132GS_TEST_PATTERN_BIT_MASK BIT(3) #define SC132GS_REG_VTS 0x320e @@ -285,18 +287,18 @@ static const struct regval sc132gs_2lane_10bit_regs[] = { {0x3018, 0x32}, {0x3019, 0x0c}, {0x301a, 0xb4}, - {0x3031, 0x0a}, + {0x301f, 0x51}, {0x3032, 0x60}, {0x3038, 0x44}, {0x3207, 0x17}, - {0x320c, 0x05}, - {0x320d, 0xdc}, - {0x320e, 0x09}, - {0x320f, 0x60}, + {0x320c, 0x02}, + {0x320d, 0xee}, + {0x320e, 0x05}, + {0x320f, 0x78}, {0x3250, 0xcc}, {0x3251, 0x02}, - {0x3252, 0x09}, - {0x3253, 0x5b}, + {0x3252, 0x05}, + {0x3253, 0x73}, {0x3254, 0x05}, {0x3255, 0x3b}, {0x3306, 0x78}, @@ -331,18 +333,22 @@ static const struct regval sc132gs_2lane_10bit_regs[] = { {0x363b, 0x48}, {0x363c, 0x83}, {0x363d, 0x10}, - {0x36ea, 0x38}, - {0x36fa, 0x25}, - {0x36fb, 0x05}, - {0x36fd, 0x04}, + {0x36ea, 0x36}, + {0x36eb, 0x04}, + {0x36ec, 0x13}, + {0x36ed, 0x24}, + {0x36fa, 0x2b}, + {0x36fb, 0x1b}, + {0x36fc, 0x11}, + {0x36fd, 0x34}, {0x3900, 0x11}, {0x3901, 0x05}, {0x3902, 0xc5}, {0x3904, 0x04}, {0x3908, 0x91}, {0x391e, 0x00}, - {0x3e01, 0x11}, - {0x3e02, 0x20}, + {0x3e01, 0x4e}, + {0x3e02, 0xc0}, {0x3e09, 0x20}, {0x3e0e, 0xd2}, {0x3e14, 0xb0}, @@ -350,7 +356,7 @@ static const struct regval sc132gs_2lane_10bit_regs[] = { {0x3e26, 0x20}, {0x4418, 0x38}, {0x4503, 0x10}, - {0x4837, 0x21}, + {0x4837, 0x35}, {0x5000, 0x0e}, {0x540c, 0x51}, {0x550f, 0x38}, @@ -381,8 +387,13 @@ static const struct regval sc132gs_2lane_10bit_regs[] = { //{0x3221, ((0x3 << 1)|(0x3 << 5))}, //PLL set - {0x36e9, 0x20}, - {0x36f9, 0x24}, + {0x36e9, 0x54}, + {0x36f9, 0x50}, + {0x0100, 0x01}, + + //gain >= 2 + {0x33fa, 0x02}, + {0x3317, 0x14}, {REG_NULL, 0x00}, }; @@ -395,14 +406,14 @@ static const struct sc132gs_mode supported_modes[] = { .numerator = 10000, .denominator = 300000, }, - .exp_def = 0x0148, - .hts_def = 0x06a0, - .vts_def = 0x084a, + .exp_def = 0x04ec, + .hts_def = 0x02ee*2, + .vts_def = 0x0578, .link_freq_index = LINK_FREQ_180M_INDEX, .pixel_rate = PIXEL_RATE_WITH_180M, .reg_list = sc132gs_2lane_10bit_regs, .lanes = 2, - .bus_fmt = MEDIA_BUS_FMT_Y10_1X10, + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, }, { @@ -644,15 +655,19 @@ static int sc132gs_enum_frame_sizes(struct v4l2_subdev *sd, static int sc132gs_enable_test_pattern(struct sc132gs *sc132gs, u32 pattern) { - u32 val; + u32 val = 0; + int ret = 0; + ret = sc132gs_read_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN, + SC132GS_REG_VALUE_08BIT, &val); if (pattern) - val = (pattern - 1) | SC132GS_TEST_PATTERN_ENABLE; + val |= SC132GS_TEST_PATTERN_BIT_MASK; else - val = SC132GS_TEST_PATTERN_DISABLE; + val &= ~SC132GS_TEST_PATTERN_BIT_MASK; - return sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN, - SC132GS_REG_VALUE_08BIT, val); + ret |= sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN, + SC132GS_REG_VALUE_08BIT, val); + return ret; } static void sc132gs_get_module_inf(struct sc132gs *sc132gs, @@ -737,50 +752,75 @@ static long sc132gs_compat_ioctl32(struct v4l2_subdev *sd, static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain) { int ret = 0; - u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg; + u32 fine_again_reg, coarse_again_reg, fine_dgain_reg, coarse_dgain_reg; if (a_gain < 0x20) a_gain = 0x20; - if (a_gain > 0x391) - a_gain = 0x391; + if (a_gain > 0x6c80) + a_gain = 0x6c80; if (a_gain < 0x3a) {/*1x~1.813*/ - fine_again = a_gain; - coarse_again = 0x03; - fine_again_reg = fine_again & 0x3f; - coarse_again_reg = coarse_again & 0x3F; - if (fine_again_reg >= 0x39) - fine_again_reg = 0x39; - } else if (a_gain < 0x72) {/*1.813~3.568x*/ - fine_again = (a_gain - 0x3a) * 1000 / 1755 + 0x20; - coarse_again = 0x23; - if (fine_again > 0x3f) - fine_again = 0x3f; - fine_again_reg = fine_again & 0x3f; - coarse_again_reg = coarse_again & 0x3F; + fine_again_reg = a_gain; + coarse_again_reg = 0x03; + fine_dgain_reg = 0x80; + coarse_dgain_reg = 0x00; + } else if (a_gain < 0x74) {/*1.813~3.568x*/ + fine_again_reg = a_gain * 0x20 / 0x3a; + coarse_again_reg = 0x23; + fine_dgain_reg = 0x80; + coarse_dgain_reg = 0x00; } else if (a_gain < 0xe8) { /*3.568x~7.250x*/ - fine_again = (a_gain - 0x72) * 1000 / 3682 + 0x20; - coarse_again = 0x27; - if (fine_again > 0x3f) - fine_again = 0x3f; - fine_again_reg = fine_again & 0x3f; - coarse_again_reg = coarse_again & 0x3F; + fine_again_reg = a_gain * 0x20 / 0x74; + coarse_again_reg = 0x27; + fine_dgain_reg = 0x80; + coarse_dgain_reg = 0x00; } else if (a_gain < 0x1d0) { /*7.250x~14.5x*/ - fine_again = (a_gain - 0xe8) * 100 / 725 + 0x20; - coarse_again = 0x2f; - if (fine_again > 0x3f) - fine_again = 0x3f; - fine_again_reg = fine_again & 0x3f; - coarse_again_reg = coarse_again & 0x3F; - } else { /*14.5x~28.547*/ - fine_again = (a_gain - 0x1d0) * 1000 / 14047 + 0x20; - coarse_again = 0x3f; - if (fine_again > 0x3f) - fine_again = 0x3f; - fine_again_reg = fine_again & 0x3f; - coarse_again_reg = coarse_again & 0x3F; + fine_again_reg = a_gain * 0x20 / 0xe8; + coarse_again_reg = 0x2f; + fine_dgain_reg = 0x80; + coarse_dgain_reg = 0x00; + } else if (a_gain < 0x3a0) { /*14.5x~28.547x*/ + fine_again_reg = a_gain * 0x20 / 0x1d0; + coarse_again_reg = 0x3f; + fine_dgain_reg = 0x80; + coarse_dgain_reg = 0x00; + } else if (a_gain < 0x740) { /*again:28.547x, dgain: 1x~2x*/ + fine_again_reg = 0x3f ; + coarse_again_reg = 0x3f; + fine_dgain_reg = a_gain * 0x8 / 0x3a; + if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80; + else fine_dgain_reg = fine_dgain_reg & 0xfc; + coarse_dgain_reg = 0x00; + } else if (a_gain < 0xe80) { /*again:28.547x, dgain: 2x~4x*/ + fine_again_reg = 0x3f ; + coarse_again_reg = 0x3f; + fine_dgain_reg = a_gain * 0x8 / 0x74; + if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80; + else fine_dgain_reg = fine_dgain_reg & 0xfc; + coarse_dgain_reg = 0x01; + } else if (a_gain < 0x1d00) { /*again:28.547x, dgain: 4x~8x*/ + fine_again_reg = 0x3f ; + coarse_again_reg = 0x3f; + fine_dgain_reg = a_gain * 0x8 / 0xe8; + if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80; + else fine_dgain_reg = fine_dgain_reg & 0xfc; + coarse_dgain_reg = 0x03; + } else if (a_gain < 0x3a00) { /*again:28.547x, dgain: 8x~16x*/ + fine_again_reg = 0x3f ; + coarse_again_reg = 0x3f; + fine_dgain_reg = a_gain * 0x8 / 0x1d0; + if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80; + else fine_dgain_reg = fine_dgain_reg & 0xfc; + coarse_dgain_reg = 0x07; + } else { /*again:28.547x, dgain: 16x~31.5x*/ + fine_again_reg = 0x3f ; + coarse_again_reg = 0x3f; + fine_dgain_reg = a_gain * 0x8 / 0x3a0; + if(fine_dgain_reg < 0x80) fine_dgain_reg =0x80; + else fine_dgain_reg = fine_dgain_reg & 0xfc; + coarse_dgain_reg = 0x0f; } - ret |= sc132gs_write_reg(sc132gs->client, + ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_COARSE_AGAIN, SC132GS_REG_VALUE_08BIT, coarse_again_reg); @@ -788,6 +828,34 @@ static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain) SC132GS_REG_FINE_AGAIN, SC132GS_REG_VALUE_08BIT, fine_again_reg); + ret |= sc132gs_write_reg(sc132gs->client, + SC132GS_REG_COARSE_DGAIN, + SC132GS_REG_VALUE_08BIT, + coarse_dgain_reg); + ret |= sc132gs_write_reg(sc132gs->client, + SC132GS_REG_FINE_DGAIN, + SC132GS_REG_VALUE_08BIT, + fine_dgain_reg); + if (a_gain < 0x40) { + ret |= sc132gs_write_reg(sc132gs->client, + 0x33fa, + SC132GS_REG_VALUE_08BIT, + 0x01); + ret |= sc132gs_write_reg(sc132gs->client, + 0x3317, + SC132GS_REG_VALUE_08BIT, + 0xf0); + } else { + ret |= sc132gs_write_reg(sc132gs->client, + 0x33fa, + SC132GS_REG_VALUE_08BIT, + 0x02); + ret |= sc132gs_write_reg(sc132gs->client, + 0x3317, + SC132GS_REG_VALUE_08BIT, + 0x0a); + } + return ret; } @@ -1110,7 +1178,7 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_VBLANK: /* Update max exposure while meeting expected vblanking */ - max = sc132gs->cur_mode->height + ctrl->val - 6; + max = sc132gs->cur_mode->height + ctrl->val - 8; __v4l2_ctrl_modify_range(sc132gs->exposure, sc132gs->exposure->minimum, max, sc132gs->exposure->step, @@ -1125,10 +1193,13 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_EXPOSURE: /* 4 least significant bits of expsoure are fractional part */ ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_EXPOSURE, - SC132GS_REG_VALUE_16BIT, ctrl->val << 4); + SC132GS_REG_VALUE_24BIT, ctrl->val << 4); + + dev_dbg(&client->dev, "set exposure 0x%x \n",ctrl->val); break; case V4L2_CID_ANALOGUE_GAIN: ret = sc132gs_set_ctrl_gain(sc132gs, ctrl->val); + dev_dbg(&client->dev, "set gain 0x%x \n",ctrl->val); break; case V4L2_CID_VBLANK: ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_VTS, @@ -1136,8 +1207,8 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + sc132gs->cur_mode->height); if (!ret) sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height; - sc132gs_modify_fps_info(sc132gs); - break; + if (sc132gs->cur_vts != sc132gs->cur_mode->vts_def) + sc132gs_modify_fps_info(sc132gs); break; case V4L2_CID_TEST_PATTERN: ret = sc132gs_enable_test_pattern(sc132gs, ctrl->val); @@ -1195,7 +1266,7 @@ static int sc132gs_initialize_controls(struct sc132gs *sc132gs) SC132GS_VTS_MAX - mode->height, 1, vblank_def); - exposure_max = mode->vts_def - 6; + exposure_max = mode->vts_def - 8; sc132gs->exposure = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops, V4L2_CID_EXPOSURE, SC132GS_EXPOSURE_MIN, exposure_max, SC132GS_EXPOSURE_STEP, From ed3b40c176dca1129a98e277d7beacb78927cc00 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 23 Jun 2025 17:12:20 +0800 Subject: [PATCH 05/25] media: i2c: sc132gs support mirror/flip control Change-Id: I5add66d64ce0cab347f9ba2e79e286bdc99b7060 Signed-off-by: Zefa Chen --- drivers/media/i2c/sc132gs.c | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/sc132gs.c b/drivers/media/i2c/sc132gs.c index 4c9f48999009..af3c82d0603f 100644 --- a/drivers/media/i2c/sc132gs.c +++ b/drivers/media/i2c/sc132gs.c @@ -70,6 +70,10 @@ #define SC132GS_REG_VTS 0x320e +#define SC132GS_FLIP_REG 0x3221 +#define SC132GS_HFLIP_MASK 0x06 +#define SC132GS_VFLIP_MASK 0x60 + #define REG_NULL 0xFFFF #define SC132GS_REG_VALUE_08BIT 1 @@ -133,6 +137,8 @@ struct sc132gs { struct v4l2_ctrl *test_pattern; struct v4l2_ctrl *pixel_rate; struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; struct mutex mutex; struct v4l2_fract cur_fps; u32 cur_vts; @@ -143,6 +149,7 @@ struct sc132gs { const char *module_facing; const char *module_name; const char *len_name; + u8 flip; }; #define to_sc132gs(sd) container_of(sd, struct sc132gs, subdev) @@ -380,11 +387,6 @@ static const struct regval sc132gs_2lane_10bit_regs[] = { //flip //{0x3221, (0x3 << 5)}, - //mirror - {0x3221, (0x3 << 1)}, - - //flip & mirror - //{0x3221, ((0x3 << 1)|(0x3 << 5))}, //PLL set {0x36e9, 0x54}, @@ -1193,7 +1195,7 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_EXPOSURE: /* 4 least significant bits of expsoure are fractional part */ ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_EXPOSURE, - SC132GS_REG_VALUE_24BIT, ctrl->val << 4); + SC132GS_REG_VALUE_24BIT, ctrl->val << 4); dev_dbg(&client->dev, "set exposure 0x%x \n",ctrl->val); break; @@ -1213,6 +1215,23 @@ static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_TEST_PATTERN: ret = sc132gs_enable_test_pattern(sc132gs, ctrl->val); break; + case V4L2_CID_HFLIP: + if (ctrl->val) + sc132gs->flip |= SC132GS_HFLIP_MASK; + else + sc132gs->flip &= ~SC132GS_HFLIP_MASK; + ret = sc132gs_write_reg(sc132gs->client, SC132GS_FLIP_REG, + SC132GS_REG_VALUE_08BIT, sc132gs->flip); + break; + case V4L2_CID_VFLIP: + if (ctrl->val) + sc132gs->flip |= SC132GS_VFLIP_MASK; + else + sc132gs->flip &= ~SC132GS_VFLIP_MASK; + + ret = sc132gs_write_reg(sc132gs->client, SC132GS_FLIP_REG, + SC132GS_REG_VALUE_08BIT, sc132gs->flip); + break; default: dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", __func__, ctrl->id, ctrl->val); @@ -1281,7 +1300,12 @@ static int sc132gs_initialize_controls(struct sc132gs *sc132gs) &sc132gs_ctrl_ops, V4L2_CID_TEST_PATTERN, ARRAY_SIZE(sc132gs_test_pattern_menu) - 1, 0, 0, sc132gs_test_pattern_menu); + sc132gs->flip = 0; + sc132gs->h_flip = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + sc132gs->v_flip = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); if (handler->error) { ret = handler->error; dev_err(&sc132gs->client->dev, From d08f47a2c49f5cb20654a68045c4be7e7dd70ea4 Mon Sep 17 00:00:00 2001 From: Leo Sun Date: Wed, 25 Jun 2025 11:09:17 +0800 Subject: [PATCH 06/25] arm64: dts: rockchip: add rv1126b-evb2-v10-aov-dual-cam.dts and update Makefile Change-Id: I397cfb1f76954c380c241b965f5839e4ecce8bc8 Signed-off-by: Leo Sun --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rv1126b-evb2-v10-aov-dual-cam.dts | 182 ++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 582d6362ad8d..7e2701be1746 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -385,6 +385,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nand.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts new file mode 100644 index 000000000000..6cec649318d1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126b.dtsi" +#include "rv1126b-evb.dtsi" +#include "rv1126b-evb2-v10.dtsi" +#include "rv1126b-evb-dual-cam-4k.dtsi" + +/ { + model = "Rockchip RV1126B EVB2 V10 Board"; + compatible = "rockchip,rv1126b-evb2-v10", "rockchip,rv1126b"; +}; + +&rockchip_suspend { + status = "okay"; + + rockchip,sleep-pin-config = < + (0 + | RKPM_SLEEP_PIN0_EN + ) + (0 + | RKPM_SLEEP_PIN0_ACT_LOW + ) + >; + + rockchip,sleep-io-config = < + /* pmic_sleep */ + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(0) + ) + /* reset */ + #if 0 + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_NONE + | RKPM_IO_CFG_ID(1) + ) + #endif + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(2) + ) + (0 + | RKPM_IO_CFG_PULL_NONE + | RKPM_IO_CFG_ID(3) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_UP + | RKPM_IO_CFG_ID(4) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(5) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(6) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_UP + | RKPM_IO_CFG_ID(7) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(8) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(9) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(10) + ) + /* uart0 tx */ + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(11) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(12) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(16) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(17) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_NONE + | RKPM_IO_CFG_ID(18) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_NONE + | RKPM_IO_CFG_ID(19) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(20) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(21) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(22) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(23) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(24) + ) + (0 + | RKPM_IO_CFG_IOMUX_GPIO + | RKPM_IO_CFG_GPIO_DIR_INPUT + | RKPM_IO_CFG_PULL_DOWN + | RKPM_IO_CFG_ID(25) + ) + >; +}; + +&sc850sl_0 { + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-stb = <1>; +}; + +&sc850sl_1 { + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-stb = <1>; +}; From 4f3c5c6bc794b93e52957bb23653cdf817336c17 Mon Sep 17 00:00:00 2001 From: Zhibin Huang Date: Thu, 26 Jun 2025 11:42:44 +0800 Subject: [PATCH 07/25] arm64: dts: rockchip: Add hyn touchscreen support Type: Function Redmine ID: #N/A Associated modifications: I649a447919003574d907b83b10ba3fd7496ad492 Test: N/A Signed-off-by: Zhibin Huang Change-Id: I310e7bf9f743accd3bc9b1f26c30a6b4fc3cd3c7 --- .../dts/rockchip/rk3562-dictpen-test3-v20.dts | 36 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi | 39 +++++++++++++++++++ .../dts/rockchip/rk3562-iotest-lp3-v10.dtsi | 39 +++++++++++++++++++ .../dts/rockchip/rk3562-test1-ddr3-v10.dtsi | 39 +++++++++++++++++++ .../boot/dts/rockchip/rk3562-toybrick.dtsi | 39 +++++++++++++++++++ .../dts/rockchip/rk3566-evb-mipitest-v10.dtsi | 5 +++ .../dts/rockchip/rk3566-evb1-ddr4-v10.dtsi | 4 ++ .../rockchip/rk3566-evb2-lp4x-v10-eink.dts | 4 ++ .../dts/rockchip/rk3566-evb2-lp4x-v10.dtsi | 4 ++ .../dts/rockchip/rk3566-evb3-ddr3-v10.dtsi | 4 ++ .../dts/rockchip/rk3566-evb5-lp4x-v10.dtsi | 4 ++ .../dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi | 4 ++ .../rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts | 7 ++++ ...k3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts | 4 ++ .../rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts | 4 ++ .../rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts | 4 ++ ...3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts | 4 ++ .../rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts | 7 ++++ .../rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts | 4 ++ .../rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts | 4 ++ .../rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts | 4 ++ ...k3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts | 4 ++ arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi | 34 ++++++++++++++++ .../dts/rockchip/rk3568-evb1-ddr4-v10.dtsi | 4 ++ .../dts/rockchip/rk3568-evb2-lp4x-v10.dtsi | 4 ++ .../dts/rockchip/rk3568-evb5-ddr4-v10.dtsi | 4 ++ .../dts/rockchip/rk3568-evb6-ddr3-v10.dtsi | 4 ++ .../rk3568-toybrick-sd0-mipi-tx0.dtsi | 35 +++++++++++++++++ .../rk3568m-serdes-evb-lp4x-v10-camera.dtsi | 4 ++ .../rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi | 4 ++ .../rk3568m-serdes-v1-evb-lp4x-v10.dtsi | 4 ++ .../dts/rockchip/rk3576-toybrick-d0-linux.dts | 36 +++++++++++++++++ .../rk3588-evb1-lp4-v10-ipc-6x-linux.dts | 4 ++ .../boot/dts/rockchip/rk3588-evb1-lp4.dtsi | 35 +++++++++++++++++ .../arm64/boot/dts/rockchip/rk3588-evb10.dtsi | 35 +++++++++++++++++ .../dts/rockchip/rk3588-evb2-lp4-v10-edp.dts | 4 ++ .../boot/dts/rockchip/rk3588-evb2-lp4.dtsi | 35 +++++++++++++++++ .../rk3588-evb3-lp5-v10-edp-linux.dts | 4 ++ .../dts/rockchip/rk3588-evb3-lp5-v10-edp.dts | 4 ++ .../boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rk3588-evb4-lp4.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rk3588-evb6-lp4.dtsi | 35 +++++++++++++++++ ...k3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts | 4 ++ .../boot/dts/rockchip/rk3588-evb7-lp4.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rk3588-evb7-v11.dtsi | 34 ++++++++++++++++ .../dts/rockchip/rk3588-toybrick-edp-x0.dtsi | 35 ++++++++++++++++- .../boot/dts/rockchip/rk3588-toybrick-x0.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rk3588s-evb2-lp5.dtsi | 35 +++++++++++++++++ ...s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts | 6 ++- .../boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rv1126b-evb1-v10.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rv1126b-evb2-v10.dtsi | 35 +++++++++++++++++ .../boot/dts/rockchip/rv1126b-evb3-v10.dts | 35 +++++++++++++++++ .../boot/dts/rockchip/rv1126b-evb4-v10.dts | 37 ++++++++++++++++++ .../boot/dts/rockchip/rv1126bp-evb-v14.dtsi | 37 ++++++++++++++++++ 56 files changed, 1057 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts index e18343ba125c..c631038130d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts @@ -919,6 +919,26 @@ power-supply = <&vcc3v3_lcd>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + + power-supply = <&vcc3v3_lcd>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c5 { @@ -1012,6 +1032,22 @@ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; sdio-pwrseq { diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi index c1ac45ec00fd..df67dca3040f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi @@ -505,6 +505,29 @@ */ power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &jpegd { @@ -526,6 +549,22 @@ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi index 7f2c5fcdaab8..e8b8c8dc0851 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi @@ -492,6 +492,29 @@ */ power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &pinctrl { @@ -507,6 +530,22 @@ <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi index 5bd49a130bc3..79282069e7f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi @@ -227,6 +227,29 @@ power-supply = <&vcc3v3_lcd_n>; }; +&hynitron { + compatible = "hyn,3240"; + reg = <0x5a>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; +}; + &mdio0 { rgmii_phy: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -262,6 +285,22 @@ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi index 14c5526e0fcb..fc2310a87cf2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi @@ -293,6 +293,29 @@ interrupts = ; wakeup-source; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mdio0 { @@ -342,6 +365,22 @@ <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; sdio-pwrseq { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi index 243eb085e9a4..3f8fb74c453e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi @@ -227,6 +227,11 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + status = "disabled"; + power-supply = <&vcc3v3_lcd0_n>; +}; + &hdmi { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi index bf0e166e339f..9a288ee6b9b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi @@ -226,6 +226,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c2 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts index 83546eef6529..a44590ab8155 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts @@ -150,6 +150,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &hdmi { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi index 79e607fa8217..af4e4d32b9c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi @@ -405,6 +405,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &mipi_csi2 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi index 0a7e2881d1fe..bf781f1cb92b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi @@ -188,6 +188,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c2 { status = "okay"; pinctrl-0 = <&i2c2m1_xfer>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi index 82e4775c1a2f..2870d4d3dabd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi @@ -172,6 +172,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c5 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi index 2394736f85f0..a826ede074fc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi @@ -396,6 +396,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &mipi_csi2 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts index 93b3082315da..ceb7191ec0ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts @@ -15,6 +15,13 @@ goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; }; +&hynitron { + status = "okay"; + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts index 672a92e58fc5..617723eb0c3d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts @@ -12,6 +12,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts index 6fb57aa5aaef..2550c72e6081 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts @@ -16,6 +16,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts index 8623a53f1f75..ec9deefa68ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts @@ -12,6 +12,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts index f0c391a82ff4..7ba8b7e342dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts @@ -16,6 +16,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts index 93bed18b809e..9c17e6b83a6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts @@ -46,6 +46,13 @@ goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; }; +&hynitron { + status = "okay"; + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts index 42fa4a5ffd91..33e95593bfa8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts @@ -47,6 +47,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts index 16d185cb7ad6..2678e89d812f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts @@ -15,6 +15,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { assigned-clocks = <&pmucru CLK_WIFI>; assigned-clock-rates = <24000000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts index bb24a93a3e82..5e0699d21460 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts @@ -47,6 +47,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts index be6c3984dc46..92ae266f5cab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts @@ -48,6 +48,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c2_rk628 { panel-backlight = <&backlight>; panel-power-supply = <&vcc3v3_lcd0_n>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi index f2da0b2e62ea..e3d818840247 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi @@ -1380,6 +1380,24 @@ goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c5 { @@ -1496,6 +1514,22 @@ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; sdio-pwrseq { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi index 2b72b8c7bbe5..630c5cd30309 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi @@ -263,6 +263,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c4 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi index 81b2de38a5a3..7be9312f1650 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi @@ -211,6 +211,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c3 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi index ceaf0f2b841d..ce1f22676747 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi @@ -264,6 +264,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c3 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi index 894fdc0ab3c8..630a49c1b0f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi @@ -111,6 +111,10 @@ power-supply = <&vcc3v3_lcd0_n>; }; +&hynitron { + power-supply = <&vcc3v3_lcd0_n>; +}; + &i2c2 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi index 7dbcf6439898..f4e5f89ca58f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi @@ -45,6 +45,25 @@ goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + status = "okay"; + reg = <0x5a>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &pwm14{ @@ -72,5 +91,21 @@ <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi index 199c55ce54bf..f1d7201b5568 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi @@ -44,6 +44,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &combphy0_us { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi index 78cb019fe9be..17f5a7a21e2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi @@ -49,6 +49,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi index 5e2b2f976ae8..cef8cc061679 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi @@ -49,6 +49,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-toybrick-d0-linux.dts b/arch/arm64/boot/dts/rockchip/rk3576-toybrick-d0-linux.dts index ca214d45edf3..ee6cb6106179 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-toybrick-d0-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-toybrick-d0-linux.dts @@ -714,6 +714,26 @@ goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + status = "okay"; + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c1 { @@ -1210,6 +1230,22 @@ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts index 2dcef191fc6b..adbe1a4294a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts @@ -83,6 +83,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c6 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi index ea7c8ea9d2ea..f38fb8c68d77 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi @@ -496,6 +496,25 @@ goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c7 { @@ -634,6 +653,22 @@ <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi index 7040968053c0..18c3294dd347 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi @@ -503,6 +503,25 @@ goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c5m3_xfer { @@ -795,6 +814,22 @@ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts index 9ea50364c627..634d35783b4e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts @@ -118,6 +118,10 @@ status = "okay"; }; +&hynitron { + status = "disabled"; +}; + &i2c6 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi index ec9136eebd35..ac62b180d2b0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi @@ -328,6 +328,25 @@ goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c7 { @@ -436,6 +455,22 @@ <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts index 9d27fbfc65c3..3d011f58cea6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts @@ -87,6 +87,10 @@ status = "okay"; }; +&hynitron { + status = "disabled"; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts index a5ee38a637ec..b622daf68e0d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts @@ -87,6 +87,10 @@ status = "okay"; }; +&hynitron { + status = "disabled"; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi index 3603c268182d..5b4d853c17a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi @@ -984,6 +984,25 @@ goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c7 { @@ -1103,6 +1122,22 @@ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi index ef5dd89975c4..d1177ce60787 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi @@ -268,6 +268,25 @@ goodix,irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c8 { @@ -383,6 +402,22 @@ <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi index 96b7406c9b3a..d60040f0807a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi @@ -341,6 +341,25 @@ goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2s5_8ch { @@ -418,6 +437,22 @@ <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts index fc23e31ffc21..8cf01c534961 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts @@ -87,6 +87,10 @@ status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c6 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi index 140343f69dea..bfec0c0b8d73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi @@ -549,6 +549,25 @@ goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c6 { @@ -707,6 +726,22 @@ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi index fac0f509bfdd..ed86fb00503d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi @@ -560,6 +560,24 @@ goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c6 { @@ -774,6 +792,22 @@ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi index 1dbb39cd381e..a38a0cd167f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi @@ -518,6 +518,24 @@ irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c7 { @@ -649,6 +667,22 @@ <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { @@ -767,4 +801,3 @@ &usbhost_dwc3_0 { status = "disabled"; }; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi index 3faa4db1d86a..7d04434be324 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi @@ -519,6 +519,25 @@ irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c7 { @@ -622,6 +641,22 @@ <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi index 5c07f761dcd9..1e19254cc005 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi @@ -813,6 +813,25 @@ goodix,irq-gpio = <&gpio4 RK_PB4 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c3 { @@ -892,6 +911,22 @@ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts index 4a03bc67aeb1..008940c5ba75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts @@ -20,12 +20,16 @@ }; /* - * The pins of gt1x and sii9022 are multiplexed + * The pins of gt1x/hynitron and sii9022 are multiplexed */ >1x { status = "disabled"; }; +&hynitron { + status = "disabled"; +}; + &i2c4 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi index cfdbcae8cbe8..c88013addb27 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi @@ -152,6 +152,25 @@ goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c8 { @@ -253,6 +272,22 @@ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb-typec { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi index a5ca242779af..8cfbba940433 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi @@ -494,6 +494,25 @@ goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; power-supply = <&vcc3v3_lcd_n>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc3v3_lcd_n>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &i2c5 { @@ -688,6 +707,22 @@ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi index 6786b6565a98..d789d93b60ef 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi @@ -319,6 +319,25 @@ goodix,rst-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio7 RK_PA6 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc_mipi>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio7 RK_PA6 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mdio { @@ -368,6 +387,22 @@ <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi index 7f9cbcbc70b8..8d3f4f1f4d2d 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10.dtsi @@ -301,6 +301,25 @@ goodix,rst-gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio3 RK_PB7 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc_lcd>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mdio { @@ -340,6 +359,22 @@ <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts index ddbbf9406da5..503e4ba33b52 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb3-v10.dts @@ -324,6 +324,25 @@ goodix,rst-gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio3 RK_PB7 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc_mipi>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mipi2_csi2 { @@ -485,6 +504,22 @@ <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; + + ts_int_active: ts_int_active { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; usb { diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb4-v10.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb4-v10.dts index 5088c15904cf..3344c5ec2793 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-evb4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb4-v10.dts @@ -362,6 +362,25 @@ goodix,rst-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc_mipi>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mdio { @@ -405,6 +424,24 @@ }; }; + touch { + ts_int_active: ts_int_active { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + usb { typec5v_pwren: typec5v-pwren { rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi b/arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi index ac666ae9e19c..a7f557374acd 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126bp-evb-v14.dtsi @@ -424,6 +424,25 @@ goodix,rst-gpio = <&gpio5 RK_PA4 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio5 RK_PA6 IRQ_TYPE_LEVEL_LOW>; }; + + hynitron: hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + power-supply = <&vcc_mipi>; + + pinctrl-names = "ts_active","ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpios = <&gpio5 RK_PA4 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio5 RK_PA6 GPIO_ACTIVE_LOW>; + + max-touch-number = <5>; + display-coords = <0 0 1080 1920>; + pos-swap = <0>; + posx-reverse = <0>; + posy-reverse = <0>; + }; }; &mdio { @@ -457,6 +476,24 @@ }; }; + touch { + ts_int_active: ts_int_active { + rockchip,pins = <5 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_reset_active: ts_reset_active { + rockchip,pins = <5 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + ts_int_suspend: ts_int_suspend { + rockchip,pins = <5 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ts_reset_suspend: ts_reset_suspend { + rockchip,pins = <5 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + wireless-bluetooth { uart2_gpios: uart2-gpios { rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; From 7bdbb62d0fc2fcd19bfb0e5c3144909ac6ca8106 Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Thu, 26 Jun 2025 19:14:13 +0800 Subject: [PATCH 08/25] mfd: display-serdes: Add support for max96749 Change-Id: I983bad88dcf06b1d7b00d091e033fe41b7b11277 Signed-off-by: Zitong Cai --- drivers/mfd/display-serdes/core.h | 2 + drivers/mfd/display-serdes/gpio.h | 30 + drivers/mfd/display-serdes/maxim/Kconfig | 6 + drivers/mfd/display-serdes/maxim/Makefile | 1 + .../mfd/display-serdes/maxim/maxim-max96749.c | 1028 +++++++++++++++++ .../mfd/display-serdes/maxim/maxim-max96749.h | 146 +++ .../mfd/display-serdes/serdes-bridge-split.c | 1 + drivers/mfd/display-serdes/serdes-bridge.c | 1 + drivers/mfd/display-serdes/serdes-core.c | 19 + drivers/mfd/display-serdes/serdes-gpio.c | 1 + drivers/mfd/display-serdes/serdes-i2c.c | 5 + drivers/mfd/display-serdes/serdes-pinctrl.c | 11 + 12 files changed, 1251 insertions(+) create mode 100644 drivers/mfd/display-serdes/maxim/maxim-max96749.c create mode 100644 drivers/mfd/display-serdes/maxim/maxim-max96749.h diff --git a/drivers/mfd/display-serdes/core.h b/drivers/mfd/display-serdes/core.h index f51c7d8e609e..b905cbdc79b8 100644 --- a/drivers/mfd/display-serdes/core.h +++ b/drivers/mfd/display-serdes/core.h @@ -404,6 +404,7 @@ struct serdes { struct kthread_delayed_work reg_check_work; bool use_reg_check_work; + bool dual_link; bool split_mode_enable; unsigned int reg_hw; unsigned int reg_use; @@ -459,6 +460,7 @@ void serdes_destroy_debugfs(struct serdes *serdes); extern struct serdes_chip_data serdes_bu18tl82_data; extern struct serdes_chip_data serdes_bu18rl82_data; extern struct serdes_chip_data serdes_max96745_data; +extern struct serdes_chip_data serdes_max96749_data; extern struct serdes_chip_data serdes_max96752_data; extern struct serdes_chip_data serdes_max96755_data; extern struct serdes_chip_data serdes_max96772_data; diff --git a/drivers/mfd/display-serdes/gpio.h b/drivers/mfd/display-serdes/gpio.h index 404e86354607..bb87511eb63f 100644 --- a/drivers/mfd/display-serdes/gpio.h +++ b/drivers/mfd/display-serdes/gpio.h @@ -43,6 +43,7 @@ enum serdes_id { ROHM_ID_BU18RL82, MAXIM_ID_MAX96745, + MAXIM_ID_MAX96749, MAXIM_ID_MAX96752, MAXIM_ID_MAX96755, MAXIM_ID_MAX96772, @@ -107,6 +108,35 @@ enum max96745_gpio_list { MAXIM_MAX96745_MFP25, }; +enum max96749_gpio_list { + MAXIM_MAX96749_MFP0 = 0, + MAXIM_MAX96749_MFP1, + MAXIM_MAX96749_MFP2, + MAXIM_MAX96749_MFP3, + MAXIM_MAX96749_MFP4, + MAXIM_MAX96749_MFP5, + MAXIM_MAX96749_MFP6, + MAXIM_MAX96749_MFP7, + MAXIM_MAX96749_MFP8, + MAXIM_MAX96749_MFP9, + MAXIM_MAX96749_MFP10, + MAXIM_MAX96749_MFP11, + MAXIM_MAX96749_MFP12, + MAXIM_MAX96749_MFP13, + MAXIM_MAX96749_MFP14, + MAXIM_MAX96749_MFP15, + MAXIM_MAX96749_MFP16, + MAXIM_MAX96749_MFP17, + MAXIM_MAX96749_MFP18, + MAXIM_MAX96749_MFP19, + MAXIM_MAX96749_MFP20, + MAXIM_MAX96749_MFP21, + MAXIM_MAX96749_MFP22, + MAXIM_MAX96749_MFP23, + MAXIM_MAX96749_MFP24, + MAXIM_MAX96749_MFP25, +}; + enum max96752_gpio_list { MAXIM_MAX96752_GPIO0 = 0, MAXIM_MAX96752_GPIO1, diff --git a/drivers/mfd/display-serdes/maxim/Kconfig b/drivers/mfd/display-serdes/maxim/Kconfig index e889dcd0bf82..fe34367ae86d 100644 --- a/drivers/mfd/display-serdes/maxim/Kconfig +++ b/drivers/mfd/display-serdes/maxim/Kconfig @@ -17,6 +17,12 @@ config SERDES_DISPLAY_CHIP_MAXIM_MAX96745 help To support maxim max96745 display serdes. +config SERDES_DISPLAY_CHIP_MAXIM_MAX96749 + tristate "maxim max96749 serdes" + default y + help + To support maxim max96749 display serdes. + config SERDES_DISPLAY_CHIP_MAXIM_MAX96752 tristate "maxim max96752 serdes" default y diff --git a/drivers/mfd/display-serdes/maxim/Makefile b/drivers/mfd/display-serdes/maxim/Makefile index 349233deda38..9fade01a4049 100644 --- a/drivers/mfd/display-serdes/maxim/Makefile +++ b/drivers/mfd/display-serdes/maxim/Makefile @@ -3,6 +3,7 @@ # maxim display serdes drivers configuration # obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745) += maxim-max96745.o +obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749) += maxim-max96749.o obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752) += maxim-max96752.o obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755) += maxim-max96755.o obj-$(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772) += maxim-max96772.o diff --git a/drivers/mfd/display-serdes/maxim/maxim-max96749.c b/drivers/mfd/display-serdes/maxim/maxim-max96749.c new file mode 100644 index 000000000000..0c9de2ace88d --- /dev/null +++ b/drivers/mfd/display-serdes/maxim/maxim-max96749.c @@ -0,0 +1,1028 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * maxim-max96749.c -- I2C register interface access for max96749 serdes chip + * + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: ZITONG CAI + */ + +#include "../core.h" +#include "maxim-max96749.h" + +static bool max96749_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x0076: + case 0x0086: + case 0x0100: + case 0x0200 ... 0x02ce: + case 0x7000: + case 0x7070: + case 0x7074: + return false; + default: + return true; + } +} + +static struct regmap_config max96749_regmap_config = { + .name = "max96749", + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x8000, + .volatile_reg = max96749_volatile_reg, + .cache_type = REGCACHE_RBTREE, +}; + +struct serdes_function_data { + u8 gpio_out_dis:1; + u8 gpio_io_rx_en:1; + u8 gpio_tx_en_a:1; + u8 gpio_tx_en_b:1; + u8 gpio_rx_en_a:1; + u8 gpio_rx_en_b:1; + u8 gpio_tx_id; + u8 gpio_rx_id; +}; + +struct config_desc { + u16 reg; + u8 mask; + u8 val; +}; + +struct serdes_group_data { + const struct config_desc *configs; + int num_configs; +}; + +static int MAX96749_MFP0_pins[] = {0}; +static int MAX96749_MFP1_pins[] = {1}; +static int MAX96749_MFP2_pins[] = {2}; +static int MAX96749_MFP3_pins[] = {3}; +static int MAX96749_MFP4_pins[] = {4}; +static int MAX96749_MFP5_pins[] = {5}; +static int MAX96749_MFP6_pins[] = {6}; +static int MAX96749_MFP7_pins[] = {7}; + +static int MAX96749_MFP8_pins[] = {8}; +static int MAX96749_MFP9_pins[] = {9}; +static int MAX96749_MFP10_pins[] = {10}; +static int MAX96749_MFP11_pins[] = {11}; +static int MAX96749_MFP12_pins[] = {12}; +static int MAX96749_MFP13_pins[] = {13}; +static int MAX96749_MFP14_pins[] = {14}; +static int MAX96749_MFP15_pins[] = {15}; + +static int MAX96749_MFP16_pins[] = {16}; +static int MAX96749_MFP17_pins[] = {17}; +static int MAX96749_MFP18_pins[] = {18}; +static int MAX96749_MFP19_pins[] = {19}; +static int MAX96749_MFP20_pins[] = {20}; +static int MAX96749_MFP21_pins[] = {21}; +static int MAX96749_MFP22_pins[] = {22}; +static int MAX96749_MFP23_pins[] = {23}; + +static int MAX96749_MFP24_pins[] = {24}; +static int MAX96749_MFP25_pins[] = {25}; +static int MAX96749_I2C_pins[] = {3, 7}; +static int MAX96749_UART_pins[] = {3, 7}; + +#define GROUP_DESC(nm) \ +{ \ + .name = #nm, \ + .pins = nm ## _pins, \ + .num_pins = ARRAY_SIZE(nm ## _pins), \ +} + +static const char * const serdes_gpio_groups[] = { + "MAX96749_MFP0", "MAX96749_MFP1", "MAX96749_MFP2", "MAX96749_MFP3", + "MAX96749_MFP4", "MAX96749_MFP5", "MAX96749_MFP6", "MAX96749_MFP7", + + "MAX96749_MFP8", "MAX96749_MFP9", "MAX96749_MFP10", "MAX96749_MFP11", + "MAX96749_MFP12", "MAX96749_MFP13", "MAX96749_MFP14", "MAX96749_MFP15", + + "MAX96749_MFP16", "MAX96749_MFP17", "MAX96749_MFP18", "MAX96749_MFP19", + "MAX96749_MFP20", "MAX96749_MFP21", "MAX96749_MFP22", "MAX96749_MFP23", + + "MAX96749_MFP24", "MAX96749_MFP25", +}; + +static const char *MAX96749_I2C_groups[] = { "MAX96749_I2C" }; +static const char *MAX96749_UART_groups[] = { "MAX96749_UART" }; + +#define FUNCTION_DESC(nm) \ +{ \ + .name = #nm, \ + .group_names = nm##_groups, \ + .num_group_names = ARRAY_SIZE(nm##_groups), \ +} \ + +#define FUNCTION_DESC_GPIO_OUTPUT_A(id) \ +{ \ + .name = "SER_TXID"#id"_TO_DES_LINKA", \ + .group_names = serdes_gpio_groups, \ + .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ + .data = (void *)(const struct serdes_function_data []) { \ + { .gpio_out_dis = 1, .gpio_tx_en_a = 1, \ + .gpio_io_rx_en = 1, .gpio_tx_id = id } \ + }, \ +} \ + +#define FUNCTION_DESC_GPIO_OUTPUT_B(id) \ +{ \ + .name = "SER_TXID"#id"_TO_DES_LINKB", \ + .group_names = serdes_gpio_groups, \ + .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ + .data = (void *)(const struct serdes_function_data []) { \ + { .gpio_out_dis = 1, .gpio_tx_en_b = 1, \ + .gpio_io_rx_en = 1, .gpio_tx_id = id } \ + }, \ +} \ + +#define FUNCTION_DESC_GPIO_INPUT_A(id) \ +{ \ + .name = "DES_RXID"#id"_TO_SER_LINKA", \ + .group_names = serdes_gpio_groups, \ + .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ + .data = (void *)(const struct serdes_function_data []) { \ + { .gpio_rx_en_a = 1, .gpio_rx_id = id } \ + }, \ +} \ + +#define FUNCTION_DESC_GPIO_INPUT_B(id) \ +{ \ + .name = "DES_RXID"#id"_TO_SER_LINKB", \ + .group_names = serdes_gpio_groups, \ + .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ + .data = (void *)(const struct serdes_function_data []) { \ + { .gpio_rx_en_b = 1, .gpio_rx_id = id } \ + }, \ +} \ + +#define FUNCTION_DESC_GPIO() \ +{ \ + .name = "MAX96749_GPIO", \ + .group_names = serdes_gpio_groups, \ + .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \ + .data = (void *)(const struct serdes_function_data []) { \ + { } \ + }, \ +} \ + +static struct pinctrl_pin_desc max96749_pins_desc[] = { + PINCTRL_PIN(MAXIM_MAX96749_MFP0, "MAX96749_MFP0"), + PINCTRL_PIN(MAXIM_MAX96749_MFP1, "MAX96749_MFP1"), + PINCTRL_PIN(MAXIM_MAX96749_MFP2, "MAX96749_MFP2"), + PINCTRL_PIN(MAXIM_MAX96749_MFP3, "MAX96749_MFP3"), + PINCTRL_PIN(MAXIM_MAX96749_MFP4, "MAX96749_MFP4"), + PINCTRL_PIN(MAXIM_MAX96749_MFP5, "MAX96749_MFP5"), + PINCTRL_PIN(MAXIM_MAX96749_MFP6, "MAX96749_MFP6"), + PINCTRL_PIN(MAXIM_MAX96749_MFP7, "MAX96749_MFP7"), + + PINCTRL_PIN(MAXIM_MAX96749_MFP8, "MAX96749_MFP8"), + PINCTRL_PIN(MAXIM_MAX96749_MFP9, "MAX96749_MFP9"), + PINCTRL_PIN(MAXIM_MAX96749_MFP10, "MAX96749_MFP10"), + PINCTRL_PIN(MAXIM_MAX96749_MFP11, "MAX96749_MFP11"), + PINCTRL_PIN(MAXIM_MAX96749_MFP12, "MAX96749_MFP12"), + PINCTRL_PIN(MAXIM_MAX96749_MFP13, "MAX96749_MFP13"), + PINCTRL_PIN(MAXIM_MAX96749_MFP14, "MAX96749_MFP14"), + PINCTRL_PIN(MAXIM_MAX96749_MFP15, "MAX96749_MFP15"), + + PINCTRL_PIN(MAXIM_MAX96749_MFP16, "MAX96749_MFP16"), + PINCTRL_PIN(MAXIM_MAX96749_MFP17, "MAX96749_MFP17"), + PINCTRL_PIN(MAXIM_MAX96749_MFP18, "MAX96749_MFP18"), + PINCTRL_PIN(MAXIM_MAX96749_MFP19, "MAX96749_MFP19"), + PINCTRL_PIN(MAXIM_MAX96749_MFP20, "MAX96749_MFP20"), + PINCTRL_PIN(MAXIM_MAX96749_MFP21, "MAX96749_MFP21"), + PINCTRL_PIN(MAXIM_MAX96749_MFP22, "MAX96749_MFP22"), + PINCTRL_PIN(MAXIM_MAX96749_MFP23, "MAX96749_MFP23"), + + PINCTRL_PIN(MAXIM_MAX96749_MFP24, "MAX96749_MFP24"), + PINCTRL_PIN(MAXIM_MAX96749_MFP25, "MAX96749_MFP25"), +}; + +static struct group_desc max96749_groups_desc[] = { + GROUP_DESC(MAX96749_MFP0), + GROUP_DESC(MAX96749_MFP1), + GROUP_DESC(MAX96749_MFP2), + GROUP_DESC(MAX96749_MFP3), + GROUP_DESC(MAX96749_MFP4), + GROUP_DESC(MAX96749_MFP5), + GROUP_DESC(MAX96749_MFP6), + GROUP_DESC(MAX96749_MFP7), + + GROUP_DESC(MAX96749_MFP8), + GROUP_DESC(MAX96749_MFP9), + GROUP_DESC(MAX96749_MFP10), + GROUP_DESC(MAX96749_MFP11), + GROUP_DESC(MAX96749_MFP12), + GROUP_DESC(MAX96749_MFP13), + GROUP_DESC(MAX96749_MFP14), + GROUP_DESC(MAX96749_MFP15), + + GROUP_DESC(MAX96749_MFP16), + GROUP_DESC(MAX96749_MFP17), + GROUP_DESC(MAX96749_MFP18), + GROUP_DESC(MAX96749_MFP19), + GROUP_DESC(MAX96749_MFP20), + GROUP_DESC(MAX96749_MFP21), + GROUP_DESC(MAX96749_MFP22), + GROUP_DESC(MAX96749_MFP23), + + GROUP_DESC(MAX96749_MFP24), + GROUP_DESC(MAX96749_MFP25), + + GROUP_DESC(MAX96749_I2C), + GROUP_DESC(MAX96749_UART), +}; + +static struct function_desc max96749_functions_desc[] = { + FUNCTION_DESC_GPIO_INPUT_A(0), + FUNCTION_DESC_GPIO_INPUT_A(1), + FUNCTION_DESC_GPIO_INPUT_A(2), + FUNCTION_DESC_GPIO_INPUT_A(3), + FUNCTION_DESC_GPIO_INPUT_A(4), + FUNCTION_DESC_GPIO_INPUT_A(5), + FUNCTION_DESC_GPIO_INPUT_A(6), + FUNCTION_DESC_GPIO_INPUT_A(7), + + FUNCTION_DESC_GPIO_INPUT_A(8), + FUNCTION_DESC_GPIO_INPUT_A(9), + FUNCTION_DESC_GPIO_INPUT_A(10), + FUNCTION_DESC_GPIO_INPUT_A(11), + FUNCTION_DESC_GPIO_INPUT_A(12), + FUNCTION_DESC_GPIO_INPUT_A(13), + FUNCTION_DESC_GPIO_INPUT_A(14), + FUNCTION_DESC_GPIO_INPUT_A(15), + + FUNCTION_DESC_GPIO_INPUT_A(16), + FUNCTION_DESC_GPIO_INPUT_A(17), + FUNCTION_DESC_GPIO_INPUT_A(18), + FUNCTION_DESC_GPIO_INPUT_A(19), + FUNCTION_DESC_GPIO_INPUT_A(20), + FUNCTION_DESC_GPIO_INPUT_A(21), + FUNCTION_DESC_GPIO_INPUT_A(22), + FUNCTION_DESC_GPIO_INPUT_A(23), + + FUNCTION_DESC_GPIO_INPUT_A(24), + FUNCTION_DESC_GPIO_INPUT_A(25), + + FUNCTION_DESC_GPIO_OUTPUT_A(0), + FUNCTION_DESC_GPIO_OUTPUT_A(1), + FUNCTION_DESC_GPIO_OUTPUT_A(2), + FUNCTION_DESC_GPIO_OUTPUT_A(3), + FUNCTION_DESC_GPIO_OUTPUT_A(4), + FUNCTION_DESC_GPIO_OUTPUT_A(5), + FUNCTION_DESC_GPIO_OUTPUT_A(6), + FUNCTION_DESC_GPIO_OUTPUT_A(7), + + FUNCTION_DESC_GPIO_OUTPUT_A(8), + FUNCTION_DESC_GPIO_OUTPUT_A(9), + FUNCTION_DESC_GPIO_OUTPUT_A(10), + FUNCTION_DESC_GPIO_OUTPUT_A(11), + FUNCTION_DESC_GPIO_OUTPUT_A(12), + FUNCTION_DESC_GPIO_OUTPUT_A(13), + FUNCTION_DESC_GPIO_OUTPUT_A(14), + FUNCTION_DESC_GPIO_OUTPUT_A(15), + + FUNCTION_DESC_GPIO_OUTPUT_A(16), + FUNCTION_DESC_GPIO_OUTPUT_A(17), + FUNCTION_DESC_GPIO_OUTPUT_A(18), + FUNCTION_DESC_GPIO_OUTPUT_A(19), + FUNCTION_DESC_GPIO_OUTPUT_A(20), + FUNCTION_DESC_GPIO_OUTPUT_A(21), + FUNCTION_DESC_GPIO_OUTPUT_A(22), + FUNCTION_DESC_GPIO_OUTPUT_A(23), + + FUNCTION_DESC_GPIO_OUTPUT_A(24), + FUNCTION_DESC_GPIO_OUTPUT_A(25), + + FUNCTION_DESC_GPIO_INPUT_B(0), + FUNCTION_DESC_GPIO_INPUT_B(1), + FUNCTION_DESC_GPIO_INPUT_B(2), + FUNCTION_DESC_GPIO_INPUT_B(3), + FUNCTION_DESC_GPIO_INPUT_B(4), + FUNCTION_DESC_GPIO_INPUT_B(5), + FUNCTION_DESC_GPIO_INPUT_B(6), + FUNCTION_DESC_GPIO_INPUT_B(7), + + FUNCTION_DESC_GPIO_INPUT_B(8), + FUNCTION_DESC_GPIO_INPUT_B(9), + FUNCTION_DESC_GPIO_INPUT_B(10), + FUNCTION_DESC_GPIO_INPUT_B(11), + FUNCTION_DESC_GPIO_INPUT_B(12), + FUNCTION_DESC_GPIO_INPUT_B(13), + FUNCTION_DESC_GPIO_INPUT_B(14), + FUNCTION_DESC_GPIO_INPUT_B(15), + + FUNCTION_DESC_GPIO_INPUT_B(16), + FUNCTION_DESC_GPIO_INPUT_B(17), + FUNCTION_DESC_GPIO_INPUT_B(18), + FUNCTION_DESC_GPIO_INPUT_B(19), + FUNCTION_DESC_GPIO_INPUT_B(20), + FUNCTION_DESC_GPIO_INPUT_B(21), + FUNCTION_DESC_GPIO_INPUT_B(22), + FUNCTION_DESC_GPIO_INPUT_B(23), + + FUNCTION_DESC_GPIO_INPUT_B(24), + FUNCTION_DESC_GPIO_INPUT_B(25), + + FUNCTION_DESC_GPIO_OUTPUT_B(0), + FUNCTION_DESC_GPIO_OUTPUT_B(1), + FUNCTION_DESC_GPIO_OUTPUT_B(2), + FUNCTION_DESC_GPIO_OUTPUT_B(3), + FUNCTION_DESC_GPIO_OUTPUT_B(4), + FUNCTION_DESC_GPIO_OUTPUT_B(5), + FUNCTION_DESC_GPIO_OUTPUT_B(6), + FUNCTION_DESC_GPIO_OUTPUT_B(7), + + FUNCTION_DESC_GPIO_OUTPUT_B(8), + FUNCTION_DESC_GPIO_OUTPUT_B(9), + FUNCTION_DESC_GPIO_OUTPUT_B(10), + FUNCTION_DESC_GPIO_OUTPUT_B(11), + FUNCTION_DESC_GPIO_OUTPUT_B(12), + FUNCTION_DESC_GPIO_OUTPUT_B(13), + FUNCTION_DESC_GPIO_OUTPUT_B(14), + FUNCTION_DESC_GPIO_OUTPUT_B(15), + + FUNCTION_DESC_GPIO_OUTPUT_B(16), + FUNCTION_DESC_GPIO_OUTPUT_B(17), + FUNCTION_DESC_GPIO_OUTPUT_B(18), + FUNCTION_DESC_GPIO_OUTPUT_B(19), + FUNCTION_DESC_GPIO_OUTPUT_B(20), + FUNCTION_DESC_GPIO_OUTPUT_B(21), + FUNCTION_DESC_GPIO_OUTPUT_B(22), + FUNCTION_DESC_GPIO_OUTPUT_B(23), + + FUNCTION_DESC_GPIO_OUTPUT_B(24), + FUNCTION_DESC_GPIO_OUTPUT_B(25), + + FUNCTION_DESC_GPIO(), + + FUNCTION_DESC(MAX96749_I2C), + FUNCTION_DESC(MAX96749_UART), +}; + +static struct serdes_chip_pinctrl_info max96749_pinctrl_info = { + .pins = max96749_pins_desc, + .num_pins = ARRAY_SIZE(max96749_pins_desc), + .groups = max96749_groups_desc, + .num_groups = ARRAY_SIZE(max96749_groups_desc), + .functions = max96749_functions_desc, + .num_functions = ARRAY_SIZE(max96749_functions_desc), +}; + +static bool max96749_vid_tx_active(struct serdes *serdes) +{ + u32 val; + int i = 0, ret = 0; + + for (i = 0; i < 5; i++) { + ret = serdes_reg_read(serdes, 0x0107, &val); + if (!ret) + break; + + SERDES_DBG_CHIP("serdes %s: false val=%d i=%d ret=%d\n", __func__, val, i, ret); + msleep(20); + } + + if (ret) { + SERDES_DBG_CHIP("serdes %s: false val=%d ret=%d\n", __func__, val, ret); + return false; + } + + if (!FIELD_GET(VID_TX_ACTIVE_A | VID_TX_ACTIVE_B, val)) { + SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val); + return false; + } + + return true; +} + +static int max96749_bridge_init(struct serdes *serdes) +{ + if (max96749_vid_tx_active(serdes)) { + extcon_set_state(serdes->extcon, EXTCON_JACK_VIDEO_OUT, true); + pr_info("serdes %s, extcon is true state=%d\n", __func__, serdes->extcon->state); + } else { + pr_info("serdes %s, extcon is false\n", __func__); + } + + return 0; +} + +static bool max96749_bridge_link_locked(struct serdes *serdes) +{ + u32 val = 0, i; + + if (serdes->lock_gpio) { + for (i = 0; i < 3; i++) { + val = gpiod_get_value_cansleep(serdes->lock_gpio); + if (val) + break; + msleep(20); + } + + SERDES_DBG_CHIP("%s:%s-%s, gpio %s\n", __func__, dev_name(serdes->dev), + serdes->chip_data->name, (val) ? "locked" : "unlocked"); + if (val) + return true; + } + + if (serdes_reg_read(serdes, 0x0013, &val)) { + SERDES_DBG_CHIP("serdes %s: unlocked val=0x%x\n", __func__, val); + return false; + } + + if (!FIELD_GET(LOCKED, val)) { + SERDES_DBG_CHIP("serdes %s: unlocked val=0x%x\n", __func__, val); + return false; + } + + SERDES_DBG_CHIP("%s: serdes reg locked 0x%x\n", __func__, val); + + return true; +} + +static int max96749_select(struct serdes *serdes, int link) +{ + int ret; + u32 i, status; + struct serdes *deser; + struct drm_panel *panel; + struct serdes_panel *serdes_panel; + + /*0076 for linkA and 0086 for linkB*/ + if (link == SER_DUAL_LINK) { + panel = serdes->serdes_bridge->panel; + serdes_panel = container_of(panel, struct serdes_panel, panel); + deser = serdes_panel->parent; + + serdes_reg_write(deser, 0x10, 0x00); + serdes_set_bits(serdes, 0x45, DUAL_LINK_MODE, + FIELD_PREP(DUAL_LINK_MODE, 1)); + serdes_set_bits(serdes, 0x0076, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + serdes_set_bits(serdes, 0x0086, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + SERDES_DBG_CHIP("%s: serdes %s change to use dual link\n", + __func__, serdes->chip_data->name); + } else if (link == SER_LINKA) { + serdes_set_bits(serdes, 0x0076, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + serdes_set_bits(serdes, 0x0086, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 1)); + SERDES_DBG_CHIP("%s: only enable %s remote i2c of linkA\n", __func__, + serdes->chip_data->name); + } else if (link == SER_LINKB) { + serdes_set_bits(serdes, 0x0076, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 1)); + serdes_set_bits(serdes, 0x0086, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + SERDES_DBG_CHIP("%s: only enable %s remote i2c of linkB\n", __func__, + serdes->chip_data->name); + } else if (link == SER_SPLITTER_MODE) { + serdes_set_bits(serdes, 0x0076, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + serdes_set_bits(serdes, 0x0086, DIS_REM_CC, + FIELD_PREP(DIS_REM_CC, 0)); + SERDES_DBG_CHIP("%s: enable %s remote i2c of linkA and linkB\n", __func__, + serdes->chip_data->name); + } + + for (i = 0; i < 80; i++) { + mdelay(5); + ret = serdes_reg_read(serdes, 0x0021, &status); + if (ret) + continue; + + if (serdes->dual_link && link != SER_DUAL_LINK) + return 0; + + switch (link) { + case SER_DUAL_LINK: + case SER_SPLITTER_MODE: + if ((status & LINKA_LOCKED) && + (status & LINKB_LOCKED)) + goto out; + break; + case SER_LINKA: + if (status & LINKA_LOCKED) + goto out; + break; + case SER_LINKB: + if (status & LINKB_LOCKED) + goto out; + break; + } + } + + dev_info(serdes->dev, "%s: link lock timeout, mode=%d val=0x%x\n", + __func__, link, status); + return -1; + +out: + dev_info(serdes->dev, "%s: link locked, mode=%d, val=0x%x\n", + __func__, link, status); + + return 0; +} + +static int max96749_deselect(struct serdes *serdes, int link) +{ + struct serdes *deser; + struct drm_panel *panel; + struct serdes_panel *serdes_panel; + struct serdes_bridge *serdes_bridge = serdes->serdes_bridge; + + if (link == SER_DUAL_LINK) { + panel = serdes_bridge->panel; + serdes_panel = container_of(panel, struct serdes_panel, panel); + deser = serdes_panel->parent; + + serdes_reg_write(deser, 0x10, 0x00); + serdes_set_bits(serdes, 0x45, DUAL_LINK_MODE, + FIELD_PREP(DUAL_LINK_MODE, 0)); + + SERDES_DBG_CHIP("%s: serdes %s disable dual link\n", __func__, + serdes->chip_data->name); + + } + + return 0; +} + +static struct serdes_chip_split_ops max96749_split_ops = { + .select = max96749_select, + .deselect = max96749_deselect, +}; + +static int max96749_bridge_attach(struct serdes *serdes) +{ + int ret; + enum drm_connector_status status; + + if (max96749_bridge_link_locked(serdes)) + status = connector_status_connected; + else { + status = connector_status_disconnected; + if (serdes->dual_link) { + dev_info(serdes->dev, "serdes disconnect, try to change dual link\n"); + + ret = max96749_select(serdes, SER_DUAL_LINK); + if (ret) { + dev_info(serdes->dev, "serdes disconnect, close dual link\n"); + max96749_deselect(serdes, SER_DUAL_LINK); + } else { + status = connector_status_connected; + } + } + } + + serdes->serdes_bridge->status = status; + + return 0; +} + +static enum drm_connector_status +max96749_bridge_detect(struct serdes *serdes) +{ + struct serdes_bridge *serdes_bridge = serdes->serdes_bridge; + enum drm_connector_status status = connector_status_connected; + + if (!drm_kms_helper_is_poll_worker()) + return serdes_bridge->status; + + if (!max96749_bridge_link_locked(serdes)) { + status = connector_status_disconnected; + goto out; + } + + if (extcon_get_state(serdes->extcon, EXTCON_JACK_VIDEO_OUT)) { + u32 dprx_trn_status2; + + if (atomic_cmpxchg(&serdes_bridge->triggered, 1, 0)) { + status = connector_status_disconnected; + SERDES_DBG_CHIP("1 status=%d state=%d\n", status, serdes->extcon->state); + goto out; + } + + if (serdes_reg_read(serdes, 0x641a, &dprx_trn_status2)) { + status = connector_status_disconnected; + SERDES_DBG_CHIP("2 status=%d state=%d\n", status, serdes->extcon->state); + goto out; + } + + if ((dprx_trn_status2 & DPRX_TRAIN_STATE) != DPRX_TRAIN_STATE) { + dev_err(serdes->dev, "Training State: 0x%lx\n", + FIELD_GET(DPRX_TRAIN_STATE, dprx_trn_status2)); + status = connector_status_disconnected; + SERDES_DBG_CHIP("3 status=%d state=%d\n", status, serdes->extcon->state); + goto out; + } + } else { + atomic_set(&serdes_bridge->triggered, 0); + SERDES_DBG_CHIP("4 status=%d state=%d\n", status, serdes->extcon->state); + } + + if (serdes_bridge->next_bridge && (serdes_bridge->next_bridge->ops & DRM_BRIDGE_OP_DETECT)) + return drm_bridge_detect(serdes_bridge->next_bridge); + +out: + serdes_bridge->status = status; + SERDES_DBG_CHIP("%s:%s %s, status=%d state=%d\n", __func__, dev_name(serdes->dev), + serdes->chip_data->name, + status, serdes->extcon->state); + return status; +} + +static int max96749_bridge_pre_enable(struct serdes *serdes) +{ + int ret = 0; + struct serdes_bridge *serdes_bridge = serdes->serdes_bridge; + + if (serdes->dual_link) { + ret = max96749_select(serdes, SER_DUAL_LINK); + if (ret) + atomic_set(&serdes_bridge->triggered, 1); + } + + SERDES_DBG_CHIP("%s: serdes chip %s ret=%d\n", __func__, serdes->chip_data->name, ret); + return ret; +} + +static int max96749_bridge_enable(struct serdes *serdes) +{ + int ret = 0; + + return ret; +} + +static int max96749_bridge_disable(struct serdes *serdes) +{ + int ret = 0; + + if (serdes->dual_link) + max96749_deselect(serdes, SER_DUAL_LINK); + + SERDES_DBG_CHIP("%s: serdes chip %s ret=%d\n", __func__, serdes->chip_data->name, ret); + return ret; +} + +static int max96749_bridge_post_disable(struct serdes *serdes) +{ + int ret = 0; + + return ret; +} + +static struct serdes_chip_bridge_ops max96749_bridge_ops = { + .init = max96749_bridge_init, + .attach = max96749_bridge_attach, + .detect = max96749_bridge_detect, + .pre_enable = max96749_bridge_pre_enable, + .enable = max96749_bridge_enable, + .disable = max96749_bridge_disable, + .post_disable = max96749_bridge_post_disable, +}; + +static int max96749_pinctrl_set_mux(struct serdes *serdes, + unsigned int function, unsigned int group) +{ + struct serdes_pinctrl *pinctrl = serdes->pinctrl; + struct function_desc *func; + struct group_desc *grp; + int i; + + func = pinmux_generic_get_function(pinctrl->pctl, function); + if (!func) + return -EINVAL; + + grp = pinctrl_generic_get_group(pinctrl->pctl, group); + if (!grp) + return -EINVAL; + + SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n", + __func__, serdes->chip_data->name, + func->name, func->data, grp->name, grp->data, grp->num_pins); + + if (func->data) { + struct serdes_function_data *data = func->data; + + for (i = 0; i < grp->num_pins; i++) { + serdes_set_bits(serdes, + GPIO_A_REG(grp->pins[i] - pinctrl->pin_base), + GPIO_OUT_DIS, + FIELD_PREP(GPIO_OUT_DIS, data->gpio_out_dis)); + serdes_set_bits(serdes, + GPIO_B_REG(grp->pins[i] - pinctrl->pin_base), + OUT_TYPE, + FIELD_PREP(OUT_TYPE, 1)); + if (data->gpio_tx_en_a || data->gpio_tx_en_b) + serdes_set_bits(serdes, + GPIO_B_REG(grp->pins[i] - pinctrl->pin_base), + GPIO_TX_ID, + FIELD_PREP(GPIO_TX_ID, data->gpio_tx_id)); + if (data->gpio_rx_en_a || data->gpio_rx_en_b) + serdes_set_bits(serdes, + GPIO_C_REG(grp->pins[i] - pinctrl->pin_base), + GPIO_RX_ID, + FIELD_PREP(GPIO_RX_ID, data->gpio_rx_id)); + serdes_set_bits(serdes, + GPIO_D_REG(grp->pins[i] - pinctrl->pin_base), + GPIO_TX_EN_A | GPIO_TX_EN_B | GPIO_IO_RX_EN | + GPIO_RX_EN_A | GPIO_RX_EN_B, + FIELD_PREP(GPIO_TX_EN_A, data->gpio_tx_en_a) | + FIELD_PREP(GPIO_TX_EN_B, data->gpio_tx_en_b) | + FIELD_PREP(GPIO_RX_EN_A, data->gpio_rx_en_a) | + FIELD_PREP(GPIO_RX_EN_B, data->gpio_rx_en_b) | + FIELD_PREP(GPIO_IO_RX_EN, data->gpio_io_rx_en)); + } + } + + return 0; +} + +static int max96749_pinctrl_config_get(struct serdes *serdes, + unsigned int pin, unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int gpio_a_reg, gpio_b_reg; + u16 arg = 0; + + serdes_reg_read(serdes, GPIO_A_REG(pin), &gpio_a_reg); + serdes_reg_read(serdes, GPIO_B_REG(pin), &gpio_b_reg); + + SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", + __func__, serdes->chip_data->name, pin, param); + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (FIELD_GET(OUT_TYPE, gpio_b_reg)) + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!FIELD_GET(OUT_TYPE, gpio_b_reg)) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_DISABLE: + if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1) + return -EINVAL; + switch (FIELD_GET(RES_CFG, gpio_a_reg)) { + case 0: + arg = 40000; + break; + case 1: + arg = 10000; + break; + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2) + return -EINVAL; + switch (FIELD_GET(RES_CFG, gpio_a_reg)) { + case 0: + arg = 40000; + break; + case 1: + arg = 10000; + break; + } + break; + case PIN_CONFIG_OUTPUT: + if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg)) + return -EINVAL; + + arg = FIELD_GET(GPIO_OUT, gpio_a_reg); + break; + default: + return -EOPNOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int max96749_pinctrl_config_set(struct serdes *serdes, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + enum pin_config_param param; + u32 arg; + u8 res_cfg; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__, + serdes->chip_data->name, pin, param); + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + serdes_set_bits(serdes, GPIO_B_REG(pin), + OUT_TYPE, FIELD_PREP(OUT_TYPE, 0)); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + serdes_set_bits(serdes, GPIO_B_REG(pin), + OUT_TYPE, FIELD_PREP(OUT_TYPE, 1)); + break; + case PIN_CONFIG_BIAS_DISABLE: + serdes_set_bits(serdes, GPIO_C_REG(pin), + PULL_UPDN_SEL, + FIELD_PREP(PULL_UPDN_SEL, 0)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + switch (arg) { + case 40000: + res_cfg = 0; + break; + case 1000000: + res_cfg = 1; + break; + default: + return -EINVAL; + } + + serdes_set_bits(serdes, GPIO_A_REG(pin), + RES_CFG, FIELD_PREP(RES_CFG, res_cfg)); + serdes_set_bits(serdes, GPIO_C_REG(pin), + PULL_UPDN_SEL, + FIELD_PREP(PULL_UPDN_SEL, 1)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + switch (arg) { + case 40000: + res_cfg = 0; + break; + case 1000000: + res_cfg = 1; + break; + default: + return -EINVAL; + } + + serdes_set_bits(serdes, GPIO_A_REG(pin), + RES_CFG, FIELD_PREP(RES_CFG, res_cfg)); + serdes_set_bits(serdes, GPIO_C_REG(pin), + PULL_UPDN_SEL, + FIELD_PREP(PULL_UPDN_SEL, 2)); + break; + case PIN_CONFIG_OUTPUT: + serdes_set_bits(serdes, GPIO_A_REG(pin), + GPIO_OUT_DIS | GPIO_OUT, + FIELD_PREP(GPIO_OUT_DIS, 0) | + FIELD_PREP(GPIO_OUT, arg)); + break; + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static struct serdes_chip_pinctrl_ops max96749_pinctrl_ops = { + .pin_config_get = max96749_pinctrl_config_get, + .pin_config_set = max96749_pinctrl_config_set, + .set_mux = max96749_pinctrl_set_mux, +}; + +static int max96749_gpio_direction_input(struct serdes *serdes, int gpio) +{ + return 0; +} + +static int max96749_gpio_direction_output(struct serdes *serdes, int gpio, int value) +{ + return 0; +} + +static int max96749_gpio_get_level(struct serdes *serdes, int gpio) +{ + return 0; +} + +static int max96749_gpio_set_level(struct serdes *serdes, int gpio, int value) +{ + return 0; +} + +static int max96749_gpio_set_config(struct serdes *serdes, int gpio, unsigned long config) +{ + return 0; +} + +static int max96749_gpio_to_irq(struct serdes *serdes, int gpio) +{ + return 0; +} + +static struct serdes_chip_gpio_ops max96749_gpio_ops = { + .direction_input = max96749_gpio_direction_input, + .direction_output = max96749_gpio_direction_output, + .get_level = max96749_gpio_get_level, + .set_level = max96749_gpio_set_level, + .set_config = max96749_gpio_set_config, + .to_irq = max96749_gpio_to_irq, +}; + +static const struct check_reg_data max96749_improtant_reg[10] = { + { + "MAX96749 LINK LOCK", + { 0x0013, (1 << 3) }, + }, { + "MAX96749 LINKA LOCK", + { 0x002A, (1 << 0) }, + }, { + "MAX96749 LINKB LOCK", + { 0x0034, (1 << 0) }, + }, { + "MAX96749 X PCLK DET", + { 0x0102, (1 << 7) }, + }, { + "MAX96749 Y PCLK DET", + { 0x0112, (1 << 7) }, + }, +}; + +static int max96749_check_reg(struct serdes *serdes) +{ + int i = 0, ret = 0; + unsigned int val = 0; + + for (i = 0; i < ARRAY_SIZE(max96749_improtant_reg); i++) { + if (!max96749_improtant_reg[i].seq.reg) + break; + + ret = serdes_reg_read(serdes, max96749_improtant_reg[i].seq.reg, &val); + if (!ret && !(val & max96749_improtant_reg[i].seq.def) + && (!atomic_read(&serdes->flag_early_suspend))) + dev_info(serdes->dev, "warning %s %s reg[0x%x] = 0x%x\n", __func__, + max96749_improtant_reg[i].name, + max96749_improtant_reg[i].seq.reg, val); + } + + return 0; +} + +static struct serdes_check_reg_ops max96749_check_reg_ops = { + .check_reg = max96749_check_reg, +}; + +static int max96749_pm_suspend(struct serdes *serdes) +{ + return 0; +} + +static int max96749_pm_resume(struct serdes *serdes) +{ + return 0; +} + +static struct serdes_chip_pm_ops max96749_pm_ops = { + .suspend = max96749_pm_suspend, + .resume = max96749_pm_resume, +}; + +static int max96749_irq_lock_handle(struct serdes *serdes) +{ + return IRQ_HANDLED; +} + +static int max96749_irq_err_handle(struct serdes *serdes) +{ + return IRQ_HANDLED; +} + +static struct serdes_chip_irq_ops max96749_irq_ops = { + .lock_handle = max96749_irq_lock_handle, + .err_handle = max96749_irq_err_handle, +}; + +struct serdes_chip_data serdes_max96749_data = { + .name = "max96749", + .serdes_type = TYPE_SER, + .serdes_id = MAXIM_ID_MAX96749, + .connector_type = DRM_MODE_CONNECTOR_eDP, + .regmap_config = &max96749_regmap_config, + .pinctrl_info = &max96749_pinctrl_info, + .bridge_ops = &max96749_bridge_ops, + .pinctrl_ops = &max96749_pinctrl_ops, + .gpio_ops = &max96749_gpio_ops, + .split_ops = &max96749_split_ops, + .check_ops = &max96749_check_reg_ops, + .pm_ops = &max96749_pm_ops, + .irq_ops = &max96749_irq_ops, +}; +EXPORT_SYMBOL_GPL(serdes_max96749_data); + +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/display-serdes/maxim/maxim-max96749.h b/drivers/mfd/display-serdes/maxim/maxim-max96749.h new file mode 100644 index 000000000000..6351a61cb657 --- /dev/null +++ b/drivers/mfd/display-serdes/maxim/maxim-max96749.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * maxim-max96749.h -- register define for max96749 chip + * + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: ZITONG CAI + * + */ + +#ifndef __MFD_SERDES_MAXIM_MAX96745_H__ +#define __MFD_SERDES_MAXIM_MAX96745_H__ + +#include + +#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8)) +#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8)) +#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8)) +#define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8)) + +/* 0005h */ +#define PU_LF3 BIT(3) +#define PU_LF2 BIT(2) +#define PU_LF1 BIT(1) +#define PU_LF0 BIT(0) + +/* 0010h */ +#define RESET_ALL BIT(7) +#define SLEEP BIT(3) + +/* 0011h */ +#define CXTP_B BIT(2) +#define CXTP_A BIT(0) + +/* 0013h */ +#define LOCKED BIT(3) +#define ERROR BIT(2) + +/* 0021h */ +#define LINKA_LOCKED BIT(2) +#define LINKB_LOCKED BIT(3) + +/* 0026h */ +#define LF_0 GENMASK(2, 0) +#define LF_1 GENMASK(6, 4) + +/* 0027h */ +#define LF_2 GENMASK(2, 0) +#define LF_3 GENMASK(6, 4) + +/* 0028h, 0032h */ +#define LINK_EN BIT(7) +#define TX_RATE GENMASK(3, 2) + +/* 0029h, 0033h */ +#define RESET_LINK BIT(0) +#define RESET_ONESHOT BIT(1) + +/* 0045h */ +#define DUAL_LINK_MODE BIT(1) + +/* 002Ah, 0034h */ +#define LINK_LOCKED BIT(0) + +/* 0076h, 0086h */ +#define DIS_REM_CC BIT(7) + +/* 0100h */ +#define VID_LINK_SEL GENMASK(2, 1) +#define VID_TX_EN BIT(0) + +/* 0101h */ +#define BPP GENMASK(5, 0) + +/* 0102h */ +#define PCLKDET_A BIT(7) +#define DRIFT_ERR_A BIT(6) +#define OVERFLOW_A BIT(5) +#define FIFO_WARN_A BIT(4) +#define LIM_HEART BIT(2) + +/* 0107h */ +#define VID_TX_ACTIVE_B BIT(7) +#define VID_TX_ACTIVE_A BIT(6) + +/* 0108h */ +#define PCLKDET_B BIT(7) +#define DRIFT_ERR_B BIT(6) +#define OVERFLOW_B BIT(5) +#define FIFO_WARN_B BIT(4) + +/* 0200h */ +#define RES_CFG BIT(7) +#define TX_COM_EN BIT(5) +#define GPIO_OUT BIT(4) +#define GPIO_IN BIT(3) +#define GPIO_OUT_DIS BIT(0) + +/* 0201h */ +#define PULL_UPDN_SEL GENMASK(7, 6) +#define OUT_TYPE BIT(5) +#define GPIO_TX_ID GENMASK(4, 0) + +/* 0202h */ +#define OVR_RES_CFG BIT(7) +#define IO_EDGE_RATE GENMASK(6, 5) +#define GPIO_RX_ID GENMASK(4, 0) + +/* 0203h */ +#define GPIO_IO_RX_EN BIT(5) +#define GPIO_OUT_LGC BIT(4) +#define GPIO_RX_EN_B BIT(3) +#define GPIO_TX_EN_B BIT(2) +#define GPIO_RX_EN_A BIT(1) +#define GPIO_TX_EN_A BIT(0) + +/* 0750h */ +#define FRCZEROPAD GENMASK(7, 6) +#define FRCZPEN BIT(5) +#define FRCSDGAIN BIT(4) +#define FRCSDEN BIT(3) +#define FRCGAIN GENMASK(2, 1) +#define FRCEN BIT(0) + +/* 0751h */ +#define FRCDATAWIDTH BIT(3) +#define FRCASYNCEN BIT(2) +#define FRCHSPOL BIT(1) +#define FRCVSPOL BIT(0) + +/* 0752h */ +#define FRCDCMODE GENMASK(1, 0) + +/* 641Ah */ +#define DPRX_TRAIN_STATE GENMASK(7, 4) + +/* 7000h */ +#define LINK_ENABLE BIT(0) + +/* 7070h */ +#define MAX_LANE_COUNT GENMASK(7, 0) + +/* 7074h */ +#define MAX_LINK_RATE GENMASK(7, 0) + +#endif diff --git a/drivers/mfd/display-serdes/serdes-bridge-split.c b/drivers/mfd/display-serdes/serdes-bridge-split.c index 2a40cc37722a..e44c51736157 100644 --- a/drivers/mfd/display-serdes/serdes-bridge-split.c +++ b/drivers/mfd/display-serdes/serdes-bridge-split.c @@ -327,6 +327,7 @@ static const struct of_device_id serdes_bridge_split_of_match[] = { { .compatible = "rohm,bu18tl82-bridge-split", }, { .compatible = "rohm,bu18rl82-bridge-split", }, { .compatible = "maxim,max96745-bridge-split", }, + { .compatible = "maxim,max96749-bridge-split", }, { .compatible = "maxim,max96755-bridge-split", }, { .compatible = "maxim,max96752-bridge-split", }, { .compatible = "maxim,max96789-bridge-split", }, diff --git a/drivers/mfd/display-serdes/serdes-bridge.c b/drivers/mfd/display-serdes/serdes-bridge.c index 9a6f9bf8aef4..381c4085938a 100644 --- a/drivers/mfd/display-serdes/serdes-bridge.c +++ b/drivers/mfd/display-serdes/serdes-bridge.c @@ -326,6 +326,7 @@ static const struct of_device_id serdes_bridge_of_match[] = { { .compatible = "rohm,bu18tl82-bridge", }, { .compatible = "rohm,bu18rl82-bridge", }, { .compatible = "maxim,max96745-bridge", }, + { .compatible = "maxim,max96749-bridge", }, { .compatible = "maxim,max96755-bridge", }, { .compatible = "maxim,max96789-bridge", }, { .compatible = "rockchip,rkx111-bridge", }, diff --git a/drivers/mfd/display-serdes/serdes-core.c b/drivers/mfd/display-serdes/serdes-core.c index da45502f254f..cbd0cd02eb72 100644 --- a/drivers/mfd/display-serdes/serdes-core.c +++ b/drivers/mfd/display-serdes/serdes-core.c @@ -49,6 +49,21 @@ static const struct mfd_cell serdes_max96745_devs[] = { }, }; +static const struct mfd_cell serdes_max96749_devs[] = { + { + .name = "serdes-pinctrl", + .of_compatible = "maxim,max96749-pinctrl", + }, + { + .name = "serdes-bridge", + .of_compatible = "maxim,max96749-bridge", + }, + { + .name = "serdes-bridge-split", + .of_compatible = "maxim,max96749-bridge-split", + }, +}; + static const struct mfd_cell serdes_max96755_devs[] = { { .name = "serdes-pinctrl", @@ -364,6 +379,10 @@ int serdes_device_init(struct serdes *serdes) serdes_devs = serdes_max96745_devs; mfd_num = ARRAY_SIZE(serdes_max96745_devs); break; + case MAXIM_ID_MAX96749: + serdes_devs = serdes_max96749_devs; + mfd_num = ARRAY_SIZE(serdes_max96749_devs); + break; case MAXIM_ID_MAX96752: serdes_devs = serdes_max96752_devs; mfd_num = ARRAY_SIZE(serdes_max96752_devs); diff --git a/drivers/mfd/display-serdes/serdes-gpio.c b/drivers/mfd/display-serdes/serdes-gpio.c index 1c49cf55fc28..eaaeb60eac34 100644 --- a/drivers/mfd/display-serdes/serdes-gpio.c +++ b/drivers/mfd/display-serdes/serdes-gpio.c @@ -209,6 +209,7 @@ static const struct of_device_id serdes_gpio_of_match[] = { { .compatible = "rohm,bu18tl82-gpio", }, { .compatible = "rohm,bu18rl82-gpio", }, { .compatible = "maxim,max96745-gpio", }, + { .compatible = "maxim,max96749-gpio", }, { .compatible = "maxim,max96752-gpio", }, { .compatible = "maxim,max96755-gpio", }, { .compatible = "maxim,max96772-gpio", }, diff --git a/drivers/mfd/display-serdes/serdes-i2c.c b/drivers/mfd/display-serdes/serdes-i2c.c index feb2d8f3460c..dfe709332adb 100644 --- a/drivers/mfd/display-serdes/serdes-i2c.c +++ b/drivers/mfd/display-serdes/serdes-i2c.c @@ -310,6 +310,8 @@ static int serdes_get_init_seq(struct serdes *serdes) return err; } + serdes->dual_link = of_property_read_bool(dev->of_node, "dual-link"); + /* init ser register(not des register) more early if uboot logo disabled */ serdes->route_enable = of_property_read_bool(dev->of_node, "route-enable"); if ((!serdes->route_enable) && (serdes->chip_data->serdes_type == TYPE_SER)) { @@ -540,6 +542,9 @@ static const struct of_device_id serdes_of_match[] = { #if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745) { .compatible = "maxim,max96745", .data = &serdes_max96745_data }, #endif +#if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749) + { .compatible = "maxim,max96749", .data = &serdes_max96749_data }, +#endif #if IS_ENABLED(CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752) { .compatible = "maxim,max96752", .data = &serdes_max96752_data }, #endif diff --git a/drivers/mfd/display-serdes/serdes-pinctrl.c b/drivers/mfd/display-serdes/serdes-pinctrl.c index 27605732ff66..d16852ddd3c6 100644 --- a/drivers/mfd/display-serdes/serdes-pinctrl.c +++ b/drivers/mfd/display-serdes/serdes-pinctrl.c @@ -30,6 +30,13 @@ static const struct mfd_cell serdes_gpio_max96745_devs[] = { }, }; +static const struct mfd_cell serdes_gpio_max96749_devs[] = { + { + .name = "serdes-gpio", + .of_compatible = "maxim,max96749-gpio", + }, +}; + static const struct mfd_cell serdes_gpio_max96755_devs[] = { { .name = "serdes-gpio", @@ -173,6 +180,10 @@ static int serdes_pinctrl_gpio_init(struct serdes *serdes) serdes_devs = serdes_gpio_max96745_devs; mfd_num = ARRAY_SIZE(serdes_gpio_max96745_devs); break; + case MAXIM_ID_MAX96749: + serdes_devs = serdes_gpio_max96749_devs; + mfd_num = ARRAY_SIZE(serdes_gpio_max96749_devs); + break; case MAXIM_ID_MAX96752: serdes_devs = serdes_gpio_max96752_devs; mfd_num = ARRAY_SIZE(serdes_gpio_max96752_devs); From 6c514e027d4ff743fee384d2650900b92dde6ba3 Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Thu, 26 Jun 2025 20:00:22 +0800 Subject: [PATCH 09/25] mfd: display-serdes: Add max96772 gpio interface control and read dpcd information Change-Id: I332f65c824738c4e2765450823bd2298bd6ce2ed Signed-off-by: Zitong Cai --- .../mfd/display-serdes/maxim/maxim-max96772.c | 253 ++++++++++++++++-- .../mfd/display-serdes/maxim/maxim-max96772.h | 59 ++-- .../mfd/display-serdes/serdes-panel-split.c | 4 - drivers/mfd/display-serdes/serdes-panel.c | 4 - 4 files changed, 279 insertions(+), 41 deletions(-) diff --git a/drivers/mfd/display-serdes/maxim/maxim-max96772.c b/drivers/mfd/display-serdes/maxim/maxim-max96772.c index 8394ec2c22b5..b6db704fea9e 100644 --- a/drivers/mfd/display-serdes/maxim/maxim-max96772.c +++ b/drivers/mfd/display-serdes/maxim/maxim-max96772.c @@ -14,11 +14,13 @@ static const struct regmap_range max96772_readable_ranges[] = { regmap_reg_range(0x0000, 0x0800), regmap_reg_range(0x1700, 0x1700), regmap_reg_range(0x4100, 0x4100), - regmap_reg_range(0x6230, 0x6230), + regmap_reg_range(0x6000, 0x6230), regmap_reg_range(0x7014, 0x7016), regmap_reg_range(0xe75e, 0xe75e), regmap_reg_range(0xe7c4, 0xe7c6), regmap_reg_range(0xe776, 0xe7bf), + regmap_reg_range(0xe7d1, 0xe7d1), + regmap_reg_range(0xe7de, 0xe7de), }; static const struct regmap_access_table max96772_readable_table = { @@ -70,6 +72,23 @@ static int MAX96772_GPIO15_pins[] = {15}; .num_pins = ARRAY_SIZE(nm ## _pins), \ } +#define GROUP_DESC_CONFIG(nm) \ +{ \ + .name = #nm, \ + .pins = nm ## _pins, \ + .num_pins = ARRAY_SIZE(nm ## _pins), \ + .data = (void *)(const struct serdes_group_data []) { \ + { \ + .configs = nm ## _configs, \ + .num_configs = ARRAY_SIZE(nm ## _configs), \ + } \ + }, \ +} + +static const struct config_desc MAX96772_GPIO7_configs[] = { + { 0x02, AUD_TX_EN, 0}, +}; + struct serdes_function_data { u8 gpio_out_dis:1; u8 gpio_tx_en:1; @@ -169,7 +188,7 @@ static struct group_desc max96772_groups_desc[] = { GROUP_DESC(MAX96772_GPIO4), GROUP_DESC(MAX96772_GPIO5), GROUP_DESC(MAX96772_GPIO6), - GROUP_DESC(MAX96772_GPIO7), + GROUP_DESC_CONFIG(MAX96772_GPIO7), GROUP_DESC(MAX96772_GPIO8), GROUP_DESC(MAX96772_GPIO9), @@ -337,6 +356,70 @@ static const struct reg_sequence max96772_clk_ref[4][14] = { } }; +static const struct reg_sequence max96772_clk_ssc[4][14] = { + { + { 0xe7b2, 0x50 }, + { 0xe7b3, 0x00 }, + { 0xe7b4, 0x35 }, + { 0xe7b5, 0x42 }, + { 0xe7b6, 0x81 }, + { 0xe7b7, 0x30 }, + { 0xe7b8, 0x07 }, + { 0xe7b9, 0x10 }, + { 0xe7ba, 0x01 }, + { 0xe7bb, 0x00 }, + { 0xe7bc, 0x00 }, + { 0xe7bd, 0x00 }, + { 0xe7be, 0x52 }, + { 0xe7bf, 0x00 }, + }, { + { 0xe7b2, 0x50 }, + { 0xe7b3, 0x00 }, + { 0xe7b4, 0xd7 }, + { 0xe7b5, 0x45 }, + { 0xe7b6, 0x6b }, + { 0xe7b7, 0x20 }, + { 0xe7b8, 0x07 }, + { 0xe7b9, 0x00 }, + { 0xe7ba, 0x01 }, + { 0xe7bb, 0x00 }, + { 0xe7bc, 0x00 }, + { 0xe7bd, 0x00 }, + { 0xe7be, 0x52 }, + { 0xe7bf, 0x00 }, + }, { + { 0xe7b2, 0x30 }, + { 0xe7b3, 0x00 }, + { 0xe7b4, 0xd7 }, + { 0xe7b5, 0x45 }, + { 0xe7b6, 0x6b }, + { 0xe7b7, 0x20 }, + { 0xe7b8, 0x14 }, + { 0xe7b9, 0x00 }, + { 0xe7ba, 0x2e }, + { 0xe7bb, 0x00 }, + { 0xe7bc, 0x02 }, + { 0xe7bd, 0x01 }, + { 0xe7be, 0x32 }, + { 0xe7bf, 0x00 }, + }, { + { 0xe7b2, 0x30 }, + { 0xe7b3, 0x00 }, + { 0xe7b4, 0xd7 }, + { 0xe7b5, 0x45 }, + { 0xe7b6, 0x6b }, + { 0xe7b7, 0x20 }, + { 0xe7b8, 0x14 }, + { 0xe7b9, 0x00 }, + { 0xe7ba, 0x2e }, + { 0xe7bb, 0x00 }, + { 0xe7bc, 0x00 }, + { 0xe7bd, 0x00 }, + { 0xe7be, 0x32 }, + { 0xe7bf, 0x00 }, + } +}; + static int max96772_aux_dpcd_read(struct serdes *serdes, unsigned int reg, unsigned int *value) { serdes_reg_write(serdes, 0xe778, reg & 0xff); @@ -358,6 +441,35 @@ static int max96772_panel_prepare(struct serdes *serdes) u32 vact, vsa, vfp, vbp; u64 hwords, mvid; bool hsync_pol, vsync_pol; + int ret; + u32 dpcd; + int link_rate; + + if (!serdes->serdes_panel->link_rate || !serdes->serdes_panel->lane_count) { + ret = max96772_aux_dpcd_read(serdes, DP_MAX_LANE_COUNT, &dpcd); + if (ret) { + dev_err(serdes->dev, "failed to read max lane count\n"); + return ret; + } + + serdes->serdes_panel->lane_count = min_t(int, 4, dpcd & DP_MAX_LANE_COUNT_MASK); + + ret = max96772_aux_dpcd_read(serdes, DP_MAX_LINK_RATE, &dpcd); + if (ret) { + dev_err(serdes->dev, "failed to read max link rate\n"); + return ret; + } + + serdes->serdes_panel->link_rate = min_t(int, dpcd, DP_LINK_BW_5_4); + + ret = max96772_aux_dpcd_read(serdes, DP_MAX_DOWNSPREAD, &dpcd); + if (ret) { + dev_err(serdes->dev, "failed to read max downspread\n"); + return ret; + } + + serdes->serdes_panel->ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); + } serdes_reg_write(serdes, 0xe790, serdes->serdes_panel->link_rate); serdes_reg_write(serdes, 0xe792, serdes->serdes_panel->lane_count); @@ -373,20 +485,46 @@ static int max96772_panel_prepare(struct serdes *serdes) serdes->serdes_panel->link_rate, serdes->serdes_panel->lane_count, serdes->serdes_panel->ssc); - switch (serdes->serdes_panel->link_rate) { - case DP_LINK_BW_5_4: - serdes_multi_reg_write(serdes, max96772_clk_ref[2], - ARRAY_SIZE(max96772_clk_ref[2])); + if (serdes->serdes_panel->ssc) { + switch (serdes->serdes_panel->link_rate) { + case DP_LINK_BW_8_1: + serdes_multi_reg_write(serdes, max96772_clk_ssc[3], + ARRAY_SIZE(max96772_clk_ssc[3])); break; - case DP_LINK_BW_2_7: - serdes_multi_reg_write(serdes, max96772_clk_ref[1], - ARRAY_SIZE(max96772_clk_ref[1])); + case DP_LINK_BW_5_4: + serdes_multi_reg_write(serdes, max96772_clk_ssc[2], + ARRAY_SIZE(max96772_clk_ssc[2])); break; - case DP_LINK_BW_1_62: - default: - serdes_multi_reg_write(serdes, max96772_clk_ref[0], - ARRAY_SIZE(max96772_clk_ref[0])); + case DP_LINK_BW_2_7: + serdes_multi_reg_write(serdes, max96772_clk_ssc[1], + ARRAY_SIZE(max96772_clk_ssc[1])); break; + case DP_LINK_BW_1_62: + default: + serdes_multi_reg_write(serdes, max96772_clk_ssc[0], + ARRAY_SIZE(max96772_clk_ssc[0])); + break; + } + } else { + switch (serdes->serdes_panel->link_rate) { + case DP_LINK_BW_8_1: + serdes_multi_reg_write(serdes, max96772_clk_ref[3], + ARRAY_SIZE(max96772_clk_ref[3])); + break; + case DP_LINK_BW_5_4: + serdes_multi_reg_write(serdes, max96772_clk_ref[2], + ARRAY_SIZE(max96772_clk_ref[2])); + break; + case DP_LINK_BW_2_7: + serdes_multi_reg_write(serdes, max96772_clk_ref[1], + ARRAY_SIZE(max96772_clk_ref[1])); + break; + case DP_LINK_BW_1_62: + default: + serdes_multi_reg_write(serdes, max96772_clk_ref[0], + ARRAY_SIZE(max96772_clk_ref[0])); + break; + } } vact = mode->vdisplay; @@ -428,9 +566,11 @@ static int max96772_panel_prepare(struct serdes *serdes) serdes_reg_write(serdes, 0xe7a4, hwords); serdes_reg_write(serdes, 0xe7a5, hwords >> 8); - /* MVID = (PCLK x NVID) x 10 / Link Rate */ + /* MVID = (PCLK_in_MHz x NVID)/(Link_Rate_in_GBs * 100) */ + link_rate = drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate); mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768, - drm_dp_bw_code_to_link_rate(serdes->serdes_panel->link_rate)); + link_rate); + serdes_reg_write(serdes, 0xe7a6, mvid & 0xff); serdes_reg_write(serdes, 0xe7a7, (mvid >> 8) & 0xff); @@ -568,7 +708,6 @@ static int max96772_pinctrl_set_mux(struct serdes *serdes, for (i = 0; i < gdata->num_configs; i++) { const struct config_desc *config = &gdata->configs[i]; - serdes_set_bits(serdes, config->reg, config->mask, config->val); } @@ -730,21 +869,101 @@ static struct serdes_chip_pinctrl_ops max96772_pinctrl_ops = { static int max96772_gpio_direction_input(struct serdes *serdes, int gpio) { + struct serdes_pinctrl *pinctrl = serdes->pinctrl; + struct group_desc *grp; + int i; + + grp = pinctrl_generic_get_group(pinctrl->pctl, gpio); + if (!grp) + return -EINVAL; + + if (grp->data) { + struct serdes_group_data *gdata = grp->data; + + for (i = 0; i < gdata->num_configs; i++) { + const struct config_desc *config = &gdata->configs[i]; + + serdes_set_bits(serdes, config->reg, + config->mask, config->val); + } + } + + serdes_set_bits(serdes, GPIO_A_REG(gpio), + GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN, + FIELD_PREP(GPIO_OUT_DIS, 0) | + FIELD_PREP(GPIO_RX_EN, 1) | + FIELD_PREP(GPIO_TX_EN, 0)); + + serdes_set_bits(serdes, GPIO_B_REG(gpio), + OUT_TYPE, + FIELD_PREP(OUT_TYPE, 1)); + + SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d\n", + __func__, serdes->chip_data->name, gpio); + return 0; } static int max96772_gpio_direction_output(struct serdes *serdes, int gpio, int value) { + struct serdes_pinctrl *pinctrl = serdes->pinctrl; + struct group_desc *grp; + int i; + + grp = pinctrl_generic_get_group(pinctrl->pctl, gpio); + if (!grp) + return -EINVAL; + + if (grp->data) { + struct serdes_group_data *gdata = grp->data; + + for (i = 0; i < gdata->num_configs; i++) { + const struct config_desc *config = &gdata->configs[i]; + + serdes_set_bits(serdes, config->reg, + config->mask, config->val); + } + } + + serdes_set_bits(serdes, GPIO_A_REG(gpio), + GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN | GPIO_OUT, + FIELD_PREP(GPIO_OUT_DIS, 0) | + FIELD_PREP(GPIO_RX_EN, 0) | + FIELD_PREP(GPIO_TX_EN, 0) | + FIELD_PREP(GPIO_OUT, value)); + + serdes_set_bits(serdes, + GPIO_B_REG(gpio), + OUT_TYPE, + FIELD_PREP(OUT_TYPE, 1)); + + SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d value=%d\n", + __func__, serdes->chip_data->name, gpio, value); + return 0; } static int max96772_gpio_get_level(struct serdes *serdes, int gpio) { - return 0; + unsigned int value; + + serdes_reg_read(serdes, GPIO_A_REG(gpio), &value); + + value &= GPIO_IN; + SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d\n", + __func__, serdes->chip_data->name, gpio, value); + + return value; } static int max96772_gpio_set_level(struct serdes *serdes, int gpio, int value) { + serdes_set_bits(serdes, GPIO_A_REG(gpio), GPIO_OUT, + FIELD_PREP(GPIO_OUT, value)); + + SERDES_DBG_CHIP("%s: serdes chip %s gpio=%d value=%d\n", + __func__, serdes->chip_data->name, gpio, value); + return 0; } diff --git a/drivers/mfd/display-serdes/maxim/maxim-max96772.h b/drivers/mfd/display-serdes/maxim/maxim-max96772.h index 3ef5b2defe79..a660ea29db17 100644 --- a/drivers/mfd/display-serdes/maxim/maxim-max96772.h +++ b/drivers/mfd/display-serdes/maxim/maxim-max96772.h @@ -11,28 +11,55 @@ #ifndef __MFD_SERDES_MAXIM_MAX96772_H__ #define __MFD_SERDES_MAXIM_MAX96772_H__ -#define GPIO_A_REG(gpio) (0x02b0 + ((gpio) * 3)) -#define GPIO_B_REG(gpio) (0x02b1 + ((gpio) * 3)) -#define GPIO_C_REG(gpio) (0x02b2 + ((gpio) * 3)) +#define GPIO_A_REG(gpio) (0x02b0 + ((gpio) * 3)) +#define GPIO_B_REG(gpio) (0x02b1 + ((gpio) * 3)) +#define GPIO_C_REG(gpio) (0x02b2 + ((gpio) * 3)) +/* 0002h */ +#define VID_EN_U BIT(7) +#define VID_EN_Z BIT(6) +#define VID_EN_Y BIT(5) +#define VID_EN_X BIT(4) +#define AUD_TX_EN BIT(2) + +/* 0004h */ +#define LINK_EN_B BIT(5) +#define LINK_EN_A BIT(4) + +/* 0010h */ +#define RESET_ALL BIT(7) +#define RESET_LINK BIT(6) +#define RESET_ONESHOT BIT(5) +#define AUTO_LINK BIT(4) +#define SLEEP BIT(3) +#define REG_ENABLE BIT(2) +#define LINK_CFG GENMASK(1, 0) + +/* 0013h */ +#define LINK_MODE BIT(4) +#define LOCKED BIT(3) + +/* 001fh */ +#define LINKA_LOCKED BIT(4) +#define LINKB_LOCKED BIT(5) /* 02b0h */ -#define RES_CFG BIT(7) -#define RSVD BIT(6) -#define TX_COMP_EN BIT(5) -#define GPIO_OUT BIT(4) -#define GPIO_IN BIT(3) -#define GPIO_RX_EN BIT(2) -#define GPIO_TX_EN BIT(1) -#define GPIO_OUT_DIS BIT(0) +#define RES_CFG BIT(7) +#define RSVD BIT(6) +#define TX_COMP_EN BIT(5) +#define GPIO_OUT BIT(4) +#define GPIO_IN BIT(3) +#define GPIO_RX_EN BIT(2) +#define GPIO_TX_EN BIT(1) +#define GPIO_OUT_DIS BIT(0) /* 02b1h */ -#define PULL_UPDN_SEL GENMASK(7, 6) -#define OUT_TYPE BIT(5) -#define GPIO_TX_ID GENMASK(4, 0) +#define PULL_UPDN_SEL GENMASK(7, 6) +#define OUT_TYPE BIT(5) +#define GPIO_TX_ID GENMASK(4, 0) /* 02b2h */ -#define OVR_RES_CFG BIT(7) -#define GPIO_RX_ID GENMASK(4, 0) +#define OVR_RES_CFG BIT(7) +#define GPIO_RX_ID GENMASK(4, 0) #endif diff --git a/drivers/mfd/display-serdes/serdes-panel-split.c b/drivers/mfd/display-serdes/serdes-panel-split.c index 01a2a8153860..1915de98359b 100644 --- a/drivers/mfd/display-serdes/serdes-panel-split.c +++ b/drivers/mfd/display-serdes/serdes-panel-split.c @@ -148,10 +148,6 @@ static int serdes_panel_split_parse_dt(struct serdes_panel_split *serdes_panel_s serdes_panel_split->width_mm = panel_size[0]; serdes_panel_split->height_mm = panel_size[1]; - serdes_panel_split->link_rate = link_rate_count_ssc[0]; - serdes_panel_split->lane_count = link_rate_count_ssc[1]; - serdes_panel_split->ssc = link_rate_count_ssc[2]; - if (of_find_property(dev->of_node, "panel-size", &len)) { len /= sizeof(unsigned int); ret = of_property_read_u32_array(dev->of_node, "panel-size", diff --git a/drivers/mfd/display-serdes/serdes-panel.c b/drivers/mfd/display-serdes/serdes-panel.c index 3691501510f2..b7fbfae76d96 100644 --- a/drivers/mfd/display-serdes/serdes-panel.c +++ b/drivers/mfd/display-serdes/serdes-panel.c @@ -147,10 +147,6 @@ static int serdes_panel_parse_dt(struct serdes_panel *serdes_panel) serdes_panel->width_mm = panel_size[0]; serdes_panel->height_mm = panel_size[1]; - serdes_panel->link_rate = link_rate_count_ssc[0]; - serdes_panel->lane_count = link_rate_count_ssc[1]; - serdes_panel->ssc = link_rate_count_ssc[2]; - if (of_find_property(dev->of_node, "panel-size", &len)) { len /= sizeof(unsigned int); if (len != 2) { From fe4e4c8d8c25c9d8f077465bd5e15a70e9641e0a Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Fri, 20 Jun 2025 10:46:17 +0800 Subject: [PATCH 10/25] pwm: add support for r7f701 Change-Id: I3a3441c5c57aded98484c81f8e2b089faef98641 Signed-off-by: Zitong Cai --- drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-r7f701.c | 280 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/pwm/pwm-r7f701.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 782bc70138e0..fcc59af8355a 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -507,6 +507,13 @@ config PWM_ROCKCHIP_TEST whether it is about the generic framework or the functions supported by Rockchip PWM. +config PWM_R7F701 + tristate "R7F701 PWM support" + help + This is a MCU for controlling brightness on the screen, which + adjusts brightness by writing corresponding registers through I2C. + If you don't have this MCU in your design, choose N. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index fe2f53833a65..611745cee577 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_ROCKCHIP_TEST) += pwm-rockchip-test.o +obj-$(CONFIG_PWM_R7F701) += pwm-r7f701.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o diff --git a/drivers/pwm/pwm-r7f701.c b/drivers/pwm/pwm-r7f701.c new file mode 100644 index 000000000000..38ffabaaeef9 --- /dev/null +++ b/drivers/pwm/pwm-r7f701.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * serdes-i2c.c -- Control screen brightness + * + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: ZITONG CAI + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_MAX_LEVEL 0x64 + +#define DISPLAY_STATUS 0x40 +#define LVDS_LOCK_STATUS 0x41 +#define CUR_BRIGHTNESS_LEVEL 0x42 +#define OLED_FAULT_RECORD 0x43 +#define PCB_TEMP_STATUS 0x44 +#define OLED_TEMP_STATUS 0x45 +#define CID_POWER_STATUS 0x46 +#define CID_HARDWARE_VERSION 0x47 +#define CID_SOFT_APP_VERSION 0x48 +#define CID_BOOTLOADER_VERSION 0x49 +#define CID_FUALT_RECORD 0x4a +#define CID_VOLTAGE_VALUE 0x4b +#define CID_CURRENT_MODE_STATUS 0x4c +#define CID_ENTER_AUTO_CAUSE 0x4d +#define CID_CAN_STATUS 0x4e + + +#define REQUEST_DISPLAY_STATUS 0x80 +#define REQUEST_LVDS_LOCK_STATUS 0x81 +#define REQUEST_BRIGHTNESS_LEVEL 0x82 +#define REQUEST_OLED_FAULT_RECORD 0x83 +#define REQUEST_PCB_TEMP_STATUS 0x84 +#define REQUEST_OLED_TEMP_STATUS 0x85 +#define REQUEST_CID_POWER_STATE 0x86 +#define REQUEST_CID_HARDWARE_VERSION 0x87 +#define REQUEST_CID_SOFT_APP_VERSION 0x88 +#define REQUEST_CID_BOOTLOADER_VERSION 0x89 +#define REQUEST_CID_FUALT_RECORD 0x8a +#define REQUEST_CID_VOLTAGE_VALUE 0x8b +#define REQUEST_CID_CURRENT_MODE_STATUS 0x8c +#define REQUEST_CID_ENTER_AUTO_CAUSE 0x8d +#define REQUEST_DISPLAY_STATUS_SET 0x8e +#define REQUEST_CID_BRIGHTNESS_SET 0x8f +#define REQUEST_IDCM_WRITE_HEART 0x90 +#define REQUEST_CID_CAN_STATUS 0x91 +#define REQUEST_IDCM_SEND_CRC 0x92 + +enum { + DISPLAY_OFF, + DISPLAY_ON +}; + +struct r7f701_pwm_chip { + struct pwm_chip chip; + struct device *dev; + struct regmap *regmap; + +}; + +static bool r7f701_is_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x80 ... 0x92: + return true; + } + return false; +} + +static bool r7f701_is_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x40 ... 0x4e: + return true; + } + return false; +} + +static bool r7f701_is_volatile_reg(struct device *dev, unsigned int reg) +{ + return true; +} + + +static const struct regmap_config r7f701_regmap_config = { + .name = "r7f701", + .reg_bits = 8, + .val_bits = 8, + .writeable_reg = r7f701_is_writeable_reg, + .readable_reg = r7f701_is_readable_reg, + .volatile_reg = r7f701_is_volatile_reg, + .cache_type = REGCACHE_RBTREE, + .max_register = 0x92, +}; + +static inline struct r7f701_pwm_chip *to_r7f701_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct r7f701_pwm_chip, chip); +} + +static int r7f701_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + u64 duty_ns, u64 period_ns) +{ + u8 reg = 0; + u64 div = 0; + u8 level = 0; + int ret = 0; + u8 data[7] = {0}; + struct r7f701_pwm_chip *r7f701 = to_r7f701_pwm_chip(chip); + + div = duty_ns * PWM_MAX_LEVEL; + level = DIV_ROUND_CLOSEST_ULL(div, period_ns); + + reg = REQUEST_DISPLAY_STATUS_SET; + data[0] = DISPLAY_ON; + data[1] = level; + data[6] = reg ^ data[0] ^ data[1]; + ret |= regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data)); + memset(data, 0, sizeof(data)); + + reg = REQUEST_CID_BRIGHTNESS_SET; + data[0] = level; + data[6] = reg ^ data[0]; + ret |= regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data)); + + dev_dbg(chip->dev, "%s: pwm chip BRIGHTNESS_SET level 0x%x ret=%d\n", __func__, level, ret); + + return 0; +} + +static int r7f701_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + dev_dbg(chip->dev, "%s: pwm chip\n", __func__); + + return 0; +} + +static void r7f701_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct r7f701_pwm_chip *r7f701 = to_r7f701_pwm_chip(chip); + int ret = 0; + u8 reg = 0; + u8 data[7] = {0}; + + reg = REQUEST_DISPLAY_STATUS_SET; + data[0] = DISPLAY_OFF; + data[6] = reg ^ data[0]; + ret = regmap_bulk_write(r7f701->regmap, reg, data, ARRAY_SIZE(data)); + + dev_dbg(chip->dev, "%s: pwm chip ret=%d\n", __func__, ret); +} + +static int r7f701_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int err; + + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!state->enabled) { + if (pwm->state.enabled) + r7f701_pwm_disable(chip, pwm); + + return 0; + } + + err = r7f701_pwm_config(chip, pwm, state->duty_cycle, state->period); + if (err) + return err; + + if (!pwm->state.enabled) + return r7f701_pwm_enable(chip, pwm); + + return 0; +} + +static int r7f701_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + state->enabled = true; + state->polarity = PWM_POLARITY_NORMAL; + + dev_dbg(chip->dev, "%s: pwm chip\n", __func__); + + return 0; +} + +static const struct pwm_ops r7f701_pwm_ops = { + .apply = r7f701_pwm_apply, + .get_state = r7f701_pwm_get_state, + .owner = THIS_MODULE, +}; + +static const struct of_device_id pwm_of_match[] = { + { .compatible = "r7f701-pwm", .data = 0}, + { } +}; + +static int pwm_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct r7f701_pwm_chip *r7f701; + int ret = 0; + + r7f701 = devm_kzalloc(dev, sizeof(*r7f701), GFP_KERNEL); + if (!r7f701) + return -ENOMEM; + + r7f701->dev = dev; + r7f701->chip.dev = dev; + r7f701->chip.ops = &r7f701_pwm_ops; + r7f701->chip.npwm = 1; + + i2c_set_clientdata(client, r7f701); + dev_set_drvdata(dev, r7f701); + + r7f701->regmap = devm_regmap_init_i2c(client, &r7f701_regmap_config); + if (IS_ERR(r7f701->regmap)) { + dev_err(dev, "%s: Failed to allocate r7f701 register map\n", __func__); + return PTR_ERR(r7f701->regmap); + } + + ret = devm_pwmchip_add(dev, &r7f701->chip); + if (ret < 0) { + dev_err(dev, "%s: pwmchip_add() failed: %d\n", __func__, ret); + return ret; + } + + dev_dbg(dev, "%s successful\n", __func__); + + return 0; +} + +static struct i2c_driver r7f701_i2c_driver = { + .driver = { + .name = "r7f701-pwm", + .of_match_table = of_match_ptr(pwm_of_match), + }, + .probe = pwm_probe, +}; + +static int __init r7f701_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&r7f701_i2c_driver); + if (ret != 0) + pr_err("Failed to register r7f701 I2C driver: %d\n", ret); + + return ret; +} + +static void __exit r7f701_i2c_exit(void) +{ + i2c_del_driver(&r7f701_i2c_driver); +} + +subsys_initcall(r7f701_i2c_init); +module_exit(r7f701_i2c_exit); + +MODULE_AUTHOR("ZITONG CAI "); +MODULE_DESCRIPTION("display pwm interface"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:r7f701-PWM"); From 6d1dda64b33f73517f39b177fb7f7068cdf2eb78 Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Fri, 27 Jun 2025 10:28:00 +0800 Subject: [PATCH 11/25] arm64: configs: rk3588_vehicle.config: enable CONFIG_PWM_R7F701 Change-Id: Iab41927cc8bd24bfc07c0b98ccba20bb11eb20a7 Signed-off-by: Zitong Cai --- arch/arm64/configs/rk3588_vehicle.config | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/configs/rk3588_vehicle.config b/arch/arm64/configs/rk3588_vehicle.config index 4a519c7040dd..59b8c7b085aa 100644 --- a/arch/arm64/configs/rk3588_vehicle.config +++ b/arch/arm64/configs/rk3588_vehicle.config @@ -48,6 +48,7 @@ CONFIG_MALI_VALHALL=y # CONFIG_MFD_RKX110_X120 is not set CONFIG_MFD_SERDES_DISPLAY=y # CONFIG_PROXIMITY_DEVICE is not set +CONFIG_PWM_R7F701=y # CONFIG_R8168 is not set CONFIG_REALTEK_PHY=y # CONFIG_REGULATOR_ACT8865 is not set @@ -120,7 +121,6 @@ CONFIG_VIDEO_MAXIM_SERDES=y # CONFIG_VIDEO_SGM3784 is not set # CONFIG_VL6180 is not set CONFIG_MALI_CSF_INCLUDE_FW=y -# CONFIG_MALI_VALHALL_ARBITRATION is not set # CONFIG_MALI_VALHALL_CORESIGHT is not set # CONFIG_MALI_VALHALL_CORESTACK is not set CONFIG_MALI_VALHALL_CSF_SUPPORT=y @@ -146,6 +146,7 @@ CONFIG_MALI_VALHALL_TRACE_POWER_GPU_WORK_PERIOD=y # CONFIG_ROCKCHIP_DRM_SELF_TEST is not set CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y +CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749=y CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y From 1da38a464da40348c6c2987e0dc28155e792a9be Mon Sep 17 00:00:00 2001 From: Zitong Cai Date: Thu, 26 Jun 2025 20:02:50 +0800 Subject: [PATCH 12/25] arm64: dts: rockchip: rk3588-vehicle-evb: Add max96749+max96772 2560x1600 resolution case Change-Id: I561ff2dff84d75ec08ad33a05eaaa063f0f2db22 Signed-off-by: Zitong Cai --- ...vehicle-serdes-mfd-display-maxim-2.5k.dtsi | 2493 +++++++++++++++++ 1 file changed, 2493 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-2.5k.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-2.5k.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-2.5k.dtsi new file mode 100644 index 000000000000..ba8b772fef2d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-2.5k.dtsi @@ -0,0 +1,2493 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl0_enable_pin>; + //enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm2 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl1_enable_pin>; + //enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + //rockchip,split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_max96749: endpoint { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c4_max96749_from_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_max96749: endpoint { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96749_from_dp1>; + }; + }; + }; + +}; + +&dp1_in_vp0 { + status = "disabled"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp2lvds_backlight0 { + pwms = <&i2c4_r7f701_pwm 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl2_enable_pin>; + //enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&i2c8_r7f701_pwm 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl3_enable_pin>; + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; +#if 0 + port@1 { + reg = <1>; + + dsi1_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi1>; + }; + }; +#endif + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&edp0 { + //rockchip,split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_max96749: endpoint { + remote-endpoint = <&i2c5_max96749_from_edp0>; + }; + }; + }; + +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl4_enable_pin>; + //enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl5_enable_pin>; + //enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + i2c2_max96789: i2c2-max96789@42 { + compatible = "maxim,max96789"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_serdes_pins>; + lock-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + sel-mipi; + id-serdes-bridge-split = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + //Independent 11_07_17-56 Using MAX96789/91/F (GMSL-1/2) + //Disable Video pipe + 0002 0003 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set Stream for DSI Port A && assign pipeX + 0053 0010 + //Set Stream for DSI Port B && assign pipeY + 0057 0021 + //Clock Select, X for portA, Y/Z for PortB + 0308 0076 + //Start DSI Port + 0311 0061 + //Set Port A Lane Mapping + 0332 004E + //Set Port B Lane Mapping + 0333 00E4 + //Set GMSL type + 0004 00F2 + //Number of Lanes + 0331 0033 + //Set phy_config + 0330 0006 + //Set soft_dtx_en + 031C 0098 + //Set soft_dtx + 0321 0024 + //Set soft_dty_en + 031D 0098 + //Set soft_dty_ + 0322 0024 + //Init Default + 0326 00E4 + //HSYNC_WIDTH_L HSYNC=32 + 0385 0020 + //VSYNC_WIDTH_L VSYNC=2 + 0386 0002 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0387 0000 + //VFP_L VFP=200 + 03A5 00C8 + //VBP_H + 03A7 0000 + //VFP_H/VBP_L VBP=8 + 03A6 0008 + //VRES_L VRES=0X02D0=720 + 03A8 00D0 + //VRES_H + 03A9 0002 + //HFP_L HFP=56 + 03AA 0038 + //HBP_H + 03AC 0003 + //HFP_H/HBP_L(4bit) HBP=56 + 03AB 0008 + //HRES_L HRES=0X0780=1920 + 03AD 0080 + //HRES_H + 03AE 0007 + //Disable FIFO/DESKEW_EN + 03A4 00C0 + //HSYNC_WIDTH_L HSYNC=40 + 0395 0028 + //VSYNC_WIDTH_L VSYNC=20 + 0396 0014 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0397 0000 + //VFP_L VFP=15 + 03B1 000F + //VBP_H + 03B3 0000 + //VFP_H/VBP_L VBP=10 + 03B2 000A + //VRES_L VRES=0X0438=1080 + 03B4 0038 + //VRES_H + 03B5 0004 + //HFP_L HFP=140 + 03B6 008C + //HBP_H + 03B8 0006 + //HFP_H/HBP_L HBP=100 + 03B7 0004 + //HRES_L HRES=0X0780=1920 + 03B9 0080 + //HRES_H + 03BA 0007 + //Disable FIFO/DESKEW_EN + 03B0 00C0 + //Turn on video pipe + 0002 0033 + //Enable splitter mode reset one shot + 0010 0021 + ffff f000 //0xf000 ms delay + ]; + + i2c2_max96789_pinctrl: i2c2-max96789-pinctrl { + compatible = "maxim,max96789-pinctrl"; + pinctrl-names = "init","sleep"; + pinctrl-0 = <&i2c2_max96789_pinctrl_pins>; + pinctrl-1 = <&i2c2_max96789_pinctrl_pins>; + status = "okay"; + i2c2_max96789_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96789_I2C"; + function = "MAX96789_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96789_MFP7"; + function = "SER_TXID4_TO_DES"; + }; + tp-int { + pins = "MAX96789_MFP8"; + function = "DES_RXID8_TO_SER"; + }; + }; + + i2c2_max96789_gpio: i2c2-max96789-gpio { + compatible = "maxim,max96789-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96789_pinctrl 0 160 20>; + }; + }; + + i2c2_max96789_bridge: i2c2-max96789-bridge { + compatible = "maxim,max96789-bridge"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96789_from_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_max96789>; + }; + }; + + port@1 { + reg = <1>; + i2c2_max96789_out_i2c2_max96752: endpoint { + remote-endpoint = <&i2c2_max96752_from_i2c2_max96789>; + }; + }; + }; + }; + }; + + i2c2_max96752: i2c2-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + //reg-hw = <0x4a>; + id-serdes-panel-split = <0x01>; + link = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0004 + ]; + + i2c2_max96752_pinctrl: i2c2-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + pinctrl-names = "init","sleep"; + pinctrl-0 = <&i2c2_max96752_panel_pins>; + pinctrl-1 = <&i2c2_max96752_panel_sleep_pins>; + status = "okay"; + + i2c2_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + lcd-bias-en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd-vdd-en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID8_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + }; + + i2c2_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c2_max96752_gpio: i2c2-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96752_pinctrl 0 180 15>; + }; + }; + + i2c2_max96752_panel: i2c2-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "okay"; + + backlight = <&backlight>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96752_from_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_out_i2c2_max96752>; + }; + }; + }; + }; + }; + + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi0>; + pinctrl-1 = <&touch_gpio_dsi0>; + himax,location = "himax-touch-dsi0"; + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c4_max96749: i2c4-max96749@42 { + compatible = "maxim,max96749"; + reg = <0x42>; + dual-link; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_serdes_pins>; + lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + + //ASYM_WR_B_MUX_Y + 05CE 003F + //ASYM_WAIT_LINE_FOR_READ_X + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y + 05D1 00F8 + //ASYM_VID_EN_W_VS_X + 04CF 00BF + //ASYM_VID_EN_W_VS_Y + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 0000 + //X_M_m + 04C1 00E1 + //X_M_h + 04C2 004B + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0000 + //X_X_MAX_h + 04C9 000A + //X_Y_MAX_l + 04CA 0040 + //X_Y_MAX_h + 04CB 0006 + //X_vs_dly_l + 04D8 00E0 + //X_vs_dly_m + 04D9 009E + //X_vs_dly_h + 04DA 0049 + //X_vs_high_l + 04DB 00B0 + //X_vs_high_m + 04DC 0022 + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 0070 + //X_vs_low_m + 04DF 001F + //X_vs_low_h + 04E0 0002 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0020 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 0070 + //X_hs_low_h + 04E7 000B + //X_hs_cnt_l + 04E8 0090 + //X_hs_cnt_h + 04E9 0006 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 0060 + //X_de_dly_m + 04EE 0001 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0000 + //X_de_high_h + 04F1 000A + //X_de_low_l + 04F2 0090 + //X_de_low_h + 04F3 0001 + //X_de_cnt_l + 04F4 0040 + //X_de_cnt_h + 04F5 0006 + //X_de_llow_l + 04F6 00A0 + //X_de_llow_m + 04F7 009B + //X_de_llow_h + 04F8 0003 + //Y_M + 05C0 0000 + //Y_M_h + 05C1 00E1 + //Y_M_h + 05C2 004B + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0000 + //Y_X_OFFSET_h + 05C7 000A + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 0014 + //Y_Y_MAX_l + 05CA 0040 + //Y_Y_MAX_h + 05CB 0006 + //Y_vs_dly_l + 05D8 00E0 + //Y_vs_dly_m + 05D9 009E + //Y_vs_dly_h + 05DA 0049 + //Y_vs_high_l + 05DB 00B0 + //Y_vs_high_m + 05DC 0022 + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 0070 + //Y_vs_low_m + 05DF 001F + //Y_vs_low_h + 05E0 0002 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0020 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 0070 + //Y_hs_low_h + 05E7 000B + //Y_hs_cnt_l + 05E8 0090 + //Y_hs_cnt_h + 05E9 0006 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 0060 + //Y_de_dly_m + 05EE 0001 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0000 + //Y_de_high_h + 05F1 000A + //Y_de_low_l + 05F2 0090 + //Y_de_low_h + 05F3 0001 + //Y_de_cnt_l + 05F4 0040 + //Y_de_cnt_h + 05F5 0006 + //Y_de_llow_l + 05F6 00A0 + //Y_de_llow_m + 05F7 009B + //Y_de_llow_h + 05F8 0003 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; + + i2c4_max96749_pinctrl: i2c4-max96749-pinctrl { + compatible = "maxim,max96749-pinctrl"; + pinctrl-names = "init", "sleep"; + pinctrl-0 = <&i2c4_max96749_pinctrl_pins>; + pinctrl-1 = <&i2c4_max96749_pinctrl_pins>; + status = "okay"; + + i2c4_max96749_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96749_I2C"; + function = "MAX96749_I2C"; + }; + tp-int { + pins = "MAX96749_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + }; + + i2c4_max96749_gpio: i2c4-max96749-gpio { + compatible = "maxim,max96749-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96749_pinctrl 0 200 25>; + }; + }; + + i2c4_max96749_bridge: i2c4-max96749-bridge { + compatible = "maxim,max96749-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c4_max96749_from_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_max96749>; + }; + }; + port@1 { + reg = <1>; + i2c4_max96749_out_i2c4_max96772: endpoint { + remote-endpoint = <&i2c4_max96772_from_i2c4_max96749>; + }; + }; + }; + }; + + i2c4_max96772: i2c4-max96772@48 { + compatible = "maxim,max96772"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + + ]; + + i2c4_max96772_pinctrl: i2c4-max96772-pinctrl { + compatible = "maxim,max96772-pinctrl"; + status = "okay"; + + pinctrl-names = "init","sleep"; + pinctrl-0 = <&i2c4_max96772_panel_pins>; + pinctrl-1 = <&i2c4_max96772_panel_pins>; + + i2c4_max96772_panel_pins: panel-pins { + tp-int { + pins = "MAX96772_GPIO10"; + function = "DES_TXID1_TO_SER"; + }; + }; + + i2c4_max96772_gpio: i2c4-max96772-gpio { + compatible = "maxim,max96772-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96772_pinctrl 0 230 15>; + }; + }; + + i2c4_max96772_panel: i2c4-max96772-panel { + compatible = "maxim,max96772-panel"; + status = "okay"; + + backlight = <&dp2lvds_backlight0>; + panel-size= <324 202>; + rate-count-ssc= <10 4 0>; + + panel-timing { + clock-frequency = <298400000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <320>; + vfront-porch = <30>; + vsync-len = <3>; + vback-porch = <47>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c4_max96772_from_i2c4_max96749: endpoint { + remote-endpoint = <&i2c4_max96749_out_i2c4_max96772>; + }; + }; + }; + }; + + i2c4_r7f701_pwm: i2c4-r7f701-pwm@77 { + compatible = "r7f701-pwm"; + #pwm-cells = <3>; + reg = <0x77>; + status = "okay"; + }; + + i2c4_cyttsp7: i2c4-cyttsp7@24 { + compatible = "cy,cyttsp7_i2c_adapter"; + reg = <0x24>; + status = "okay"; + + cy,core { + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_dp0>; + cy,irq_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + cy,rst_gpio = <&i2c4_max96772_gpio 7 GPIO_ACTIVE_HIGH>; + + cy,max_xfer_len = <0x100>; + + /* CY_CORE_FLAG_WAKE_ON_GESTURE */ + /* cy,flags = <1>; */ + /* CY_CORE_EWG_TAP_TAP | CY_CORE_EWG_TWO_FINGER_SLIDE */ + /* cy,easy_wakeup_gesture = <3>; */ + cy,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + cy,btn_keys-tag = <0>; + + cy,mt { + cy,inp_dev_name = "cyttsp7-mt-dp0"; + /* CY_MT_FLAG_FLIP | CY_MT_FLAG_INV_X | CY_MT_FLAG_INV_Y */ + cy,flags = <0x20>; + cy,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + < + 0x35 0 2560 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1600 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0 + /* SRI:ABS_MT_DISTANCE, 0,MAX, 0, 0 */ + 0x3b 0 255 0 0>; + + cy,vkeys_x = <2560>; + cy,vkeys_y = <1600>; + + cy,virtual_keys = /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 1360 90 160 180 + /* KEY_MENU */ + 139 1360 270 160 180 + /* KEY_HOMEPAGE */ + 172 1360 450 160 180 + /* KEY SEARCH */ + 217 1360 630 160 180>; + }; + + cy,btn { + cy,inp_dev_name = "cyttsp7-btn-dp0"; + }; + + cy,proximity { + cy,inp_dev_name = "cyttsp7-proximity-dp0"; + cy,abs = + /* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */ + <0x19 0 1 0 0>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + i2c5_max96749: i2c5-max96749@42 { + compatible = "maxim,max96749"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_serdes_pins>; + lock-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-bridge-split = <0x02>; + status = "okay"; + + serdes-init-sequence = [ + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + //ASYM_WR_B_MUX_Y + 05CE 0037 + //ASYM_WAIT_LINE_FOR_READ_X + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y + 05D1 00F8 + //ASYM_VID_EN_W_VS_X + 04CF 00BF + //ASYM_VID_EN_W_VS_Y + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 00F8 + //X_M_m + 04C1 00C3 + //X_M_h + 04C2 0025 + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0080 + //X_X_MAX_h + 04C9 0007 + //X_Y_MAX_l + 04CA 0038 + //X_Y_MAX_h + 04CB 0004 + //Y_M + 05C0 00F8 + //Y_M_h + 05C1 00C3 + //Y_M_h + 05C2 0025 + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0080 + //Y_X_OFFSET_h + 05C7 0007 + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 000F + //Y_Y_MAX_l + 05CA 0038 + //Y_Y_MAX_h + 05CB 0004 + //X_vs_dly_l + 04D8 0028 + //X_vs_dly_m + 04D9 00C2 + //X_vs_dly_h + 04DA 0024 + //X_vs_high_l + 04DB 00E0 + //X_vs_high_m + 04DC 00AB + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 00F0 + //X_vs_low_m + 04DF 0055 + //X_vs_low_h + 04E0 0000 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0028 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 0070 + //X_hs_low_h + 04E7 0008 + //X_hs_cnt_l + 04E8 0065 + //X_hs_cnt_h + 04E9 0004 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 008C + //X_de_dly_m + 04EE 0000 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0080 + //X_de_high_h + 04F1 0007 + //X_de_low_l + 04F2 0018 + //X_de_low_h + 04F3 0001 + //X_de_cnt_l + 04F4 0038 + //X_de_cnt_h + 04F5 0004 + //X_de_llow_l + 04F6 002C + //X_de_llow_m + 04F7 0082 + //X_de_llow_h + 04F8 0001 + + //Y_vs_dly_l + 05D8 0028 + //Y_vs_dly_m + 05D9 00C2 + //Y_vs_dly_h + 05DA 0024 + //Y_vs_high_l + 05DB 00E0 + //Y_vs_high_m + 05DC 00AB + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 00F0 + //Y_vs_low_m + 05DF 0055 + //Y_vs_low_h + 05E0 0000 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0028 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 0070 + //Y_hs_low_h + 05E7 0008 + //Y_hs_cnt_l + 05E8 0065 + //Y_hs_cnt_h + 05E9 0004 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 008C + //Y_de_dly_m + 05EE 0000 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0080 + //Y_de_high_h + 05F1 0007 + //Y_de_low_l + 05F2 0018 + //Y_de_low_h + 05F3 0001 + //Y_de_cnt_l + 05F4 0038 + //Y_de_cnt_h + 05F5 0004 + //Y_de_llow_l + 05F6 002C + //Y_de_llow_m + 05F7 0082 + //Y_de_llow_h + 05F8 0001 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; + + i2c5_max96749_pinctrl: i2c5-max96749-pinctrl { + compatible = "maxim,max96749-pinctrl"; + pinctrl-names = "init", "sleep"; + pinctrl-0 = <&i2c5_max96749_pinctrl_pins>; + pinctrl-1 = <&i2c5_max96749_pinctrl_pins>; + status = "okay"; + + i2c5_max96749_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96749_I2C"; + function = "MAX96749_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96749_MFP0"; + function = "SER_TXID4_TO_DES_LINKA"; + }; + tp-int { + pins = "MAX96749_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + }; + + i2c5_max96749_gpio: i2c5-max96749-gpio { + compatible = "maxim,max96749-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96749_pinctrl 0 250 25>; + }; + }; + + i2c5_max96749_bridge: i2c5-max96749-bridge { + compatible = "maxim,max96749-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_max96749_from_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_max96749>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_max96749_out_i2c5_max96752: endpoint { + remote-endpoint = <&i2c5_max96752_from_i2c5_max96749>; + }; + }; + }; + }; + + i2c5_max96752: i2c5-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0004 + ]; + + i2c5_max96752_pinctrl: i2c5-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + pinctrl-names = "init","sleep"; + pinctrl-0 = <&i2c5_max96752_panel_pins>; + pinctrl-1 = <&i2c5_max96752_panel_sleep_pins>; + + i2c5_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID1_TO_SER"; + }; + 40ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_40MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c5_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c5_max96752_gpio: i2c5-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96752_pinctrl 0 280 15>; + }; + }; + + i2c5_max96752_panel: i2c5-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "okay"; + + backlight = <&edp2lvds_backlight0>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c5_max96752_from_i2c5_max96749: endpoint { + remote-endpoint = <&i2c5_max96749_out_i2c5_max96752>; + }; + }; + }; + }; + + ilitek@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_edp0>; + //reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + ilitek,name = "ilitek_i2c"; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c8_max96749: i2c8-max96749@42 { + compatible = "maxim,max96749"; + reg = <0x42>; + dual-link; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_serdes_pins>; + lock-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + + //ASYM_WR_B_MUX_Y + 05CE 0037 + //ASYM_WAIT_LINE_FOR_READ_X + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y + 05D1 00F8 + //ASYM_VID_EN_W_VS_X + 04CF 00BF + //ASYM_VID_EN_W_VS_Y + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 0000 + //X_M_m + 04C1 00E1 + //X_M_h + 04C2 004B + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0000 + //X_X_MAX_h + 04C9 000A + //X_Y_MAX_l + 04CA 0040 + //X_Y_MAX_h + 04CB 0006 + //X_vs_dly_l + 04D8 00E0 + //X_vs_dly_m + 04D9 009E + //X_vs_dly_h + 04DA 0049 + //X_vs_high_l + 04DB 00B0 + //X_vs_high_m + 04DC 0022 + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 0070 + //X_vs_low_m + 04DF 001F + //X_vs_low_h + 04E0 0002 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0020 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 0070 + //X_hs_low_h + 04E7 000B + //X_hs_cnt_l + 04E8 0090 + //X_hs_cnt_h + 04E9 0006 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 0060 + //X_de_dly_m + 04EE 0001 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0000 + //X_de_high_h + 04F1 000A + //X_de_low_l + 04F2 0090 + //X_de_low_h + 04F3 0001 + //X_de_cnt_l + 04F4 0040 + //X_de_cnt_h + 04F5 0006 + //X_de_llow_l + 04F6 00A0 + //X_de_llow_m + 04F7 009B + //X_de_llow_h + 04F8 0003 + //Y_M + 05C0 0000 + //Y_M_h + 05C1 00E1 + //Y_M_h + 05C2 004B + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0000 + //Y_X_OFFSET_h + 05C7 000A + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 0014 + //Y_Y_MAX_l + 05CA 0040 + //Y_Y_MAX_h + 05CB 0006 + //Y_vs_dly_l + 05D8 00E0 + //Y_vs_dly_m + 05D9 009E + //Y_vs_dly_h + 05DA 0049 + //Y_vs_high_l + 05DB 00B0 + //Y_vs_high_m + 05DC 0022 + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 0070 + //Y_vs_low_m + 05DF 001F + //Y_vs_low_h + 05E0 0002 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0020 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 0070 + //Y_hs_low_h + 05E7 000B + //Y_hs_cnt_l + 05E8 0090 + //Y_hs_cnt_h + 05E9 0006 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 0060 + //Y_de_dly_m + 05EE 0001 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0000 + //Y_de_high_h + 05F1 000A + //Y_de_low_l + 05F2 0090 + //Y_de_low_h + 05F3 0001 + //Y_de_cnt_l + 05F4 0040 + //Y_de_cnt_h + 05F5 0006 + //Y_de_llow_l + 05F6 00A0 + //Y_de_llow_m + 05F7 009B + //Y_de_llow_h + 05F8 0003 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; + + i2c8_max96749_pinctrl: i2c8-max96749-pinctrl { + compatible = "maxim,max96749-pinctrl"; + pinctrl-names = "init", "sleep"; + pinctrl-0 = <&i2c8_max96749_pinctrl_pins>; + pinctrl-1 = <&i2c8_max96749_pinctrl_pins>; + status = "okay"; + + i2c8_max96749_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96749_I2C"; + function = "MAX96749_I2C"; + }; + tp-int { + pins = "MAX96749_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + }; + + i2c8_max96749_gpio: i2c8-max96749-gpio { + compatible = "maxim,max96749-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_max96749_pinctrl 0 300 25>; + }; + }; + + i2c8_max96749_bridge: i2c8-max96749-bridge { + compatible = "maxim,max96749-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96749_from_dp1: endpoint { + remote-endpoint = <&dp1_out_i2c8_max96749>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96749_out_i2c8_max96772: endpoint { + remote-endpoint = <&i2c8_max96772_from_i2c8_max96749>; + }; + }; + }; + }; + + i2c8_max96772: i2c8-max96772@48 { + compatible = "maxim,max96772"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + + ]; + + i2c8_max96772_pinctrl: i2c8-max96772-pinctrl { + compatible = "maxim,max96772-pinctrl"; + status = "okay"; + + pinctrl-names = "init","sleep"; + pinctrl-0 = <&i2c8_max96772_panel_pins>; + pinctrl-1 = <&i2c8_max96772_panel_pins>; + + i2c8_max96772_panel_pins: panel-pins { + tp-int { + pins = "MAX96772_GPIO10"; + function = "DES_TXID1_TO_SER"; + }; + }; + + i2c8_max96772_gpio: i2c8-max96772-gpio { + compatible = "maxim,max96772-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_max96772_pinctrl 0 330 15>; + }; + }; + + i2c8_max96772_panel: i2c8-max96772-panel { + compatible = "maxim,max96772-panel"; + status = "okay"; + + backlight = <&dp2lvds_backlight1>; + panel-size= <324 202>; + rate-count-ssc= <10 4 0>; + + panel-timing { + clock-frequency = <298400000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <320>; + vfront-porch = <30>; + vsync-len = <3>; + vback-porch = <47>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96772_from_i2c8_max96749: endpoint { + remote-endpoint = <&i2c8_max96749_out_i2c8_max96772>; + }; + }; + }; + }; + + i2c8_r7f701_pwm: i2c8-r7f701-pwm@77 { + compatible = "r7f701-pwm"; + #pwm-cells = <3>; + reg = <0x77>; + status = "okay"; + }; + + i2c8_cyttsp7: i2c8-cyttsp7@24 { + compatible = "cy,cyttsp7_i2c_adapter"; + reg = <0x24>; + + status = "okay"; + cy,core { + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_dp1>; + cy,irq_gpio = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + cy,rst_gpio = <&i2c8_max96772_gpio 7 GPIO_ACTIVE_HIGH>; + + cy,max_xfer_len = <0x100>; + + /* CY_CORE_FLAG_WAKE_ON_GESTURE */ + /* cy,flags = <1>; */ + /* CY_CORE_EWG_TAP_TAP | CY_CORE_EWG_TWO_FINGER_SLIDE */ + /* cy,easy_wakeup_gesture = <3>; */ + cy,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + cy,btn_keys-tag = <0>; + + cy,mt { + cy,inp_dev_name = "cyttsp7-mt-dp1"; + /* CY_MT_FLAG_FLIP | CY_MT_FLAG_INV_X | CY_MT_FLAG_INV_Y */ + cy,flags = <0x20>; + cy,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + < + 0x35 0 2560 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1600 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0 + /* SRI:ABS_MT_DISTANCE, 0,MAX, 0, 0 */ + 0x3b 0 255 0 0>; + + cy,vkeys_x = <2560>; + cy,vkeys_y = <1600>; + + cy,virtual_keys = /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 1360 90 160 180 + /* KEY_MENU */ + 139 1360 270 160 180 + /* KEY_HOMEPAGE */ + 172 1360 450 160 180 + /* KEY SEARCH */ + 217 1360 630 160 180>; + }; + + cy,btn { + cy,inp_dev_name = "cyttsp7-btn-dp1"; + }; + + cy,proximity { + cy,inp_dev_name = "cyttsp7-proximity-dp1"; + cy,abs = + /* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */ + <0x19 0 1 0 0>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&pinctrl { + serdes { + /*dsi0*/ + i2c2_serdes_pins: i2c2-serdes-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + /*dp0*/ + i2c4_serdes_pins: i2c4-serdes-pins { + rockchip,pins = + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + /*edp0*/ + i2c5_serdes_pins: i2c5-serdes-pins { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + /*dsi1*/ + i2c6_serdes_pins: i2c6-serdes-pins { + rockchip,pins = + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + /*edp1*/ + i2c7_serdes_pins: i2c7-serdes-pins { + rockchip,pins = + <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + /*dp1*/ + i2c8_serdes_pins: i2c8-serdes-pins { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,/*err*/ + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;/*lock*/ + }; + }; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; //v23 hw change to PWM2_M1(GPIO3_B1) +}; + +/* dp1->serdes->lvds_panel */ +&pwm1 { + pinctrl-0 = <&pwm1m2_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp2_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp3_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +//dp0 +&vp0 { + assigned-clocks = <&cru DCLK_VOP0>; + assigned-clock-parents = <&hdptxphy_hdmi1>; +}; + +//edp +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +//dp1 +&vp2 { + assigned-clocks = <&cru DCLK_VOP2>; + assigned-clock-parents = <&hdptxphy_hdmi1>; +}; + +//dsi0 +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; From 0e41810ce36ea6b8faba55556e0ff572ac7e83d2 Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Mon, 19 May 2025 16:59:54 +0800 Subject: [PATCH 13/25] media: i2c: maxim: remote: add ox03c10 sensor driver Signed-off-by: Cai Wenzhong Change-Id: If545395a7d420ab84347cb31ddf8a0c8687af688 --- drivers/media/i2c/maxim/remote/Kconfig | 9 + drivers/media/i2c/maxim/remote/Makefile | 2 + drivers/media/i2c/maxim/remote/ox03c10.c | 6042 ++++++++++++++++++++++ 3 files changed, 6053 insertions(+) create mode 100644 drivers/media/i2c/maxim/remote/ox03c10.c diff --git a/drivers/media/i2c/maxim/remote/Kconfig b/drivers/media/i2c/maxim/remote/Kconfig index f826eec06613..220bf8aff589 100644 --- a/drivers/media/i2c/maxim/remote/Kconfig +++ b/drivers/media/i2c/maxim/remote/Kconfig @@ -74,6 +74,15 @@ config VIDEO_MAXIM_CAM_OV231X To compile this driver as a module, choose M here: the module will be called ov231x. +config VIDEO_MAXIM_CAM_OX03C10 + tristate "Maxim Remote Sensor ox03c10 support" + depends on VIDEO_MAXIM_SERDES + help + This driver supports the remote sensor ox03c10. + + To compile this driver as a module, choose M here: the + module will be called ox03c10. + config VIDEO_MAXIM_CAM_OX03J10 tristate "Maxim Remote Sensor ox03j10 support" depends on VIDEO_MAXIM_SERDES diff --git a/drivers/media/i2c/maxim/remote/Makefile b/drivers/media/i2c/maxim/remote/Makefile index 96144938baa9..82c85bc7e18c 100644 --- a/drivers/media/i2c/maxim/remote/Makefile +++ b/drivers/media/i2c/maxim/remote/Makefile @@ -8,6 +8,7 @@ maxim-dummy-objs := dummy.o maxim-sc320at-objs := sc320at.o maxim-ox01f10-objs := ox01f10.o maxim-ov231x-objs := ov231x.o +maxim-ox03c10-objs := ox03c10.o maxim-ox03j10-objs := ox03j10.o maxim-os04a10-objs := os04a10.o @@ -15,5 +16,6 @@ obj-$(CONFIG_VIDEO_MAXIM_CAM_DUMMY) += maxim-dummy.o obj-$(CONFIG_VIDEO_MAXIM_CAM_SC320AT) += maxim-sc320at.o obj-$(CONFIG_VIDEO_MAXIM_CAM_OX01F10) += maxim-ox01f10.o obj-$(CONFIG_VIDEO_MAXIM_CAM_OV231X) += maxim-ov231x.o +obj-$(CONFIG_VIDEO_MAXIM_CAM_OX03C10) += maxim-ox03c10.o obj-$(CONFIG_VIDEO_MAXIM_CAM_OX03J10) += maxim-ox03j10.o obj-$(CONFIG_VIDEO_MAXIM_CAM_OS04A10) += maxim-os04a10.o diff --git a/drivers/media/i2c/maxim/remote/ox03c10.c b/drivers/media/i2c/maxim/remote/ox03c10.c new file mode 100644 index 000000000000..999259b398e0 --- /dev/null +++ b/drivers/media/i2c/maxim/remote/ox03c10.c @@ -0,0 +1,6042 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Maxim Remote Sensor OmniVision OX03C10 driver + * + * Copyright (C) 2025 Rockchip Electronics Co., Ltd. + * + * Author: Cai Wenzhong + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "maxim_remote.h" + +#define DRIVER_VERSION KERNEL_VERSION(1, 0x00, 0x01) + +#ifndef V4L2_CID_DIGITAL_GAIN +#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN +#endif + +#define OX03C10_NAME "ox03c10" + +#define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode" +#define OF_CAMERA_HDR_OPERATING_MODE "hdr-operating-mode" + +#define OX03C10_XVCLK_FREQ 24000000 + +#define OX03C10_LINK_FREQ_300MHZ 300000000 +#define OX03C10_LINK_FREQ_480MHZ 480000000 + +#define OX03C10_CHIP_ID 0x005803 +#define OX03C10_REG_CHIP_ID 0x300A + +#define OX03C10_REG_CTRL_MODE 0x0100 +#define OX03C10_MODE_SW_STANDBY 0x0 +#define OX03C10_MODE_STREAMING BIT(0) + +#define OX03C10_VTS_MAX 0x7FFF + +#define OX03C10_GAIN_MIN 0x10 +#define OX03C10_GAIN_MAX 0xF7F +#define OX03C10_GAIN_STEP 0x01 +#define OX03C10_GAIN_DEFAULT 0x30 + +// exposure ctrl reg for DCG +#define OX03C10_EXPOSURE_HCG_MIN 4 +#define OX03C10_EXPOSURE_HCG_STEP 1 +#define OX03C10_REG_EXPOSURE_DCG_H 0x3501 // bit[7:0] for exposure[15:8] +#define OX03C10_REG_EXPOSURE_DCG_L 0x3502 // bit[7:0] for exposure[7:0] + +// gain ctrl reg for HCG +#define OX03C10_REG_AGAIN_HCG_H 0x3508 // bit[3:0] for RealGain[7:4] +#define OX03C10_REG_AGAIN_HCG_L 0x3509 // bit[7:4] for RealGain[3:0] +#define OX03C10_REG_DGAIN_HCG_H 0x350A // bit[3:0] for DigitalGain[13:10] +#define OX03C10_REG_DGAIN_HCG_M 0x350B // bit[7:0] for DigitalGain[9:2] +#define OX03C10_REG_DGAIN_HCG_L 0x350C // bit[7:6] for DigitalGain[1:0] + +// gain ctrl reg for LCG +#define OX03C10_REG_AGAIN_LCG_H 0x3588 // bit[3:0] for RealGain[7:4] +#define OX03C10_REG_AGAIN_LCG_L 0x3589 // bit[7:4] for RealGain[3:0] +#define OX03C10_REG_DGAIN_LCG_H 0x358A // bit[3:0] for DigitalGain[13:10] +#define OX03C10_REG_DGAIN_LCG_M 0x358B // bit[7:0] for DigitalGain[9:2] +#define OX03C10_REG_DGAIN_LCG_L 0x358C // bit[7:6] for DigitalGain[1:0] + +// exposure and gain ctrl reg for SPD +#define OX03C10_EXPOSURE_SPD_MIN 4 +#define OX03C10_EXPOSURE_SPD_STEP 1 +#define OX03C10_REG_EXPOSURE_SPD_H 0x3541 // bit[7:0] for exposure[15:8] +#define OX03C10_REG_EXPOSURE_SPD_L 0x3542 // bit[7:0] for exposure[7:0] +#define OX03C10_REG_AGAIN_SPD_H 0x3548 // bit[3:0] for RealGain[7:4] +#define OX03C10_REG_AGAIN_SPD_L 0x3549 // bit[7:4] for RealGain[3:0] +#define OX03C10_REG_DGAIN_SPD_H 0x354A // bit[3:0] for DigitalGain[13:10] +#define OX03C10_REG_DGAIN_SPD_M 0x354B // bit[7:0] for DigitalGain[9:2] +#define OX03C10_REG_DGAIN_SPD_L 0x354C // bit[7:6] for DigitalGain[1:0] + +// exposure and gain ctrl reg for VS +#define OX03C10_EXPOSURE_VS_MIN 4 +#define OX03C10_EXPOSURE_VS_STEP 1 +#define OX03C10_REG_EXPOSURE_VS_H 0x35C1 // bit[7:0] for exposure[15:8] +#define OX03C10_REG_EXPOSURE_VS_L 0x35C2 // bit[7:0] for exposure[7:0] +#define OX03C10_REG_AGAIN_VS_H 0x35C8 // bit[3:0] for RealGain[7:4] +#define OX03C10_REG_AGAIN_VS_L 0x35C9 // bit[7:4] for RealGain[3:0] +#define OX03C10_REG_DGAIN_VS_H 0x35CA // bit[3:0] for DigitalGain[13:10] +#define OX03C10_REG_DGAIN_VS_M 0x35CB // bit[7:0] for DigitalGain[9:2] +#define OX03C10_REG_DGAIN_VS_L 0x35CC // bit[7:6] for DigitalGain[1:0] + +#define OX03C10_GROUP_UPDATE_ADDRESS 0x3208 +#define OX03C10_GROUP_UPDATE_START_DATA 0x00 +#define OX03C10_GROUP_UPDATE_END_DATA 0x10 +#define OX03C10_GROUP_UPDATE_LAUNCH 0xA0 + +#define OX03C10_GROUP1_UPDATE_START_DATA 0x01 +#define OX03C10_GROUP1_UPDATE_END_DATA 0x11 +#define OX03C10_GROUP1_UPDATE_LAUNCH 0xA1 + +#define OX03C10_REG_TEST_PATTERN 0x5040 +#define OX03C10_TEST_PATTERN_ENABLE 0x80 +#define OX03C10_TEST_PATTERN_DISABLE 0x0 + +#define OX03C10_REG_VTS 0x380E + +#define OX03C10_REG_HCG_B_GAIN 0x5280 +#define OX03C10_REG_HCG_GB_GAIN 0x5282 +#define OX03C10_REG_HCG_GR_GAIN 0x5284 +#define OX03C10_REG_HCG_R_GAIN 0x5286 + +#define OX03C10_REG_LCG_B_GAIN 0x5480 +#define OX03C10_REG_LCG_GB_GAIN 0x5482 +#define OX03C10_REG_LCG_GR_GAIN 0x5484 +#define OX03C10_REG_LCG_R_GAIN 0x5486 + +#define OX03C10_REG_SPD_B_GAIN 0x5680 +#define OX03C10_REG_SPD_GB_GAIN 0x5682 +#define OX03C10_REG_SPD_GR_GAIN 0x5684 +#define OX03C10_REG_SPD_R_GAIN 0x5686 + +#define OX03C10_REG_VS_B_GAIN 0x5880 +#define OX03C10_REG_VS_GB_GAIN 0x5882 +#define OX03C10_REG_VS_GR_GAIN 0x5884 +#define OX03C10_REG_VS_R_GAIN 0x5886 + +#define OX03C10_REG_HCG_BLC 0x4026 +#define OX03C10_REG_LCG_BLC 0x4028 +#define OX03C10_REG_SPD_BLC 0x402A +#define OX03C10_REG_VS_BLC 0x402C + +#define OX03C10_VFLIP_REG 0x3820 +#define MIRROR_BIT_MASK BIT(5) +#define FLIP_BIT_MASK BIT(2) + +/* I2C default address */ +#define OX03C10_I2C_ADDR_DEF 0x36 + +/* register address: 16bit */ +#define OX03C10_REG_ADDR_16BITS 2 + +/* register value: 8bit or 16bit or 24bit */ +#define OX03C10_REG_VALUE_08BIT 1 +#define OX03C10_REG_VALUE_16BIT 2 +#define OX03C10_REG_VALUE_24BIT 3 + +#define I2C_REG_NULL 0xFFFF +#define I2C_REG_DELAY 0xFFEE + +struct i2c_regval { + u16 reg_addr; + u8 reg_val; +}; + +/* + * ox03c10 hdr operating mode + * + * Note: Please confirm if the SoC supports RAW16 + * + * Each Pixel has two photo diodes with independent + * exposure gain controls to extend the dynamic range. + * + * LPD: Large Photo Diode + * LPD for HCG, LCG and VS + * SPD: Small Photo Diode + * + * DCG: Dual Conversion Gain + * HCG: High Conversion Gain + * LCG: Low Conversion Gain + * VS: Very Short Exposure + * + * PWL: PieceWise Linear + * HDR3: PWL12, PWL14, PWL16 + * HDR4: PWL12, PWL14, PWL16, PWL20 + * + * LFM: LED Flicker Mitigation + * + * HDR3: DCG (HCG + LCG) + VS or DCG (HCG + LCG) + SPD + * uncompressed 20bit + * HDR4: DCG (HCG + LCG) + SPD + VS + * uncompressed 24bit + */ +enum ox03c10_hdr_operating_mode { + OX03C10_HDR3_DCG_VS_12BIT = 0, + OX03C10_HDR3_DCG_SPD_12BIT = 1, + OX03C10_HDR3_DCG_VS_LFM_16BIT = 2, + OX03C10_HDR_OPERATING_MODE_MAX, +}; + +struct ox03c10_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + u32 exp_mode; + + u32 link_freq_idx; + u32 bpp; + u32 hdr_mode; + struct rkmodule_hdr_compr *hdr_compr; + u32 hdr_operating_mode; + u32 vc[PAD_MAX]; + const struct i2c_regval *reg_list; + const struct i2c_regval *linear_reg_list; +}; + +struct ox03c10 { + struct i2c_client *client; + struct regulator *poc_regulator; + + struct mutex mutex; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + struct v4l2_ctrl *test_pattern; + + struct v4l2_fwnode_endpoint bus_cfg; + + bool streaming; + bool power_on; + + const struct ox03c10_mode *supported_modes; + const struct ox03c10_mode *cur_mode; + u32 cfg_modes_num; + + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + + bool has_init_exp; + bool has_init_wbgain; + struct preisp_hdrae_exp_s init_hdrae_exp; + struct rkmodule_wb_gain_group init_wbgain; + struct rkmodule_dcg_ratio dcg_ratio; + struct rkmodule_dcg_ratio spd_ratio; + + u8 cam_i2c_addr_def; + u8 cam_i2c_addr_map; + + struct maxim_remote_ser *remote_ser; +}; + +/* + * hdr_operating_mode: OX03C10_HDR3_DCG_SPD_12BIT + */ +static const struct i2c_regval ox03c10_1920x1080_30fps_HDR3_DCG_SPD_PWL12_mipi600[] = { + {0x0103, 0x01}, + {0x0107, 0x01}, + {I2C_REG_DELAY, 6}, + {0x4d5a, 0x1c}, + {0x4d09, 0xff}, + {0x4d09, 0xdf}, + {0x3208, 0x04}, + {0x4620, 0x04}, + {0x3208, 0x14}, + {0x3208, 0x05}, + {0x4620, 0x04}, + {0x3208, 0x15}, + {0x3208, 0x02}, + {0x3507, 0x00}, + {0x3208, 0x12}, + {0x3208, 0xa2}, + {0x0301, 0xc8}, + {0x0303, 0x01}, + {0x0304, 0x01}, + {0x0305, 0x2c}, + {0x0306, 0x04}, + {0x0307, 0x03}, + {0x0316, 0x00}, + {0x0317, 0x00}, + {0x0318, 0x00}, + {0x0323, 0x05}, + {0x0324, 0x01}, + {0x0325, 0x2c}, + {0x032e, 0x00}, + {0x032a, 0x04}, + {0x0326, 0x09}, + {0x0327, 0x04}, + {0x0331, 0x04}, + {0x0400, 0xe0}, + {0x0401, 0x80}, + {0x0403, 0xde}, + {0x0404, 0x34}, + {0x0405, 0x3b}, + {0x0406, 0xd4}, + {0x0407, 0x08}, + {0x0408, 0xe0}, + {0x0409, 0x62}, + {0x040a, 0xde}, + {0x040b, 0x34}, + {0x040c, 0x8f}, + {0x040d, 0x9b}, + {0x040e, 0x08}, + {0x2803, 0xfe}, + {0x280b, 0x00}, + {0x280c, 0x79}, + {0x3001, 0x03}, + {0x3002, 0xf8}, + {0x3005, 0x80}, + {0x3007, 0x01}, + {0x3008, 0x80}, + {0x3012, 0x41}, + {0x3020, 0x05}, + {0x3700, 0x28}, + {0x3701, 0x15}, + {0x3702, 0x19}, + {0x3703, 0x23}, + {0x3704, 0x0a}, + {0x3705, 0x00}, + {0x3706, 0x3e}, + {0x3707, 0x0d}, + {0x3708, 0x50}, + {0x3709, 0x5a}, + {0x370a, 0x00}, + {0x370b, 0x96}, + {0x3711, 0x11}, + {0x3712, 0x13}, + {0x3717, 0x02}, + {0x3718, 0x73}, + {0x372c, 0x40}, + {0x3733, 0x01}, + {0x3738, 0x36}, + {0x3739, 0x36}, + {0x373a, 0x25}, + {0x373b, 0x25}, + {0x373f, 0x21}, + {0x3740, 0x21}, + {0x3741, 0x21}, + {0x3742, 0x21}, + {0x3747, 0x28}, + {0x3748, 0x28}, + {0x3749, 0x19}, + {0x3755, 0x1a}, + {0x3756, 0x0a}, + {0x3757, 0x1c}, + {0x3765, 0x19}, + {0x3766, 0x05}, + {0x3767, 0x05}, + {0x3768, 0x13}, + {0x376c, 0x07}, + {0x3778, 0x20}, + {0x377c, 0xc8}, + {0x3781, 0x02}, + {0x3783, 0x02}, + {0x379c, 0x58}, + {0x379e, 0x00}, + {0x379f, 0x00}, + {0x37a0, 0x00}, + {0x37bc, 0x22}, + {0x37c0, 0x01}, + {0x37c4, 0x3e}, + {0x37c5, 0x3e}, + {0x37c6, 0x2a}, + {0x37c7, 0x28}, + {0x37c8, 0x02}, + {0x37c9, 0x12}, + {0x37cb, 0x29}, + {0x37cd, 0x29}, + {0x37d2, 0x00}, + {0x37d3, 0x73}, + {0x37d6, 0x00}, + {0x37d7, 0x6b}, + {0x37dc, 0x00}, + {0x37df, 0x54}, + {0x37e2, 0x00}, + {0x37e3, 0x00}, + {0x37f8, 0x00}, + {0x37f9, 0x01}, + {0x37fa, 0x00}, + {0x37fb, 0x19}, + {0x3c03, 0x01}, + {0x3c04, 0x01}, + {0x3c06, 0x21}, + {0x3c08, 0x01}, + {0x3c09, 0x01}, + {0x3c0a, 0x01}, + {0x3c0b, 0x21}, + {0x3c13, 0x21}, + {0x3c14, 0x82}, + {0x3c16, 0x13}, + {0x3c21, 0x00}, + {0x3c22, 0xf3}, + {0x3c37, 0x12}, + {0x3c38, 0x31}, + {0x3c3c, 0x00}, + {0x3c3d, 0x03}, + {0x3c44, 0x16}, + {0x3c5c, 0x8a}, + {0x3c5f, 0x03}, + {0x3c61, 0x80}, + {0x3c6f, 0x2b}, + {0x3c70, 0x5f}, + {0x3c71, 0x2c}, + {0x3c72, 0x2c}, + {0x3c73, 0x2c}, + {0x3c76, 0x12}, + {0x3182, 0x12}, + {0x320e, 0x00}, + {0x320f, 0x00}, + {0x3211, 0x61}, + {0x3215, 0xcd}, + {0x3219, 0x08}, + {0x3506, 0x20}, + {0x350a, 0x01}, + {0x350b, 0x00}, + {0x350c, 0x00}, + {0x3586, 0x30}, + {0x358a, 0x01}, + {0x358b, 0x00}, + {0x358c, 0x00}, + {0x3541, 0x00}, + {0x3542, 0x04}, + {0x3546, 0x10}, + {0x3548, 0x04}, + {0x3549, 0x40}, + {0x354a, 0x01}, + {0x354b, 0x00}, + {0x354c, 0x00}, + {0x35c1, 0x00}, + {0x35c2, 0x02}, + {0x35c6, 0x90}, + {0x3600, 0x8f}, + {0x3605, 0x16}, + {0x3609, 0xf0}, + {0x360a, 0x01}, + {0x360e, 0x1d}, + {0x360f, 0x10}, + {0x3610, 0x70}, + {0x3611, 0x3a}, + {0x3612, 0x28}, + {0x361a, 0x29}, + {0x361b, 0x6c}, + {0x361c, 0x0b}, + {0x361d, 0x00}, + {0x361e, 0xfc}, + {0x362a, 0x00}, + {0x364d, 0x0f}, + {0x364e, 0x18}, + {0x364f, 0x12}, + {0x3653, 0x1c}, + {0x3654, 0x00}, + {0x3655, 0x1f}, + {0x3656, 0x1f}, + {0x3657, 0x0c}, + {0x3658, 0x0a}, + {0x3659, 0x14}, + {0x365a, 0x18}, + {0x365b, 0x14}, + {0x365c, 0x10}, + {0x365e, 0x12}, + {0x3674, 0x08}, + {0x3677, 0x3a}, + {0x3678, 0x3a}, + {0x3679, 0x19}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3806, 0x05}, + {0x3807, 0x0b}, + {0x3808, 0x07}, + {0x3809, 0x80}, + {0x380a, 0x04}, + {0x380b, 0x38}, + {0x380c, 0x08}, + {0x380d, 0x8e}, + {0x380e, 0x02}, + {0x380f, 0xae}, + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x68}, + {0x3816, 0x01}, + {0x3817, 0x01}, + {0x381c, 0x18}, + {0x381e, 0x01}, + {0x381f, 0x01}, + {0x3820, 0x00}, + {0x3821, 0x19}, + {0x3832, 0x00}, + {0x3834, 0x00}, + {0x384c, 0x04}, + {0x384d, 0x1a}, + {0x3850, 0x00}, + {0x3851, 0x42}, + {0x3852, 0x00}, + {0x3853, 0x40}, + {0x3858, 0x04}, + {0x388c, 0x04}, + {0x388d, 0x56}, + {0x3b40, 0x05}, + {0x3b41, 0x40}, + {0x3b42, 0x00}, + {0x3b43, 0x90}, + {0x3b44, 0x02}, + {0x3b45, 0x00}, + {0x3b46, 0x02}, + {0x3b47, 0x00}, + {0x3b48, 0x19}, + {0x3b49, 0x12}, + {0x3b4a, 0x16}, + {0x3b4b, 0x2e}, + {0x3b4c, 0x03}, + {0x3b4d, 0x00}, + {0x3b86, 0x00}, + {0x3b87, 0x34}, + {0x3b88, 0x00}, + {0x3b89, 0x08}, + {0x3b8a, 0x05}, + {0x3b8b, 0x00}, + {0x3b8c, 0x07}, + {0x3b8d, 0x80}, + {0x3b8e, 0x00}, + {0x3b8f, 0x00}, + {0x3b92, 0x05}, + {0x3b93, 0x00}, + {0x3b94, 0x07}, + {0x3b95, 0x80}, + {0x3b9e, 0x09}, + {0x3d85, 0x05}, + {0x3d8a, 0x03}, + {0x3d8b, 0xff}, + {0x3d99, 0x00}, + {0x3d9a, 0x9f}, + {0x3d9b, 0x00}, + {0x3d9c, 0xa0}, + {0x3da4, 0x00}, + {0x3da7, 0x50}, + {0x420e, 0x6b}, + {0x420f, 0x6e}, + {0x4210, 0x06}, + {0x4211, 0xc1}, + {0x421e, 0x02}, + {0x421f, 0x45}, + {0x4220, 0xe1}, + {0x4221, 0x01}, + {0x4301, 0xff}, + {0x4307, 0x03}, + {0x4308, 0x13}, + {0x430a, 0x13}, + {0x430d, 0x93}, + {0x430f, 0x57}, + {0x4310, 0x95}, + {0x4311, 0x16}, + {0x4316, 0x00}, + {0x4317, 0x08}, + {0x4319, 0x03}, + {0x431a, 0x00}, + {0x431b, 0x00}, + {0x431d, 0x2a}, + {0x431e, 0x11}, + {0x431f, 0x20}, + {0x4320, 0x19}, + {0x4323, 0x80}, + {0x4324, 0x00}, + {0x4503, 0x4e}, + {0x4505, 0x00}, + {0x4509, 0x00}, + {0x450a, 0x00}, + {0x4580, 0xf8}, + {0x4583, 0x07}, + {0x4584, 0x6a}, + {0x4585, 0x08}, + {0x4586, 0x05}, + {0x4587, 0x04}, + {0x4588, 0x73}, + {0x4589, 0x05}, + {0x458a, 0x1f}, + {0x458b, 0x02}, + {0x458c, 0xdc}, + {0x458d, 0x03}, + {0x458e, 0x02}, + {0x4597, 0x07}, + {0x4598, 0x40}, + {0x4599, 0x0e}, + {0x459a, 0x0e}, + {0x459b, 0xf5}, + {0x459c, 0xf1}, + {0x4602, 0x00}, + {0x4603, 0x13}, + {0x4604, 0x00}, + {0x4609, 0x60}, + {0x460a, 0x30}, + {0x4610, 0x00}, + {0x4611, 0x40}, + {0x4612, 0x01}, + {0x4613, 0x00}, + {0x4614, 0x00}, + {0x4615, 0x40}, + {0x4616, 0x01}, + {0x4617, 0x00}, + {0x4800, 0x04}, + {0x480a, 0x22}, + {0x4813, 0xe4}, + {0x4814, 0x2a}, + {0x4837, 0x1a}, + {0x484b, 0x47}, + {0x484f, 0x00}, + {0x4887, 0x51}, + {0x4d00, 0x4a}, + {0x4d01, 0x18}, + {0x4d05, 0xff}, + {0x4d06, 0x88}, + {0x4d08, 0x63}, + {0x4d09, 0xdf}, + {0x4d15, 0x7d}, + {0x4d1a, 0x20}, + {0x4d30, 0x0a}, + {0x4d31, 0x00}, + {0x4d34, 0x7d}, + {0x4d3c, 0x7d}, + {0x4f00, 0x3f}, + {0x4f01, 0xff}, + {0x4f02, 0xff}, + {0x4f03, 0x2c}, + {0x4f04, 0xe0}, + {0x6a00, 0x00}, + {0x6a01, 0x20}, + {0x6a02, 0x00}, + {0x6a03, 0x20}, + {0x6a04, 0x02}, + {0x6a05, 0x80}, + {0x6a06, 0x01}, + {0x6a07, 0xe0}, + {0x6a08, 0xcf}, + {0x6a09, 0x01}, + {0x6a0a, 0x40}, + {0x6a20, 0x00}, + {0x6a21, 0x02}, + {0x6a22, 0x00}, + {0x6a23, 0x00}, + {0x6a24, 0x00}, + {0x6a25, 0x00}, + {0x6a26, 0x00}, + {0x6a27, 0x00}, + {0x6a28, 0x00}, + {0x5000, 0x8f}, + {0x5001, 0x75}, + {0x5002, 0x7f}, + {0x5003, 0x7a}, + {0x5004, 0x3e}, + {0x5005, 0x1e}, + {0x5006, 0x1e}, + {0x5007, 0x1e}, + {0x5008, 0x00}, + {0x500c, 0x00}, + {0x502c, 0x00}, + {0x502e, 0x00}, + {0x502f, 0x00}, + {0x504b, 0x00}, + {0x5053, 0x00}, + {0x505b, 0x00}, + {0x5063, 0x00}, + {0x5070, 0x00}, + {0x5074, 0x04}, + {0x507a, 0x04}, + {0x507b, 0x09}, + {0x5500, 0x02}, + {0x5700, 0x02}, + {0x5900, 0x02}, + {0x6007, 0x04}, + {0x6008, 0x05}, + {0x6009, 0x02}, + {0x600b, 0x08}, + {0x600c, 0x07}, + {0x600d, 0x88}, + {0x6016, 0x00}, + {0x6027, 0x04}, + {0x6028, 0x05}, + {0x6029, 0x02}, + {0x602b, 0x08}, + {0x602c, 0x07}, + {0x602d, 0x88}, + {0x6047, 0x04}, + {0x6048, 0x05}, + {0x6049, 0x02}, + {0x604b, 0x08}, + {0x604c, 0x07}, + {0x604d, 0x88}, + {0x6067, 0x04}, + {0x6068, 0x05}, + {0x6069, 0x02}, + {0x606b, 0x08}, + {0x606c, 0x07}, + {0x606d, 0x88}, + {0x6087, 0x04}, + {0x6088, 0x05}, + {0x6089, 0x02}, + {0x608b, 0x08}, + {0x608c, 0x07}, + {0x608d, 0x88}, + {0x5e00, 0x00}, + {0x5e01, 0x08}, + {0x5e02, 0x09}, + {0x5e03, 0x0a}, + {0x5e04, 0x0b}, + {0x5e05, 0x0c}, + {0x5e06, 0x0c}, + {0x5e07, 0x0c}, + {0x5e08, 0x0c}, + {0x5e09, 0x0c}, + {0x5e0a, 0x0d}, + {0x5e0b, 0x0d}, + {0x5e0c, 0x0d}, + {0x5e0d, 0x0d}, + {0x5e0e, 0x0d}, + {0x5e0f, 0x0d}, + {0x5e10, 0x0d}, + {0x5e11, 0x0d}, + {0x5e12, 0x0e}, + {0x5e13, 0x0e}, + {0x5e14, 0x0e}, + {0x5e15, 0x0e}, + {0x5e16, 0x0e}, + {0x5e17, 0x0e}, + {0x5e18, 0x0e}, + {0x5e19, 0x10}, + {0x5e1a, 0x11}, + {0x5e1b, 0x11}, + {0x5e1c, 0x12}, + {0x5e1d, 0x12}, + {0x5e1e, 0x14}, + {0x5e1f, 0x15}, + {0x5e20, 0x17}, + {0x5e21, 0x17}, + {0x5e22, 0x00}, + {0x5e23, 0x01}, + {0x5e26, 0x00}, + {0x5e27, 0x3f}, + {0x5e29, 0x00}, + {0x5e2a, 0x40}, + {0x5e2c, 0x00}, + {0x5e2d, 0x40}, + {0x5e2f, 0x00}, + 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{0x5b45, 0xfc}, + {0x5b46, 0x0f}, + {0x5b47, 0xf0}, + {0x5b48, 0x01}, + {0x5b49, 0x02}, + {0x5b4a, 0x00}, + {0x5b4b, 0x0e}, + {0x5b4c, 0x0f}, + {0x5b4d, 0xf1}, + {0x5b4e, 0x0f}, + {0x5b4f, 0xe4}, + {0x5b50, 0x01}, + {0x5b51, 0x2b}, + {0x5b52, 0x01}, + {0x5b53, 0x0f}, + {0x5b54, 0x0f}, + {0x5b55, 0xf1}, + {0x5b56, 0x00}, + {0x5b57, 0x00}, + {0x5b58, 0x0f}, + {0x5b59, 0xeb}, + {0x5b5a, 0x01}, + {0x5b5b, 0x04}, + {0x5b5c, 0x00}, + {0x5b5d, 0x11}, + {0x5b5e, 0x0f}, + {0x5b5f, 0xc8}, + {0x5b60, 0x0f}, + {0x5b61, 0xbd}, + {0x5b62, 0x01}, + {0x5b63, 0x7b}, + {0x5b64, 0x01}, + {0x5b65, 0x11}, + {0x5b66, 0x0f}, + {0x5b67, 0xf4}, + {0x5b68, 0x0f}, + {0x5b69, 0xfb}, + {0x5b6a, 0x0f}, + {0x5b6b, 0xf2}, + {0x5b6c, 0x01}, + {0x5b6d, 0x04}, + {0x5b6e, 0x00}, + {0x5b6f, 0x0a}, + {0x5b70, 0x0f}, + {0x5b71, 0xea}, + {0x5b72, 0x0f}, + {0x5b73, 0xc7}, + {0x5b74, 0x01}, + {0x5b75, 0x4e}, + {0x5b78, 0x00}, + {0x5b79, 0x4c}, + {0x5b7a, 0x00}, + {0x5b7b, 0xb9}, + {0x5b7c, 0x01}, + {0x5b7d, 0x38}, + {0x5b7e, 0x01}, + {0x5280, 0x05}, + {0x5281, 0xf2}, + {0x5282, 0x04}, + {0x5283, 0x00}, + {0x5284, 0x04}, + {0x5285, 0x00}, + {0x5286, 0x07}, + {0x5287, 0x3f}, + {0x4221, 0x13}, + {0x3501, 0x01}, + {0x3502, 0xc8}, + {0x3541, 0x01}, + {0x3542, 0xc8}, + {0x35c1, 0x00}, + {0x35c2, 0x00}, + {0x35c8, 0x01}, + {0x420e, 0x66}, + {0x420f, 0x5d}, + {0x4210, 0xa8}, + {0x4211, 0x55}, + {0x507a, 0x5f}, + {0x507b, 0x46}, + {0x4f00, 0x00}, + {0x4f01, 0x01}, + {0x4f02, 0x80}, + {0x4f03, 0x2c}, + {0x4f04, 0xf8}, + + {I2C_REG_NULL, 0x00}, +}; + +/* + * hdr_operating_mode: OX03C10_HDR3_DCG_VS_12BIT + */ +static const struct i2c_regval ox03c10_1920x1080_30fps_HDR3_DCG_VS_PWL12_mipi600[] = { + {0x0103, 0x01}, + {0x0107, 0x01}, + {I2C_REG_DELAY, 6}, + {0x4d5a, 0x1c}, + {0x4d09, 0xff}, + {0x4d09, 0xdf}, + {0x3208, 0x04}, + {0x4620, 0x04}, + {0x3208, 0x14}, + {0x3208, 0x05}, + {0x4620, 0x04}, + {0x3208, 0x15}, + {0x3208, 0x02}, + {0x3507, 0x00}, + {0x3208, 0x12}, + {0x3208, 0xa2}, + {0x0301, 0xc8}, + {0x0303, 0x01}, + {0x0304, 0x01}, + {0x0305, 0x2c}, + {0x0306, 0x04}, + {0x0307, 0x03}, + {0x0316, 0x00}, + {0x0317, 0x00}, + {0x0318, 0x00}, + {0x0323, 0x05}, + {0x0324, 0x01}, + {0x0325, 0x2c}, + {0x032e, 0x00}, + {0x032a, 0x04}, + {0x0326, 0x09}, + {0x0327, 0x04}, + {0x0331, 0x04}, + {0x0400, 0xe0}, + {0x0401, 0x80}, + {0x0403, 0xde}, + {0x0404, 0x34}, + {0x0405, 0x3b}, + {0x0406, 0xd4}, + {0x0407, 0x08}, + {0x0408, 0xe0}, + {0x0409, 0x62}, + {0x040a, 0xde}, + {0x040b, 0x34}, + {0x040c, 0x8f}, + {0x040d, 0x9b}, + {0x040e, 0x08}, + {0x2803, 0xfe}, + {0x280b, 0x00}, + {0x280c, 0x79}, + {0x3001, 0x03}, + {0x3002, 0xf8}, + {0x3005, 0x80}, + {0x3007, 0x01}, + {0x3008, 0x80}, + {0x3012, 0x41}, + {0x3020, 0x05}, + {0x3700, 0x28}, + {0x3701, 0x15}, + {0x3702, 0x19}, + {0x3703, 0x23}, + {0x3704, 0x0a}, + {0x3705, 0x00}, + {0x3706, 0x3e}, + {0x3707, 0x0d}, + {0x3708, 0x50}, + {0x3709, 0x5a}, + {0x370a, 0x00}, + {0x370b, 0x96}, + {0x3711, 0x11}, + {0x3712, 0x13}, + {0x3717, 0x02}, + {0x3718, 0x73}, + {0x372c, 0x40}, + {0x3733, 0x01}, + {0x3738, 0x36}, + {0x3739, 0x36}, + {0x373a, 0x25}, + {0x373b, 0x25}, + {0x373f, 0x21}, + {0x3740, 0x21}, + {0x3741, 0x21}, + {0x3742, 0x21}, + {0x3747, 0x28}, + {0x3748, 0x28}, + {0x3749, 0x19}, + {0x3755, 0x1a}, + {0x3756, 0x0a}, + {0x3757, 0x1c}, + {0x3765, 0x19}, + {0x3766, 0x05}, + {0x3767, 0x05}, + {0x3768, 0x13}, + {0x376c, 0x07}, + {0x3778, 0x20}, + {0x377c, 0xc8}, + {0x3781, 0x02}, + {0x3783, 0x02}, + {0x379c, 0x58}, + {0x379e, 0x00}, + {0x379f, 0x00}, + {0x37a0, 0x00}, + {0x37bc, 0x22}, + {0x37c0, 0x01}, + {0x37c4, 0x3e}, + {0x37c5, 0x3e}, + {0x37c6, 0x2a}, + {0x37c7, 0x28}, + {0x37c8, 0x02}, + {0x37c9, 0x12}, + {0x37cb, 0x29}, + {0x37cd, 0x29}, + {0x37d2, 0x00}, + {0x37d3, 0x73}, + {0x37d6, 0x00}, + {0x37d7, 0x6b}, + {0x37dc, 0x00}, + {0x37df, 0x54}, + {0x37e2, 0x00}, + {0x37e3, 0x00}, + {0x37f8, 0x00}, + {0x37f9, 0x01}, + {0x37fa, 0x00}, + {0x37fb, 0x19}, + {0x3c03, 0x01}, + {0x3c04, 0x01}, + {0x3c06, 0x21}, + {0x3c08, 0x01}, + {0x3c09, 0x01}, + {0x3c0a, 0x01}, + {0x3c0b, 0x21}, + {0x3c13, 0x21}, + {0x3c14, 0x82}, + {0x3c16, 0x13}, + {0x3c21, 0x00}, + {0x3c22, 0xf3}, + {0x3c37, 0x12}, + {0x3c38, 0x31}, + {0x3c3c, 0x00}, + {0x3c3d, 0x03}, + {0x3c44, 0x16}, + {0x3c5c, 0x8a}, + {0x3c5f, 0x03}, + {0x3c61, 0x80}, + {0x3c6f, 0x2b}, + {0x3c70, 0x5f}, + {0x3c71, 0x2c}, + {0x3c72, 0x2c}, + {0x3c73, 0x2c}, + {0x3c76, 0x12}, + {0x3182, 0x12}, + {0x320e, 0x00}, + {0x320f, 0x00}, + {0x3211, 0x61}, + {0x3215, 0xcd}, + {0x3219, 0x08}, + {0x3506, 0x20}, + {0x350a, 0x01}, + {0x350b, 0x00}, + {0x350c, 0x00}, + {0x3586, 0x30}, + {0x358a, 0x01}, + {0x358b, 0x00}, + {0x358c, 0x00}, + {0x3541, 0x00}, + {0x3542, 0x04}, + {0x3546, 0x10}, + {0x3548, 0x04}, + {0x3549, 0x40}, + {0x354a, 0x01}, + {0x354b, 0x00}, + {0x354c, 0x00}, + {0x35c1, 0x00}, + {0x35c2, 0x02}, + {0x35c6, 0x90}, + {0x3600, 0x8f}, + {0x3605, 0x16}, + {0x3609, 0xf0}, + {0x360a, 0x01}, + {0x360e, 0x1d}, + {0x360f, 0x10}, + {0x3610, 0x70}, + {0x3611, 0x3a}, + {0x3612, 0x28}, + {0x361a, 0x29}, + {0x361b, 0x6c}, + {0x361c, 0x0b}, + {0x361d, 0x00}, + {0x361e, 0xfc}, + {0x362a, 0x00}, + {0x364d, 0x0f}, + {0x364e, 0x18}, + {0x364f, 0x12}, + {0x3653, 0x1c}, + {0x3654, 0x00}, + {0x3655, 0x1f}, + {0x3656, 0x1f}, + {0x3657, 0x0c}, + {0x3658, 0x0a}, + {0x3659, 0x14}, + {0x365a, 0x18}, + {0x365b, 0x14}, + {0x365c, 0x10}, + {0x365e, 0x12}, + {0x3674, 0x08}, + {0x3677, 0x3a}, + {0x3678, 0x3a}, + {0x3679, 0x19}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3806, 0x05}, + {0x3807, 0x0b}, + {0x3808, 0x07}, + {0x3809, 0x80}, + {0x380a, 0x04}, + {0x380b, 0x38}, + {0x380c, 0x08}, + {0x380d, 0x8e}, + {0x380e, 0x02}, + {0x380f, 0xae}, + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x68}, + {0x3816, 0x01}, + {0x3817, 0x01}, + {0x381c, 0x18}, + {0x381e, 0x01}, + {0x381f, 0x01}, + {0x3820, 0x00}, + {0x3821, 0x19}, + {0x3832, 0x00}, + {0x3834, 0x00}, + {0x384c, 0x04}, + {0x384d, 0x1a}, + {0x3850, 0x00}, + {0x3851, 0x42}, + {0x3852, 0x00}, + {0x3853, 0x40}, + {0x3858, 0x04}, + {0x388c, 0x04}, + {0x388d, 0x56}, + {0x3b40, 0x05}, + {0x3b41, 0x40}, + {0x3b42, 0x00}, + {0x3b43, 0x90}, + {0x3b44, 0x02}, + {0x3b45, 0x00}, + {0x3b46, 0x02}, + {0x3b47, 0x00}, + {0x3b48, 0x19}, + {0x3b49, 0x12}, + {0x3b4a, 0x16}, + {0x3b4b, 0x2e}, + {0x3b4c, 0x03}, + {0x3b4d, 0x00}, + {0x3b86, 0x00}, + {0x3b87, 0x34}, + {0x3b88, 0x00}, + {0x3b89, 0x08}, + {0x3b8a, 0x05}, + {0x3b8b, 0x00}, + {0x3b8c, 0x07}, + {0x3b8d, 0x80}, + {0x3b8e, 0x00}, + {0x3b8f, 0x00}, + {0x3b92, 0x05}, + {0x3b93, 0x00}, + {0x3b94, 0x07}, + {0x3b95, 0x80}, + {0x3b9e, 0x09}, + {0x3d85, 0x05}, + {0x3d8a, 0x03}, + {0x3d8b, 0xff}, + {0x3d99, 0x00}, + {0x3d9a, 0x9f}, + {0x3d9b, 0x00}, + {0x3d9c, 0xa0}, + {0x3da4, 0x00}, + {0x3da7, 0x50}, + {0x420e, 0x6b}, + {0x420f, 0x6e}, + {0x4210, 0x06}, + {0x4211, 0xc1}, + {0x421e, 0x02}, + {0x421f, 0x45}, + {0x4220, 0xe1}, + {0x4221, 0x01}, + {0x4301, 0x0f}, + {0x4307, 0x03}, + {0x4308, 0x13}, + {0x430a, 0x13}, + {0x430d, 0x93}, + {0x430f, 0x57}, + {0x4310, 0x95}, + {0x4311, 0x16}, + {0x4316, 0x00}, + {0x4317, 0x08}, + {0x4319, 0x01}, + {0x431a, 0x00}, + {0x431b, 0x00}, + {0x431d, 0x2a}, + {0x431e, 0x11}, + {0x431f, 0x20}, + {0x4320, 0x19}, + {0x4323, 0x80}, + {0x4324, 0x00}, + {0x4503, 0x4e}, + {0x4505, 0x00}, + {0x4509, 0x00}, + {0x450a, 0x00}, + {0x4580, 0xf8}, + {0x4583, 0x07}, + {0x4584, 0x6a}, + {0x4585, 0x08}, + {0x4586, 0x05}, + {0x4587, 0x04}, + {0x4588, 0x73}, + {0x4589, 0x05}, + {0x458a, 0x1f}, + {0x458b, 0x02}, + {0x458c, 0xdc}, + {0x458d, 0x03}, + {0x458e, 0x02}, + {0x4597, 0x07}, + {0x4598, 0x40}, + {0x4599, 0x0e}, + {0x459a, 0x0e}, + {0x459b, 0xf5}, + {0x459c, 0xf1}, + {0x4602, 0x00}, + {0x4603, 0x13}, + {0x4604, 0x00}, + {0x4609, 0x60}, + {0x460a, 0x30}, + {0x4610, 0x00}, + {0x4611, 0x40}, + {0x4612, 0x01}, + {0x4613, 0x00}, + {0x4614, 0x00}, + {0x4615, 0x40}, + {0x4616, 0x01}, + {0x4617, 0x00}, + {0x4800, 0x04}, + {0x480a, 0x22}, + {0x4813, 0xe4}, + {0x4814, 0x2a}, + {0x4837, 0x1a}, + {0x484b, 0x47}, + {0x484f, 0x00}, + {0x4887, 0x51}, + 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{0x5c86, 0x05}, + {0x5bb8, 0x01}, + {0x5bb9, 0x01}, + {0x5c38, 0x01}, + {0x5c39, 0x01}, + {0x5cb8, 0x01}, + {0x5cb9, 0x01}, + {0x5bc7, 0x00}, + {0x5bc8, 0x80}, + {0x5c47, 0x00}, + {0x5c48, 0x80}, + {0x5cc7, 0x00}, + {0x5cc8, 0x80}, + {0x5bba, 0x01}, + {0x5bbb, 0x00}, + {0x5c3a, 0x01}, + {0x5c3b, 0x00}, + {0x5cba, 0x01}, + {0x5cbb, 0x00}, + {0x5d74, 0x01}, + {0x5d75, 0x00}, + {0x5d1f, 0x81}, + {0x5d11, 0x00}, + {0x5d12, 0x10}, + {0x5d13, 0x10}, + {0x5d15, 0x05}, + {0x5d16, 0x05}, + {0x5d17, 0x05}, + {0x5d08, 0x03}, + {0x5d09, 0x6b}, + {0x5d0a, 0x03}, + {0x5d0b, 0x6b}, + {0x5d18, 0x03}, + {0x5d19, 0x6b}, + {0x52c6, 0x00}, + {0x52c7, 0x12}, + {0x52c8, 0x04}, + {0x52c9, 0x02}, + {0x52ca, 0x01}, + {0x52cb, 0x01}, + {0x52cc, 0x04}, + {0x52cd, 0x02}, + {0x52ce, 0x01}, + {0x52cf, 0x01}, + {0x52d0, 0x03}, + {0x52d1, 0x08}, + {0x52d2, 0x0c}, + {0x54c6, 0x00}, + {0x54c7, 0x12}, + {0x54c8, 0x04}, + {0x54c9, 0x02}, + {0x54ca, 0x01}, + {0x54cb, 0x01}, + {0x54cc, 0x04}, + {0x54cd, 0x02}, + {0x54ce, 0x01}, + {0x54cf, 0x01}, + {0x54d0, 0x03}, + {0x54d1, 0x08}, + {0x54d2, 0x0c}, + {0x56c6, 0x00}, + {0x56c7, 0x12}, + {0x56c8, 0x04}, + {0x56c9, 0x02}, + {0x56ca, 0x01}, + {0x56cb, 0x01}, + {0x56cc, 0x04}, + {0x56cd, 0x02}, + {0x56ce, 0x01}, + {0x56cf, 0x01}, + {0x56d0, 0x03}, + {0x56d1, 0x08}, + {0x56d2, 0x0c}, + {0x58c6, 0x00}, + {0x58c7, 0x12}, + {0x58c8, 0x04}, + {0x58c9, 0x02}, + {0x58ca, 0x01}, + {0x58cb, 0x01}, + {0x58cc, 0x04}, + {0x58cd, 0x02}, + {0x58ce, 0x01}, + {0x58cf, 0x01}, + {0x58d0, 0x03}, + {0x58d1, 0x08}, + {0x58d2, 0x0c}, + {0x5004, 0x1e}, + {0x610a, 0x07}, + {0x610b, 0x80}, + {0x610c, 0x05}, + {0x610d, 0x00}, + {0x6102, 0x3f}, + {0x5d62, 0x07}, + {0x5d40, 0x02}, + {0x5d41, 0x01}, + {0x5d63, 0x08}, + {0x5d64, 0x01}, + {0x5d65, 0xff}, + {0x5d56, 0x00}, + {0x5d57, 0x20}, + {0x5d58, 0x00}, + {0x5d59, 0x20}, + {0x5d5a, 0x00}, + {0x5d5b, 0x0c}, + {0x5d5c, 0x02}, + {0x5d5d, 0x40}, + {0x5d5e, 0x02}, + {0x5d5f, 0x40}, + {0x5d60, 0x03}, + {0x5d61, 0x40}, + {0x5d4a, 0x02}, + {0x5d4b, 0x40}, + {0x5d4c, 0x02}, + {0x5d4d, 0x40}, + {0x5d4e, 0x02}, + {0x5d4f, 0x40}, + {0x5d50, 0x18}, + {0x5d51, 0x80}, + {0x5d52, 0x18}, + {0x5d53, 0x80}, + {0x5d54, 0x18}, + {0x5d55, 0x80}, + {0x5d46, 0x20}, + {0x5d47, 0x00}, + {0x5d48, 0x22}, + {0x5d49, 0x00}, + {0x5d42, 0x20}, + {0x5d43, 0x00}, + {0x5d44, 0x22}, + {0x5d45, 0x00}, + {0x5b40, 0x01}, + {0x5b41, 0x14}, + {0x5b42, 0x0f}, + {0x5b43, 0xf1}, + {0x5b44, 0x0f}, + {0x5b45, 0xfc}, + {0x5b46, 0x0f}, + {0x5b47, 0xf0}, + {0x5b48, 0x01}, + {0x5b49, 0x02}, + {0x5b4a, 0x00}, + {0x5b4b, 0x0e}, + {0x5b4c, 0x0f}, + {0x5b4d, 0xf1}, + {0x5b4e, 0x0f}, + {0x5b4f, 0xe4}, + {0x5b50, 0x01}, + {0x5b51, 0x2b}, + {0x5b52, 0x01}, + {0x5b53, 0x0f}, + {0x5b54, 0x0f}, + {0x5b55, 0xf1}, + {0x5b56, 0x00}, + {0x5b57, 0x00}, + {0x5b58, 0x0f}, + {0x5b59, 0xeb}, + {0x5b5a, 0x01}, + {0x5b5b, 0x04}, + {0x5b5c, 0x00}, + {0x5b5d, 0x11}, + {0x5b5e, 0x0f}, + {0x5b5f, 0xc8}, + {0x5b60, 0x0f}, + {0x5b61, 0xbd}, + {0x5b62, 0x01}, + {0x5b63, 0x7b}, + {0x5b64, 0x01}, + {0x5b65, 0x11}, + {0x5b66, 0x0f}, + {0x5b67, 0xf4}, + {0x5b68, 0x0f}, + {0x5b69, 0xfb}, + {0x5b6a, 0x0f}, + {0x5b6b, 0xf2}, + {0x5b6c, 0x01}, + {0x5b6d, 0x04}, + {0x5b6e, 0x00}, + {0x5b6f, 0x0a}, + {0x5b70, 0x0f}, + {0x5b71, 0xea}, + {0x5b72, 0x0f}, + {0x5b73, 0xc7}, + {0x5b74, 0x01}, + {0x5b75, 0x4e}, + {0x5b78, 0x00}, + {0x5b79, 0x4c}, + {0x5b7a, 0x00}, + {0x5b7b, 0xb9}, + {0x5b7c, 0x01}, + {0x5b7d, 0x38}, + {0x5b7e, 0x01}, + {0x5280, 0x05}, + {0x5281, 0xf2}, + {0x5282, 0x04}, + {0x5283, 0x00}, + {0x5284, 0x04}, + {0x5285, 0x00}, + {0x5286, 0x07}, + {0x5287, 0x3f}, + {0x4221, 0x13}, + {0x3501, 0x01}, + {0x3502, 0xc8}, + {0x3541, 0x01}, + {0x3542, 0xc8}, + {0x35c1, 0x00}, + {0x35c2, 0x01}, + {0x420e, 0x66}, + {0x420f, 0x5d}, + {0x4210, 0xa8}, + {0x4211, 0x55}, + {0x507a, 0x5f}, + {0x507b, 0x46}, + {0x4f00, 0x00}, + {0x4f01, 0x01}, + {0x4f02, 0x80}, + {0x4f03, 0x2c}, + {0x4f04, 0xf8}, + + {I2C_REG_NULL, 0x00}, +}; + +/* + * hdr_operating_mode: OX03C10_HDR3_DCG_VS_LFM_16BIT + * Note: LFM-bit packed in MIPI RAW 8b format on separate VC (default on MIPI VC1) + */ +static const struct i2c_regval ox03c10_1920x1080_30fps_HDR3_DCG_VS_LFM_PWL16_mipi996[] = { + {0x0103, 0x01}, + {0x0107, 0x01}, + {I2C_REG_DELAY, 6}, + {0x4d5a, 0x1c}, + {0x4d09, 0xff}, + {0x4d09, 0xdf}, + {0x3208, 0x04}, + {0x4620, 0x04}, + {0x3208, 0x14}, + {0x3208, 0x05}, + {0x4620, 0x04}, + {0x3208, 0x15}, + {0x3208, 0x02}, + {0x3507, 0x00}, + {0x3208, 0x12}, + {0x3208, 0xa2}, + {0x0301, 0xc8}, + {0x0303, 0x01}, + {0x0304, 0x01}, + {0x0305, 0x2c}, + {0x0306, 0x04}, + {0x0307, 0x01}, + {0x0316, 0x00}, + {0x0317, 0x00}, + {0x0318, 0x00}, + {0x0323, 0x05}, + {0x0324, 0x01}, + {0x0325, 0x2c}, + {0x0400, 0xe0}, + {0x0401, 0x80}, + {0x0403, 0xde}, + {0x0404, 0x34}, + {0x0405, 0x3b}, + {0x0406, 0xde}, + {0x0407, 0x08}, + {0x0408, 0xe0}, + {0x0409, 0x7f}, + {0x040a, 0xde}, + {0x040b, 0x34}, + {0x040c, 0x47}, + {0x040d, 0xd8}, + {0x040e, 0x08}, + {0x2803, 0xfe}, + {0x280b, 0x00}, + {0x280c, 0x79}, + {0x3001, 0x03}, + {0x3002, 0xf8}, + {0x3005, 0x80}, + {0x3007, 0x01}, + {0x3008, 0x80}, + {0x3012, 0x41}, + {0x3020, 0x05}, + {0x3700, 0x28}, + {0x3701, 0x15}, + {0x3702, 0x19}, + {0x3703, 0x23}, + {0x3704, 0x0a}, + {0x3705, 0x00}, + {0x3706, 0x3e}, + {0x3707, 0x0d}, + {0x3708, 0x50}, + {0x3709, 0x5a}, + {0x370a, 0x00}, + {0x370b, 0x96}, + {0x3711, 0x11}, + {0x3712, 0x13}, + {0x3717, 0x02}, + {0x3718, 0x73}, + {0x372c, 0x40}, + {0x3733, 0x01}, + {0x3738, 0x36}, + {0x3739, 0x36}, + {0x373a, 0x25}, + {0x373b, 0x25}, + {0x373f, 0x21}, + {0x3740, 0x21}, + {0x3741, 0x21}, + {0x3742, 0x21}, + {0x3747, 0x28}, + {0x3748, 0x28}, + {0x3749, 0x19}, + {0x3755, 0x1a}, + {0x3756, 0x0a}, + {0x3757, 0x1c}, + {0x3765, 0x19}, + {0x3766, 0x05}, + {0x3767, 0x05}, + {0x3768, 0x13}, + {0x376c, 0x07}, + {0x3778, 0x20}, + {0x377c, 0xc8}, + {0x3781, 0x02}, + {0x3783, 0x02}, + {0x379c, 0x58}, + {0x379e, 0x00}, + {0x379f, 0x00}, + {0x37a0, 0x00}, + {0x37bc, 0x22}, + {0x37c0, 0x01}, + {0x37c4, 0x3e}, + {0x37c5, 0x3e}, + {0x37c6, 0x2a}, + {0x37c7, 0x28}, + {0x37c8, 0x02}, + {0x37c9, 0x12}, + {0x37cb, 0x29}, + {0x37cd, 0x29}, + {0x37d2, 0x00}, + {0x37d3, 0x73}, + {0x37d6, 0x00}, + {0x37d7, 0x6b}, + {0x37dc, 0x00}, + {0x37df, 0x54}, + {0x37e2, 0x00}, + {0x37e3, 0x00}, + {0x37f8, 0x00}, + {0x37f9, 0x01}, + {0x37fa, 0x00}, + {0x37fb, 0x19}, + {0x3c03, 0x01}, + {0x3c04, 0x01}, + {0x3c06, 0x21}, + {0x3c08, 0x01}, + {0x3c09, 0x01}, + {0x3c0a, 0x01}, + {0x3c0b, 0x21}, + {0x3c13, 0x21}, + {0x3c14, 0x82}, + {0x3c16, 0x13}, + {0x3c21, 0x00}, + {0x3c22, 0xf3}, + {0x3c37, 0x12}, + {0x3c38, 0x31}, + {0x3c3c, 0x00}, + {0x3c3d, 0x03}, + {0x3c44, 0x16}, + {0x3c5c, 0x8a}, + {0x3c5f, 0x03}, + {0x3c61, 0x80}, + {0x3c6f, 0x2b}, + {0x3c70, 0x5f}, + {0x3c71, 0x2c}, + {0x3c72, 0x2c}, + {0x3c73, 0x2c}, + {0x3c76, 0x12}, + {0x3182, 0x12}, + {0x320e, 0x00}, + {0x320f, 0x00}, + {0x3211, 0x61}, + {0x3215, 0xcd}, + {0x3219, 0x08}, + {0x3506, 0x30}, + {0x350a, 0x01}, + {0x350b, 0x00}, + {0x350c, 0x00}, + {0x3586, 0x60}, + {0x358a, 0x01}, + {0x358b, 0x00}, + {0x358c, 0x00}, + {0x3541, 0x00}, + {0x3542, 0x04}, + {0x3548, 0x04}, + {0x3549, 0x40}, + {0x354a, 0x01}, + {0x354b, 0x00}, + {0x354c, 0x00}, + {0x35c1, 0x00}, + {0x35c2, 0x02}, + {0x35c6, 0xa0}, + {0x3600, 0x8f}, + {0x3605, 0x16}, + {0x3609, 0xf0}, + {0x360a, 0x01}, + {0x360e, 0x1d}, + {0x360f, 0x10}, + {0x3610, 0x70}, + {0x3611, 0x3a}, + {0x3612, 0x28}, + {0x361a, 0x29}, + {0x361b, 0x6c}, + {0x361c, 0x0b}, + {0x361d, 0x00}, + {0x361e, 0xfc}, + {0x362a, 0x00}, + {0x364d, 0x0f}, + {0x364e, 0x18}, + {0x364f, 0x12}, + {0x3653, 0x1c}, + {0x3654, 0x00}, + {0x3655, 0x1f}, + {0x3656, 0x1f}, + {0x3657, 0x0c}, + {0x3658, 0x0a}, + {0x3659, 0x14}, + {0x365a, 0x18}, + {0x365b, 0x14}, + {0x365c, 0x10}, + {0x365e, 0x12}, + {0x3674, 0x08}, + {0x3677, 0x3a}, + {0x3678, 0x3a}, + {0x3679, 0x19}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3806, 0x05}, + {0x3807, 0x0b}, + {0x3808, 0x07}, + {0x3809, 0x80}, + {0x380a, 0x05}, + {0x380b, 0x00}, + {0x380c, 0x04}, + {0x380d, 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0x03}, + {0x5cad, 0x08}, + {0x5cae, 0x01}, + {0x5caf, 0x00}, + {0x5cb0, 0x02}, + {0x5cb1, 0x00}, + {0x5cb2, 0x03}, + {0x5cb3, 0x08}, + {0x5be7, 0x80}, + {0x5bc9, 0x80}, + {0x5bca, 0x80}, + {0x5bcb, 0x80}, + {0x5bcc, 0x80}, + {0x5bcd, 0x80}, + {0x5bce, 0x80}, + {0x5bcf, 0x80}, + {0x5bd0, 0x80}, + {0x5bd1, 0x80}, + {0x5bd2, 0x20}, + {0x5bd3, 0x80}, + {0x5bd4, 0x40}, + {0x5bd5, 0x20}, + {0x5bd6, 0x00}, + {0x5bd7, 0x00}, + {0x5bd8, 0x00}, + {0x5bd9, 0x00}, + {0x5bda, 0x00}, + {0x5bdb, 0x00}, + {0x5bdc, 0x00}, + {0x5bdd, 0x00}, + {0x5bde, 0x00}, + {0x5bdf, 0x00}, + {0x5be0, 0x00}, + {0x5be1, 0x00}, + {0x5be2, 0x00}, + {0x5be3, 0x00}, + {0x5be4, 0x00}, + {0x5be5, 0x00}, + {0x5be6, 0x00}, + {0x5c49, 0x80}, + {0x5c4a, 0x80}, + {0x5c4b, 0x80}, + {0x5c4c, 0x80}, + {0x5c4d, 0x40}, + {0x5c4e, 0x80}, + {0x5c4f, 0x80}, + {0x5c50, 0x80}, + {0x5c51, 0x60}, + {0x5c52, 0x20}, + {0x5c53, 0x80}, + {0x5c54, 0x80}, + {0x5c55, 0x80}, + {0x5c56, 0x20}, + {0x5c57, 0x00}, + {0x5c58, 0x80}, + {0x5c59, 0x40}, + {0x5c5a, 0x20}, + {0x5c5b, 0x00}, + {0x5c5c, 0x00}, + {0x5c5d, 0x80}, + {0x5c5e, 0x00}, + {0x5c5f, 0x00}, + {0x5c60, 0x00}, + {0x5c61, 0x00}, + {0x5c62, 0x00}, + {0x5c63, 0x00}, + {0x5c64, 0x00}, + {0x5c65, 0x00}, + {0x5c66, 0x00}, + {0x5cc9, 0x80}, + {0x5cca, 0x80}, + {0x5ccb, 0x80}, + {0x5ccc, 0x80}, + {0x5ccd, 0x80}, + {0x5cce, 0x80}, + {0x5ccf, 0x80}, + {0x5cd0, 0x80}, + {0x5cd1, 0x80}, + {0x5cd2, 0x60}, + {0x5cd3, 0x80}, + {0x5cd4, 0x80}, + {0x5cd5, 0x80}, + {0x5cd6, 0x60}, + {0x5cd7, 0x40}, + {0x5cd8, 0x80}, + {0x5cd9, 0x80}, + {0x5cda, 0x80}, + {0x5cdb, 0x40}, + {0x5cdc, 0x20}, + {0x5cdd, 0x80}, + {0x5cde, 0x80}, + {0x5cdf, 0x80}, + {0x5ce0, 0x20}, + {0x5ce1, 0x00}, + {0x5ce2, 0x80}, + {0x5ce3, 0x80}, + {0x5ce4, 0x80}, + {0x5ce5, 0x00}, + {0x5ce6, 0x00}, + {0x5d74, 0x01}, + {0x5d75, 0x00}, + {0x5d1f, 0x81}, + {0x5d11, 0x00}, + {0x5d12, 0x10}, + {0x5d13, 0x10}, + {0x5d15, 0x05}, + {0x5d16, 0x05}, + {0x5d17, 0x05}, + {0x5d08, 0x03}, + {0x5d09, 0xb6}, + {0x5d0a, 0x03}, + {0x5d0b, 0xb6}, + {0x5d18, 0x03}, + {0x5d19, 0xb6}, + {0x5d62, 0x01}, + {0x5d40, 0x02}, + {0x5d41, 0x01}, + {0x5d63, 0x1f}, + {0x5d64, 0x00}, + {0x5d65, 0x80}, + {0x5d56, 0x00}, + {0x5d57, 0x20}, + {0x5d58, 0x00}, + {0x5d59, 0x20}, + {0x5d5a, 0x00}, + {0x5d5b, 0x0c}, + {0x5d5c, 0x02}, + {0x5d5d, 0x40}, + {0x5d5e, 0x02}, + {0x5d5f, 0x40}, + {0x5d60, 0x03}, + {0x5d61, 0x40}, + {0x5d4a, 0x02}, + {0x5d4b, 0x40}, + {0x5d4c, 0x02}, + {0x5d4d, 0x40}, + {0x5d4e, 0x02}, + {0x5d4f, 0x40}, + {0x5d50, 0x18}, + {0x5d51, 0x80}, + {0x5d52, 0x18}, + {0x5d53, 0x80}, + {0x5d54, 0x18}, + {0x5d55, 0x80}, + {0x5d46, 0x20}, + {0x5d47, 0x00}, + {0x5d48, 0x22}, + {0x5d49, 0x00}, + {0x5d42, 0x20}, + {0x5d43, 0x00}, + {0x5d44, 0x22}, + {0x5d45, 0x00}, + {0x5004, 0x1e}, + {0x4221, 0x03}, + {0x380e, 0x02}, + {0x380f, 0xae}, + {0x380c, 0x04}, + {0x380d, 0x47}, + {0x384c, 0x02}, + {0x384d, 0x0d}, + {0x388c, 0x02}, + {0x388d, 0x2b}, + {0x420e, 0x54}, + {0x420f, 0xa0}, + {0x4210, 0xca}, + {0x4211, 0xf2}, + {0x507a, 0x5f}, + {0x507b, 0x46}, + {0x3802, 0x00}, + {0x3803, 0x68}, + {0x3806, 0x04}, + {0x3807, 0xa7}, + {0x380a, 0x04}, + {0x380b, 0x38}, + {0x3812, 0x00}, + {0x3813, 0x04}, + {0x380c, 0x08}, + {0x380d, 0x8e}, + {0x384c, 0x04}, + {0x384d, 0x1a}, + {0x388c, 0x04}, + {0x388d, 0x56}, + {0x0304, 0x00}, + {0x0305, 0xf9}, + {0x4837, 0x10}, + {0x0408, 0x78}, + {0x0409, 0x00}, + {0x040a, 0xd1}, + {0x040b, 0x1e}, + {0x040c, 0x2e}, + {0x040d, 0x44}, + {0x040e, 0x0c}, + + {I2C_REG_NULL, 0x00}, +}; + +// Switch to linear bypass mode: LCG RAW10 +static const struct i2c_regval ox03c10_switch_linear_lcg_raw10[] = { + {0x4221, 0x05}, + {0x5002, 0x3f}, // PWL 1 & 0 disable, Re-timing enable, Statistic block 4/3/2/1/0 enable + {0x5003, 0x2a}, // Combine enable, Combine sync buffer enable, HDR sync buffer enable + {0x502c, 0x0f}, // Manual set V/S/M/L channel exposure index enable + {0x504b, 0x04}, // Manual exposure index for L channel + {0x5053, 0x03}, // Manual exposure index for M channel + {0x505b, 0x02}, // Manual exposure index for S channel + {0x5063, 0x01}, // Manual exposure index for V channel + {0x5074, 0x59}, // Manual combine out option: Non-combine out + // Manual select exposure out when in non-combine out mode: 1 + // 0x49: HCG, 0x59: LCG, 0x69: SPD, 0x79: VS + // Manual exposure mode: enable & 2 exposure combine + {0x4319, 0x43}, // Force VFIFO/MIPI bitwidth for other group1, Use SPD in combine, Enable DCG combine + {0x431a, 0x01}, // mipi_bitw_man0: 10bit + + {I2C_REG_NULL, 0x00}, +}; + +static struct rkmodule_hdr_compr ox03c10_hdr_compr_12 = { + .point = 30, + .src_bit = 20, + .k_shift = 7, + .data_src = {0, 256, 768, 1792, 3840, 7936, 12032, 16128, 20224, 24320, + 32512, 40704, 48896, 57088, 65280, 73472, 81664, 89856, 106240, 122624, + 139008, 155392, 171776, 188160, 204544, 270080, 401152, 532224, 794368, 1056512}, + .data_compr = {0, 256, 320, 384, 448, 512, 576, 640, 704, 768, + 832, 928, 1024, 1120, 1216, 1312, 1408, 1504, 1632, 1760, + 1888, 2016, 2144, 2272, 2400, 2688, 3152, 3456, 3840, 4096}, + .slope_k = {128, 1024, 2048, 4096, 8192, 8192, 8192, 8192, 8192, 16384, + 10922, 10922, 10922, 10922, 10922, 10922, 10922, 16384, 16384, 16384, + 16384, 16384, 16384, 16384, 29127, 36157, 55188, 87381, 131072, 0}, +}; + +static struct rkmodule_hdr_compr ox03c10_hdr_compr_16 = { + .point = 30, + .src_bit = 20, + .k_shift = 12, + .data_src = {0, 2048, 2048, 2048, 2048, 4096, 8192, 12288, 16384, 20480, + 24576, 32768, 40960, 49152, 57344, 65536, 73728, 81920, 98304, 114688, + 131072, 147456, 163840, 180224, 196608, 262144, 393216, 524288, 786432, 1048576}, + .data_compr = {0, 2048, 2048, 2048, 2048, 3071, 4095, 5119, 6143, 7167, + 8191, 9727, 11263, 12799, 14335, 15871, 17407, 18943, 20991, 23039, + 25087, 27135, 29183, 31231, 33279, 38911, 47103, 53247, 59391, 65534}, + .slope_k = {4096, 0, 0, 0, 8200, 16384, 16384, 16384, 16384, 16384, + 21845, 21845, 21845, 21845, 21845, 21845, 21845, 32768, 32768, 32768, + 32768, 32768, 32768, 32768, 47662, 65536, 87381, 174762, 174762, 0}, +}; + +/* + * The width and height must be configured to be + * the same as the current output resolution of the sensor. + * The input width of the isp needs to be 16 aligned. + * The input height of the isp needs to be 8 aligned. + * If the width or height does not meet the alignment rules, + * you can configure the cropping parameters with the following function to + * crop out the appropriate resolution. + * struct v4l2_subdev_pad_ops { + * .get_selection + * } + */ +static const struct ox03c10_mode supported_modes[] = { + { /* NO_HDR: RAW10 */ + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0200, + .hts_def = 0x10FE, + .vts_def = 0x02AE * 2, + .exp_mode = EXP_NORMAL, + .bpp = 10, + .link_freq_idx = 0, + .hdr_mode = NO_HDR, + .hdr_compr = NULL, + .reg_list = ox03c10_1920x1080_30fps_HDR3_DCG_VS_PWL12_mipi600, + .linear_reg_list = ox03c10_switch_linear_lcg_raw10, +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + .vc[PAD0] = 0, +#else + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, +#endif /* LINUX_VERSION_CODE */ + }, + { /* HDR_COMPR: OX03C10_HDR3_DCG_VS_12BIT */ + .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12, + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0200, + .hts_def = 0x10FE, + .vts_def = 0x02AE * 2, + .exp_mode = EXP_HDR3_DCG_VS, + .bpp = 12, + .link_freq_idx = 0, + .hdr_mode = HDR_COMPR, + .hdr_compr = &ox03c10_hdr_compr_12, + .hdr_operating_mode = OX03C10_HDR3_DCG_VS_12BIT, + .reg_list = ox03c10_1920x1080_30fps_HDR3_DCG_VS_PWL12_mipi600, +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + .vc[PAD0] = 0, +#else + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, +#endif /* LINUX_VERSION_CODE */ + }, + { /* HDR_COMPR: OX03C10_HDR3_DCG_SPD_12BIT */ + .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12, + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0200, + .hts_def = 0x10FE, + .vts_def = 0x02AE * 2, + .exp_mode = EXP_HDR3_DCG_SPD, + .bpp = 12, + .link_freq_idx = 0, + .hdr_mode = HDR_COMPR, + .hdr_compr = &ox03c10_hdr_compr_12, + .hdr_operating_mode = OX03C10_HDR3_DCG_SPD_12BIT, + .reg_list = ox03c10_1920x1080_30fps_HDR3_DCG_SPD_PWL12_mipi600, +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + .vc[PAD0] = 0, +#else + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, +#endif /* LINUX_VERSION_CODE */ + }, + { /* HDR_COMPR: OX03C10_HDR3_DCG_VS_LFM_16BIT */ + .bus_fmt = MEDIA_BUS_FMT_SBGGR16_1X16, + .width = 1920, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0038, + .hts_def = 0x10FE, + .vts_def = 0x02AE * 2, + .exp_mode = EXP_HDR3_DCG_VS, + .bpp = 16, + .link_freq_idx = 1, + .hdr_mode = HDR_COMPR, + .hdr_compr = &ox03c10_hdr_compr_16, + .hdr_operating_mode = OX03C10_HDR3_DCG_VS_LFM_16BIT, + .reg_list = ox03c10_1920x1080_30fps_HDR3_DCG_VS_LFM_PWL16_mipi996, +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + .vc[PAD0] = 0, +#else + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, +#endif /* LINUX_VERSION_CODE */ + }, +}; + +static const s64 link_freq_menu_items[] = { + OX03C10_LINK_FREQ_300MHZ, + OX03C10_LINK_FREQ_480MHZ, +}; + +static const char * const ox03c10_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +/* Write registers up to 4 at a time */ +static int __maybe_unused ox03c10_i2c_write_reg(struct i2c_client *client, + u16 reg_addr, u32 val_len, u32 reg_val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + dev_info(&client->dev, "i2c addr(0x%02x) write: 0x%04x = 0x%08x (%d)\n", + client->addr, reg_addr, reg_val, val_len); + + if (val_len > 4) + return -EINVAL; + + buf[0] = reg_addr >> 8; + buf[1] = reg_addr & 0xff; + buf_i = 2; + + val_be = cpu_to_be32(reg_val); + val_p = (u8 *)&val_be; + val_i = 4 - val_len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, (val_len + 2)) != (val_len + 2)) { + dev_err(&client->dev, + "%s: writing register 0x%04x from 0x%02x failed\n", + __func__, reg_addr, client->addr); + return -EIO; + } + + return 0; +} + +/* Read registers up to 4 at a time */ +static int __maybe_unused ox03c10_i2c_read_reg(struct i2c_client *client, + u16 reg_addr, u32 val_len, u32 *reg_val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg_addr); + u8 *reg_be_p; + int ret; + + if (val_len > 4 || !val_len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + reg_be_p = (u8 *)®_addr_be; + + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = reg_be_p; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = val_len; + msgs[1].buf = &data_be_p[4 - val_len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, + "%s: reading register 0x%04x from 0x%02x failed\n", + __func__, reg_addr, client->addr); + return -EIO; + } + + *reg_val = be32_to_cpu(data_be); + +#if 0 + dev_info(&client->dev, "i2c addr(0x%02x) read: 0x%04x = 0x%08x (%d)\n", + client->addr, reg_addr, *reg_val, val_len); +#endif + + return 0; +} + +static int __maybe_unused ox03c10_i2c_write_array(struct i2c_client *client, + const struct i2c_regval *regs) +{ + u32 i = 0, delay_us = 0; + int ret = 0; + + for (i = 0; (ret == 0) && (regs[i].reg_addr != I2C_REG_NULL); i++) { + if (regs[i].reg_addr != I2C_REG_DELAY) { + ret = ox03c10_i2c_write_reg(client, regs[i].reg_addr, + OX03C10_REG_VALUE_08BIT, regs[i].reg_val); + } else { + if (regs[i].reg_val != 0) { + dev_info(&client->dev, "delay %d ms\n", regs[i].reg_val); + + delay_us = regs[i].reg_val * 1000; + usleep_range(delay_us, delay_us + 100); + } + } + } + + return ret; +} + +static const struct ox03c10_mode *ox03c10_find_mode(int hdr_mode, int hdr_operating_mode) +{ + unsigned int i = 0, cur_best_fit = 0; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (supported_modes[i].hdr_mode == hdr_mode) { + if (hdr_mode == NO_HDR) { // NO_HDR Mode + cur_best_fit = i; + break; + } else { // HDR_COMPR Mode + if (supported_modes[i].hdr_operating_mode == hdr_operating_mode) { + cur_best_fit = i; + break; + } + } + } + } + + return &supported_modes[cur_best_fit]; +} + +static int __ox03c10_power_on(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + int ret = 0; + + dev_info(dev, "ox03c10 device power on\n"); + + ret = regulator_enable(ox03c10->poc_regulator); + if (ret < 0) { + dev_err(dev, "Unable to turn PoC regulator on\n"); + return ret; + } + + return 0; +} + +static void __ox03c10_power_off(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + int ret = 0; + + dev_info(dev, "ox03c10 device power off\n"); + + ret = regulator_disable(ox03c10->poc_regulator); + if (ret < 0) + dev_warn(dev, "Unable to turn PoC regulator off\n"); +} + +static int ox03c10_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = __ox03c10_power_on(ox03c10); + + return ret; +} + +static int ox03c10_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + __ox03c10_power_off(ox03c10); + + return 0; +} + +static const struct dev_pm_ops ox03c10_pm_ops = { + SET_RUNTIME_PM_OPS( + ox03c10_runtime_suspend, ox03c10_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int ox03c10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->state, 0); +#else + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); +#endif + const struct ox03c10_mode *def_mode = &ox03c10->supported_modes[0]; + + mutex_lock(&ox03c10->mutex); + + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&ox03c10->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int ox03c10_s_power(struct v4l2_subdev *sd, int on) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + struct i2c_client *client = ox03c10->client; + int ret = 0; + + mutex_lock(&ox03c10->mutex); + + /* If the power state is not modified - no work to do. */ + if (ox03c10->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ox03c10->power_on = true; + } else { + pm_runtime_put(&client->dev); + ox03c10->power_on = false; + } + +unlock_and_return: + mutex_unlock(&ox03c10->mutex); + + return ret; +} + +static void ox03c10_get_module_inf(struct ox03c10 *ox03c10, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, OX03C10_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, ox03c10->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, ox03c10->len_name, sizeof(inf->base.lens)); +} + +static int ox03c10_set_hdrae(struct ox03c10 *ox03c10, + struct preisp_hdrae_exp_s *ae) +{ + int ret = 0; + u32 l_dgain = 1024; + u32 m_dgain = 1024; + u32 s_dgain = 1024; + u32 l_exp = ae->long_exp_reg; + u32 m_exp = ae->middle_exp_reg; + u32 s_exp = ae->short_exp_reg; + u32 l_again = ae->long_gain_reg; + u32 m_again = ae->middle_gain_reg; + u32 s_again = ae->short_gain_reg; + + if (!ox03c10->has_init_exp && !ox03c10->streaming) { + ox03c10->init_hdrae_exp = *ae; + ox03c10->has_init_exp = true; + dev_dbg(&ox03c10->client->dev, "ox03c10 don't stream, record exp for hdr!\n"); + return ret; + } + + dev_dbg(&ox03c10->client->dev, + "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n", + l_exp, l_again, m_exp, m_again, s_exp, s_again); + + if (l_exp < 4) + l_exp = 4; + if (s_exp < 1) + s_exp = 1; + if (s_exp > 35 && ox03c10->cur_mode->exp_mode == EXP_HDR3_DCG_VS) + s_exp = 35; + + if (l_again < 16) { + l_again = 16; + } else if (l_again <= 31) { + } else if (l_again <= 47) { + l_again = (l_again - 16) << 1; + } else if (l_again <= 63) { + l_again = (l_again - 32) << 2; + } else if (l_again <= 95) { + l_again = (l_again - 48) << 3; + } else if (l_again >= 248) { + l_dgain = div_u64(l_again * 1024, 248); + l_again = 248; + } else { + dev_err(&ox03c10->client->dev, "%s set l_gain val:0x%x not support", + __func__, l_again); + return -EINVAL; + } + + if (m_again < 16) { + m_again = 16; + } else if (m_again <= 31) { + } else if (m_again <= 47) { + m_again = (m_again - 16) << 1; + } else if (m_again <= 63) { + m_again = (m_again - 32) << 2; + } else if (m_again <= 95) { + m_again = (m_again - 48) << 3; + } else if (m_again >= 248) { + m_dgain = div_u64(m_again * 1024, 248); + m_again = 248; + } else { + dev_err(&ox03c10->client->dev, "%s set m_gain val:0x%x not support", + __func__, m_again); + return -EINVAL; + } + + if (s_again < 16) { + s_again = 16; + } else if (s_again <= 31) { + } else if (s_again <= 47) { + s_again = (s_again - 16) << 1; + } else if (s_again <= 63) { + s_again = (s_again - 32) << 2; + } else if (s_again <= 95) { + s_again = (s_again - 48) << 3; + } else if (s_again >= 248) { + s_dgain = div_u64(s_again * 1024, 248); + s_again = 248; + } else { + dev_err(&ox03c10->client->dev, "%s set s_gain val:0x%x not support", + __func__, s_again); + return -EINVAL; + } + + dev_dbg(&ox03c10->client->dev, + "l_again 0x%x l_dgain 0x%x, m_again 0x%x m_dgain 0x%x, s_again 0x%x s_dgain 0x%x\n", + l_again, l_dgain, m_again, m_dgain, s_again, s_dgain); + + if (ox03c10->streaming) + ret |= ox03c10_i2c_write_reg(ox03c10->client, OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_START_DATA); + // dcg exposure + ret |= ox03c10_i2c_write_reg(ox03c10->client, OX03C10_REG_EXPOSURE_DCG_H, + OX03C10_REG_VALUE_16BIT, + l_exp); + + // hcg real gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_HCG_H, + OX03C10_REG_VALUE_08BIT, + (l_again >> 4) & 0x0f); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_HCG_L, + OX03C10_REG_VALUE_08BIT, + (l_again << 4) & 0xf0); + // hcg digital gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_HCG_H, + OX03C10_REG_VALUE_08BIT, + (l_dgain >> 10) & 0xf); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_HCG_M, + OX03C10_REG_VALUE_08BIT, + (l_dgain >> 2) & 0xff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_HCG_L, + OX03C10_REG_VALUE_08BIT, + (l_dgain << 6) & 0xc0); + + // lcg real gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_LCG_H, + OX03C10_REG_VALUE_08BIT, + (m_again >> 4) & 0x0f); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_LCG_L, + OX03C10_REG_VALUE_08BIT, + (m_again << 4) & 0xf0); + // lcg digital gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_LCG_H, + OX03C10_REG_VALUE_08BIT, + (m_dgain >> 10) & 0xf); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_LCG_M, + OX03C10_REG_VALUE_08BIT, + (m_dgain >> 2) & 0xff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_LCG_L, + OX03C10_REG_VALUE_08BIT, + (m_dgain << 6) & 0xc0); + + if (ox03c10->cur_mode->exp_mode == EXP_HDR3_DCG_VS) { + // vs exposure + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_EXPOSURE_VS_H, + OX03C10_REG_VALUE_16BIT, + s_exp); + + // vs real gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_VS_H, + OX03C10_REG_VALUE_08BIT, + (s_again >> 4) & 0x0f); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_VS_L, + OX03C10_REG_VALUE_08BIT, + (s_again << 4) & 0xf0); + + // vs digital gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_VS_H, + OX03C10_REG_VALUE_08BIT, + (s_dgain >> 10) & 0xf); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_VS_M, + OX03C10_REG_VALUE_08BIT, + (s_dgain >> 2) & 0xff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_VS_L, + OX03C10_REG_VALUE_08BIT, + (s_dgain << 6) & 0xc0); + } else if (ox03c10->cur_mode->exp_mode == EXP_HDR3_DCG_SPD) { + // spd exposure + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_EXPOSURE_SPD_H, + OX03C10_REG_VALUE_16BIT, + s_exp); + + // spd real gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_SPD_H, + OX03C10_REG_VALUE_08BIT, + (s_again >> 4) & 0x0f); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_AGAIN_SPD_L, + OX03C10_REG_VALUE_08BIT, + (s_again << 4) & 0xf0); + + // spd digital gain + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_SPD_H, + OX03C10_REG_VALUE_08BIT, + (s_dgain >> 10) & 0xf); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_SPD_M, + OX03C10_REG_VALUE_08BIT, + (s_dgain >> 2) & 0xff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_DGAIN_SPD_L, + OX03C10_REG_VALUE_08BIT, + (s_dgain << 6) & 0xc0); + } + + if (ox03c10->streaming) { + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_END_DATA); + ret |= ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_LAUNCH); + } + + return ret; +} + +static int ox03c10_set_wb_gain(struct ox03c10 *ox03c10, + struct rkmodule_wb_gain_group *wb_gain_group) +{ + struct rkmodule_wb_gain wb_gain; + u16 reg_bgain, reg_gbgain, reg_grgain, reg_rgain; + int i = 0; + int ret = 0; +#ifdef DEBUG + u32 bgain, gbgain, grgain, rgain; +#endif + + if (!ox03c10->has_init_wbgain && !ox03c10->streaming) { + ox03c10->init_wbgain = *wb_gain_group; + ox03c10->has_init_wbgain = true; + dev_info(&ox03c10->client->dev, "ox03c10 don't stream, record wbgain!\n"); + return ret; + } + + for (i = 0; i < wb_gain_group->group_num; i++) { + switch (wb_gain_group->wb_gain_type[i]) { + case RKMODULE_HCG_WB_GAIN: + reg_bgain = OX03C10_REG_HCG_B_GAIN; + reg_gbgain = OX03C10_REG_HCG_GB_GAIN; + reg_grgain = OX03C10_REG_HCG_GR_GAIN; + reg_rgain = OX03C10_REG_HCG_R_GAIN; + break; + case RKMODULE_LCG_WB_GAIN: + reg_bgain = OX03C10_REG_LCG_B_GAIN; + reg_gbgain = OX03C10_REG_LCG_GB_GAIN; + reg_grgain = OX03C10_REG_LCG_GR_GAIN; + reg_rgain = OX03C10_REG_LCG_R_GAIN; + break; + case RKMODULE_SPD_WB_GAIN: + reg_bgain = OX03C10_REG_SPD_B_GAIN; + reg_gbgain = OX03C10_REG_SPD_GB_GAIN; + reg_grgain = OX03C10_REG_SPD_GR_GAIN; + reg_rgain = OX03C10_REG_SPD_R_GAIN; + break; + case RKMODULE_VS_WB_GAIN: + reg_bgain = OX03C10_REG_VS_B_GAIN; + reg_gbgain = OX03C10_REG_VS_GB_GAIN; + reg_grgain = OX03C10_REG_VS_GR_GAIN; + reg_rgain = OX03C10_REG_VS_R_GAIN; + break; + default: + return -EINVAL; + } + wb_gain = wb_gain_group->wb_gain[i]; + ret = ox03c10_i2c_write_reg(ox03c10->client, reg_bgain, + OX03C10_REG_VALUE_16BIT, wb_gain.b_gain & 0xffff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, reg_grgain, + OX03C10_REG_VALUE_16BIT, wb_gain.gr_gain & 0xffff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, reg_gbgain, + OX03C10_REG_VALUE_16BIT, wb_gain.gb_gain & 0xffff); + ret |= ox03c10_i2c_write_reg(ox03c10->client, reg_rgain, + OX03C10_REG_VALUE_16BIT, wb_gain.r_gain & 0xffff); + dev_info(&ox03c10->client->dev, + "write wb gain, type:%d, b:0x%x, gb:0x%x, gr:0x%x, r:0x%x\n", + wb_gain_group->wb_gain_type[i], + wb_gain.b_gain, wb_gain.gb_gain, + wb_gain.gr_gain, wb_gain.r_gain); +#ifdef DEBUG + ret |= ox03c10_i2c_read_reg(ox03c10->client, reg_bgain, + OX03C10_REG_VALUE_16BIT, &bgain); + ret |= ox03c10_i2c_read_reg(ox03c10->client, reg_gbgain, + OX03C10_REG_VALUE_16BIT, &gbgain); + ret |= ox03c10_i2c_read_reg(ox03c10->client, reg_grgain, + OX03C10_REG_VALUE_16BIT, &grgain); + ret |= ox03c10_i2c_read_reg(ox03c10->client, reg_rgain, + OX03C10_REG_VALUE_16BIT, &rgain); + dev_info(&ox03c10->client->dev, + "read wb gain, type %d, b:0x%x, gb:0x%x, gr:0x%x, r:0x%x\n", + wb_gain_group->wb_gain_type[i], bgain, gbgain, grgain, rgain); +#endif + } + + return ret; +} + +static int ox03c10_set_blc(struct ox03c10 *ox03c10, + struct rkmodule_blc_group *blc_group) +{ + u32 reg_blc = 0; + u32 blc_val = 0; + int i = 0; + int ret = 0; + + for (i = 0; i < blc_group->group_num; i++) { + switch (blc_group->blc_type[i]) { + case RKMODULE_HCG_BLC: + reg_blc = OX03C10_REG_HCG_BLC; + break; + case RKMODULE_LCG_BLC: + reg_blc = OX03C10_REG_LCG_BLC; + break; + case RKMODULE_SPD_BLC: + reg_blc = OX03C10_REG_SPD_BLC; + break; + case RKMODULE_VS_BLC: + reg_blc = OX03C10_REG_VS_BLC; + break; + default: + return -EINVAL; + } + blc_val = blc_group->blc[i]; + ret = ox03c10_i2c_write_reg(ox03c10->client, reg_blc, + OX03C10_REG_VALUE_16BIT, blc_val & 0x3ff); + dev_info(&ox03c10->client->dev, + "write blc, type:%d, blc_val:0x%x\n", + blc_group->blc_type[i], + blc_val); +#ifdef DEBUG + ret |= ox03c10_i2c_read_reg(ox03c10->client, reg_blc, + OX03C10_REG_VALUE_16BIT, &blc_val); + dev_info(&ox03c10->client->dev, + "read blc, type %d, blc_val:0x%x\n", + blc_group->blc_type[i], blc_val); +#endif + } + + return ret; +} + +static int ox03c10_get_channel_info(struct ox03c10 *ox03c10, struct rkmodule_channel_info *ch_info) +{ + if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX) + return -EINVAL; + + ch_info->vc = ox03c10->cur_mode->vc[ch_info->index]; + ch_info->width = ox03c10->cur_mode->width; + ch_info->height = ox03c10->cur_mode->height; + ch_info->bus_fmt = ox03c10->cur_mode->bus_fmt; + if (ox03c10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR16_1X16) { + ch_info->data_type = 0x2a; + ch_info->data_bit = 16; + } + + return 0; +} + +static int ox03c10_select_exp_mode(struct ox03c10 *ox03c10, u32 exp_mode) +{ + int ret = -EINVAL; + u32 i, h, w, hdr_mode; + + w = ox03c10->cur_mode->width; + h = ox03c10->cur_mode->height; + hdr_mode = ox03c10->cur_mode->hdr_mode; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr_mode && + supported_modes[i].exp_mode == exp_mode) { + ox03c10->cur_mode = &supported_modes[i]; + w = ox03c10->cur_mode->hts_def - ox03c10->cur_mode->width; + h = ox03c10->cur_mode->vts_def - ox03c10->cur_mode->height; + __v4l2_ctrl_modify_range(ox03c10->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(ox03c10->vblank, h, + OX03C10_VTS_MAX - ox03c10->cur_mode->height, 1, h); + ret = 0; + break; + } + } + + return ret; +} + +static long ox03c10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + struct rkmodule_hdr_cfg *hdr = NULL; + struct rkmodule_dcg_ratio *dcg_ratio = NULL; + struct rkmodule_wb_gain_group *wb_gain_group = NULL; + struct rkmodule_blc_group *blc_group = NULL; + struct rkmodule_channel_info *ch_info = NULL; + u32 *exp_mode = NULL; + u32 i, h, w; + long ret = 0; + + dev_dbg(&ox03c10->client->dev, "ioctl cmd = 0x%08x\n", cmd); + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + ox03c10_get_module_inf(ox03c10, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = ox03c10->cur_mode->hdr_mode; + if (hdr->hdr_mode == HDR_COMPR) + hdr->compr = *ox03c10->cur_mode->hdr_compr; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + if (ox03c10->cur_mode->hdr_mode == HDR_COMPR) + hdr->hdr_mode = ox03c10->cur_mode->hdr_mode; + w = ox03c10->cur_mode->width; + h = ox03c10->cur_mode->height; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + ox03c10->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) { + dev_err(&ox03c10->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + w = ox03c10->cur_mode->hts_def - ox03c10->cur_mode->width; + h = ox03c10->cur_mode->vts_def - ox03c10->cur_mode->height; + __v4l2_ctrl_modify_range(ox03c10->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(ox03c10->vblank, h, + OX03C10_VTS_MAX - ox03c10->cur_mode->height, 1, h); + } + break; + case PREISP_CMD_SET_HDRAE_EXP: + return ox03c10_set_hdrae(ox03c10, arg); + case RKMODULE_GET_DCG_RATIO: + dcg_ratio = (struct rkmodule_dcg_ratio *)arg; + *dcg_ratio = ox03c10->dcg_ratio; + break; + case RKMODULE_GET_SPD_RATIO: + dcg_ratio = (struct rkmodule_dcg_ratio *)arg; + *dcg_ratio = ox03c10->spd_ratio; + break; + case RKMODULE_SET_WB_GAIN: + wb_gain_group = (struct rkmodule_wb_gain_group *)arg; + ret = ox03c10_set_wb_gain(ox03c10, wb_gain_group); + break; + case RKMODULE_SET_BLC: + blc_group = (struct rkmodule_blc_group *)arg; + ret = ox03c10_set_blc(ox03c10, blc_group); + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = (struct rkmodule_channel_info *)arg; + ret = ox03c10_get_channel_info(ox03c10, ch_info); + break; + case RKMODULE_GET_EXP_MODE: + exp_mode = (u32 *)arg; + *exp_mode = ox03c10->cur_mode->exp_mode; + break; + case RKMODULE_SET_EXP_MODE: + ret = ox03c10_select_exp_mode(ox03c10, *(u32 *)arg); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long ox03c10_compat_ioctl32(struct v4l2_subdev *sd, unsigned int cmd, + unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf = NULL; + struct rkmodule_awb_cfg *cfg = NULL; + struct rkmodule_hdr_cfg *hdr = NULL; + struct preisp_hdrae_exp_s *hdrae = NULL; + struct rkmodule_dcg_ratio *dcg_ratio = NULL; + struct rkmodule_wb_gain_group *wb_gain_group = NULL; + struct rkmodule_blc_group *blc_group = NULL; + struct rkmodule_channel_info *ch_info = NULL; + u32 exp_mode = 0; + long ret = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, inf); + if (!ret) { + if (copy_to_user(up, inf, sizeof(*inf))) { + kfree(inf); + return -EFAULT; + } + } + kfree(inf); + break; + case RKMODULE_AWB_CFG: + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); + if (!cfg) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(cfg, up, sizeof(*cfg))) { + kfree(cfg); + return -EFAULT; + } + ret = ox03c10_ioctl(sd, cmd, cfg); + kfree(cfg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, hdr); + if (!ret) { + if (copy_to_user(up, hdr, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdr, up, sizeof(*hdr))) { + kfree(hdr); + return -EFAULT; + } + ret = ox03c10_ioctl(sd, cmd, hdr); + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + if (copy_from_user(hdrae, up, sizeof(*hdrae))) { + kfree(hdrae); + return -EFAULT; + } + ret = ox03c10_ioctl(sd, cmd, hdrae); + kfree(hdrae); + break; + case RKMODULE_GET_DCG_RATIO: + dcg_ratio = kzalloc(sizeof(*dcg_ratio), GFP_KERNEL); + if (!dcg_ratio) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, dcg_ratio); + if (!ret) { + ret = copy_to_user(up, dcg_ratio, sizeof(*dcg_ratio)); + if (ret) + return -EFAULT; + } + kfree(dcg_ratio); + break; + case RKMODULE_GET_SPD_RATIO: + dcg_ratio = kzalloc(sizeof(*dcg_ratio), GFP_KERNEL); + if (!dcg_ratio) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, dcg_ratio); + if (!ret) { + ret = copy_to_user(up, dcg_ratio, sizeof(*dcg_ratio)); + if (ret) + return -EFAULT; + } + kfree(dcg_ratio); + break; + case RKMODULE_SET_WB_GAIN: + wb_gain_group = kzalloc(sizeof(*wb_gain_group), GFP_KERNEL); + if (!wb_gain_group) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, wb_gain_group); + if (!ret) { + ret = copy_to_user(up, wb_gain_group, sizeof(*wb_gain_group)); + if (ret) + return -EFAULT; + } + kfree(wb_gain_group); + break; + case RKMODULE_SET_BLC: + blc_group = kzalloc(sizeof(*blc_group), GFP_KERNEL); + if (!blc_group) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, blc_group); + if (!ret) { + ret = copy_to_user(up, blc_group, sizeof(*blc_group)); + if (ret) + return -EFAULT; + } + kfree(blc_group); + break; + case RKMODULE_GET_CHANNEL_INFO: + ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL); + if (!ch_info) { + ret = -ENOMEM; + return ret; + } + + ret = ox03c10_ioctl(sd, cmd, ch_info); + if (!ret) { + ret = copy_to_user(up, ch_info, sizeof(*ch_info)); + if (ret) + ret = -EFAULT; + } + kfree(ch_info); + break; + case RKMODULE_GET_EXP_MODE: + ret = ox03c10_ioctl(sd, cmd, &exp_mode); + if (!ret) { + ret = copy_to_user(up, &exp_mode, sizeof(exp_mode)); + if (ret) + return -EFAULT; + } + break; + case RKMODULE_SET_EXP_MODE: + if (copy_from_user(&exp_mode, up, sizeof(u32))) + return -EFAULT; + ret = ox03c10_ioctl(sd, cmd, &exp_mode); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif /* CONFIG_COMPAT */ + +static int ox03c10_check_sensor_id(struct ox03c10 *ox03c10) +{ + struct i2c_client *client = ox03c10->client; + struct device *dev = &client->dev; + u32 sensor_id = 0; + int ret = 0, loop = 0; + + for (loop = 0; loop < 3; loop++) { + if (loop != 0) { + dev_info(dev, "check sensor id retry (%d)", loop); + msleep(10); + } + + ret = ox03c10_i2c_read_reg(client, OX03C10_REG_CHIP_ID, + OX03C10_REG_VALUE_16BIT, &sensor_id); + if (ret == 0) { + if (sensor_id != OX03C10_CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x)\n", sensor_id); + return -ENODEV; + } else { + dev_info(dev, "Detected OV%06x sensor\n", OX03C10_CHIP_ID); + return 0; + } + } + } + + dev_err(dev, "Check sensor id error, ret = %d\n", ret); + + return -ENODEV; +} + +/* Note: In the Serdes scheme, the function must run after start stream */ +static int ox03c10_get_dcg_and_spd_ratio(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + u32 val = 0; + int ret = 0; + + ox03c10->dcg_ratio.integer = 0; + ret |= ox03c10_i2c_read_reg(ox03c10->client, 0x7057, + OX03C10_REG_VALUE_24BIT, &val); + ox03c10->dcg_ratio.decimal = val & 0x1ffff; + ret |= ox03c10_i2c_read_reg(ox03c10->client, 0x705b, + OX03C10_REG_VALUE_24BIT, &val); + ox03c10->dcg_ratio.div_coeff = val & 0x1ffff; + if (ret != 0 || val == 0) + dev_err(dev, "get dcg ratio fail, ret %d, dcg ratio %d, %d\n", + ret, ox03c10->dcg_ratio.integer, ox03c10->dcg_ratio.decimal); + else + dev_info(dev, "get dcg ratio reg val integer %d, dec 0x%x, div 0x%x\n", + ox03c10->dcg_ratio.integer, ox03c10->dcg_ratio.decimal, ox03c10->dcg_ratio.div_coeff); + + ox03c10->spd_ratio.integer = 0; + ox03c10->spd_ratio.decimal = val & 0x1ffff; + ret |= ox03c10_i2c_read_reg(ox03c10->client, 0x705f, + OX03C10_REG_VALUE_24BIT, &val); + ox03c10->spd_ratio.div_coeff = val & 0x1ffff; + if (ret != 0 || val == 0) + dev_err(dev, "get spd ratio fail, ret %d, spd ratio %d, %d\n", + ret, ox03c10->spd_ratio.integer, ox03c10->spd_ratio.decimal); + else + dev_info(dev, "get spd ratio reg val integer %d, dec 0x%x div 0x%x\n", + ox03c10->spd_ratio.integer, ox03c10->spd_ratio.decimal, ox03c10->spd_ratio.div_coeff); + + return ret; +} + +static int __ox03c10_start_stream(struct ox03c10 *ox03c10) +{ + maxim_remote_ser_t *remote_ser = ox03c10->remote_ser; + struct i2c_client *client = ox03c10->client; + struct device *dev = &client->dev; + int ret = 0; + + if (remote_ser == NULL) { + dev_err(dev, "%s: remote_ser error\n", __func__); + return -EINVAL; + } + + if (remote_ser->ser_ops == NULL) { + dev_err(dev, "%s: remote_ser ser_ops error\n", __func__); + return -EINVAL; + } + + ret = remote_ser->ser_ops->ser_module_init(remote_ser); + if (ret) { + dev_err(dev, "%s: remote_ser module_init error\n", __func__); + return ret; + } + + ret = ox03c10_check_sensor_id(ox03c10); + if (ret) { + dev_err(dev, "%s: ox03c10 check sensor id error\n", __func__); + return ret; + } + + ret = ox03c10_i2c_write_array(client, ox03c10->cur_mode->reg_list); + if (ret) { + dev_err(dev, "%s: ox03c10 reg_list write array error\n", __func__); + return ret; + } + + if (ox03c10->cur_mode->hdr_mode == NO_HDR) { + ret = ox03c10_i2c_write_array(client, ox03c10->cur_mode->linear_reg_list); + if (ret) { + dev_err(dev, "%s: ox03c10 linear_reg_list write array error\n", __func__); + return ret; + } + } + + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&ox03c10->ctrl_handler); + if (ret) + return ret; + if (ox03c10->has_init_exp && ox03c10->cur_mode->hdr_mode != NO_HDR) { + ret = ox03c10_ioctl(&ox03c10->subdev, + PREISP_CMD_SET_HDRAE_EXP, + &ox03c10->init_hdrae_exp); + if (ret) { + dev_err(&ox03c10->client->dev, + "init exp fail in hdr mode\n"); + return ret; + } + } + + if (ox03c10->has_init_wbgain) { + ret = ox03c10_ioctl(&ox03c10->subdev, + RKMODULE_SET_WB_GAIN, + &ox03c10->init_wbgain); + if (ret) { + dev_err(&ox03c10->client->dev, + "init wbgain fail\n"); + return ret; + } + } + + /* streaming control register */ + ret = ox03c10_i2c_write_reg(client, + OX03C10_REG_CTRL_MODE, + OX03C10_REG_VALUE_08BIT, + OX03C10_MODE_STREAMING); + if (ret) { + dev_err(dev, "%s: ox03c10 start stream error\n", __func__); + return ret; + } + + ret = remote_ser->ser_ops->ser_pclk_detect(remote_ser); + if (ret) { + dev_err(dev, "%s: remote_ser pclk_detect error\n", __func__); + return ret; + } + + /* note: get dcg and spd ratio after start stream */ + ret = ox03c10_get_dcg_and_spd_ratio(ox03c10); + if (ret) + dev_warn(dev, "get dcg and spd ratio failed\n"); + + return 0; +} + +static int __ox03c10_stop_stream(struct ox03c10 *ox03c10) +{ + maxim_remote_ser_t *remote_ser = ox03c10->remote_ser; + struct i2c_client *client = ox03c10->client; + struct device *dev = &client->dev; + int ret = 0; + + ox03c10->has_init_exp = false; + ox03c10->has_init_wbgain = false; + + /* streaming control register */ + ret = ox03c10_i2c_write_reg(client, + OX03C10_REG_CTRL_MODE, + OX03C10_REG_VALUE_08BIT, + OX03C10_MODE_SW_STANDBY); + if (ret) { + dev_err(dev, "%s: ox03c10 stop stream error\n", __func__); + return ret; + } + + if (remote_ser == NULL) { + dev_err(dev, "%s: remote_ser error\n", __func__); + return -EINVAL; + } + + if (remote_ser->ser_ops == NULL) { + dev_err(dev, "%s: remote_ser ser_ops error\n", __func__); + return -EINVAL; + } + + ret = remote_ser->ser_ops->ser_module_deinit(remote_ser); + if (ret) { + dev_err(dev, "%s: remote_ser module_deinit error\n", __func__); + return ret; + } + + return 0; +} + +static int ox03c10_s_stream(struct v4l2_subdev *sd, int on) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + struct i2c_client *client = ox03c10->client; + int ret = 0; + + dev_info(&client->dev, "%s: on = %d\n", __func__, on); + + mutex_lock(&ox03c10->mutex); + on = !!on; + if (on == ox03c10->streaming) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __ox03c10_start_stream(ox03c10); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __ox03c10_stop_stream(ox03c10); + pm_runtime_put(&client->dev); + } + + ox03c10->streaming = on; + +unlock_and_return: + mutex_unlock(&ox03c10->mutex); + + return ret; +} + +static int ox03c10_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + const struct ox03c10_mode *mode = ox03c10->cur_mode; + + fi->interval = mode->max_fps; + + return 0; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +#else +static int ox03c10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + if (code->index != 0) + return -EINVAL; + code->code = ox03c10->cur_mode->bus_fmt; + + return 0; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +#else +static int ox03c10_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + if (fse->index >= ox03c10->cfg_modes_num) + return -EINVAL; + + if (fse->code != ox03c10->supported_modes[fse->index].bus_fmt) + return -EINVAL; + + fse->min_width = ox03c10->supported_modes[fse->index].width; + fse->max_width = ox03c10->supported_modes[fse->index].width; + fse->max_height = ox03c10->supported_modes[fse->index].height; + fse->min_height = ox03c10->supported_modes[fse->index].height; + + return 0; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +#else +static int ox03c10_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + if (fie->index >= ox03c10->cfg_modes_num) + return -EINVAL; + + fie->code = ox03c10->supported_modes[fie->index].bus_fmt; + fie->width = ox03c10->supported_modes[fie->index].width; + fie->height = ox03c10->supported_modes[fie->index].height; + fie->interval = ox03c10->supported_modes[fie->index].max_fps; + + return 0; +} + +static int ox03c10_get_reso_dist(const struct ox03c10_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct ox03c10_mode * +ox03c10_find_best_fit(struct ox03c10 *ox03c10, struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ox03c10->cfg_modes_num; i++) { + dist = ox03c10_get_reso_dist(&ox03c10->supported_modes[i], framefmt); + if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) && + (ox03c10->supported_modes[i].bus_fmt == framefmt->code)) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &ox03c10->supported_modes[cur_best_fit]; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +#else +static int ox03c10_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + struct device *dev = &ox03c10->client->dev; + const struct ox03c10_mode *mode; + u64 link_freq = 0, pixel_rate = 0; + s64 h_blank, vblank_def; + u8 data_lanes = ox03c10->bus_cfg.bus.mipi_csi2.num_data_lanes; + + mutex_lock(&ox03c10->mutex); + + mode = ox03c10_find_best_fit(ox03c10, fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + #if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; + #else + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; + #endif +#else + mutex_unlock(&ox03c10->mutex); + return -ENOTTY; +#endif + } else { + ox03c10->cur_mode = mode; + + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(ox03c10->hblank, + h_blank, h_blank, 1, h_blank); + + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(ox03c10->vblank, + vblank_def, OX03C10_VTS_MAX - mode->height, 1, vblank_def); + + __v4l2_ctrl_s_ctrl(ox03c10->link_freq, mode->link_freq_idx); + + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + link_freq = link_freq_menu_items[mode->link_freq_idx]; + pixel_rate = (u32)link_freq / mode->bpp * 2 * data_lanes; + __v4l2_ctrl_s_ctrl_int64(ox03c10->pixel_rate, pixel_rate); + + dev_info(dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n", + mode->link_freq_idx, link_freq); + dev_info(dev, "pixel_rate = %lld, bpp = %d\n", + pixel_rate, mode->bpp); + } + + dev_info(dev, "Set format done!(cur_mode: %d)\n", mode->hdr_mode); + + mutex_unlock(&ox03c10->mutex); + + return 0; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +#else +static int ox03c10_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + const struct ox03c10_mode *mode = ox03c10->cur_mode; + + mutex_lock(&ox03c10->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + #if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); + #else + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + #endif +#else + mutex_unlock(&ox03c10->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&ox03c10->mutex); + + return 0; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +#else +static int ox03c10_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +#endif +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { + sel->r.left = 0; + sel->r.width = ox03c10->cur_mode->width; + sel->r.top = 0; + sel->r.height = ox03c10->cur_mode->height; + return 0; + } + + return -EINVAL; +} + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE +static int ox03c10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad, + struct v4l2_mbus_config *config) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + config->type = V4L2_MBUS_CSI2_DPHY; + config->bus.mipi_csi2 = ox03c10->bus_cfg.bus.mipi_csi2; + + return 0; +} +#elif KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE +static int ox03c10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad, + struct v4l2_mbus_config *config) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + u32 val = 0; + u8 data_lanes = ox03c10->bus_cfg.bus.mipi_csi2.num_data_lanes; + + val |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + val |= (1 << (data_lanes - 1)); + + val |= V4L2_MBUS_CSI2_CHANNEL_0; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} +#else +static int ox03c10_g_mbus_config(struct v4l2_subdev *sd, + struct v4l2_mbus_config *config) +{ + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + u32 val = 0; + u8 data_lanes = ox03c10->bus_cfg.bus.mipi_csi2.num_data_lanes; + + val |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + val |= (1 << (data_lanes - 1)); + + val |= V4L2_MBUS_CSI2_CHANNEL_0; + + config->type = V4L2_MBUS_CSI2; + config->flags = val; + + return 0; +} +#endif /* LINUX_VERSION_CODE */ + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops ox03c10_internal_ops = { + .open = ox03c10_open, +}; +#endif + +static const struct v4l2_subdev_core_ops ox03c10_core_ops = { + .s_power = ox03c10_s_power, + .ioctl = ox03c10_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = ox03c10_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops ox03c10_video_ops = { + .s_stream = ox03c10_s_stream, + .g_frame_interval = ox03c10_g_frame_interval, +#if KERNEL_VERSION(5, 10, 0) > LINUX_VERSION_CODE + .g_mbus_config = ox03c10_g_mbus_config, +#endif +}; + +static const struct v4l2_subdev_pad_ops ox03c10_pad_ops = { + .enum_mbus_code = ox03c10_enum_mbus_code, + .enum_frame_size = ox03c10_enum_frame_sizes, + .enum_frame_interval = ox03c10_enum_frame_interval, + .get_fmt = ox03c10_get_fmt, + .set_fmt = ox03c10_set_fmt, + .get_selection = ox03c10_get_selection, +#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE + .get_mbus_config = ox03c10_g_mbus_config, +#endif +}; + +static const struct v4l2_subdev_ops ox03c10_subdev_ops = { + .core = &ox03c10_core_ops, + .video = &ox03c10_video_ops, + .pad = &ox03c10_pad_ops, +}; + +static int ox03c10_enable_test_pattern(struct ox03c10 *ox03c10, u32 pattern) +{ + u32 val; + + if (pattern) + val = (pattern - 1) | OX03C10_TEST_PATTERN_ENABLE; + else + val = OX03C10_TEST_PATTERN_DISABLE; + + return ox03c10_i2c_write_reg(ox03c10->client, + OX03C10_REG_TEST_PATTERN, + OX03C10_REG_VALUE_08BIT, val); +} + +static int ox03c10_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ox03c10 *ox03c10 = container_of(ctrl->handler, + struct ox03c10, ctrl_handler); + struct i2c_client *client = ox03c10->client; + s64 exposure_max = 0; + u16 exp_reg, again_reg, dgain_reg; + u32 again = 16, dgain = 1024; + u32 val = 0; + int ret = 0; + + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + exposure_max = (ox03c10->cur_mode->height + ctrl->val) / 2 - 12; + __v4l2_ctrl_modify_range(ox03c10->exposure, + ox03c10->exposure->minimum, exposure_max, + ox03c10->exposure->step, + ox03c10->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + // i2c can't be accessed before serdes link ok + if (maxim_remote_ser_is_inited(ox03c10->remote_ser) == false) { + dev_warn(&client->dev, "%s ctrl id = 0x%x before serializer init\n", + __func__, ctrl->id); + return 0; + } + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + if (ox03c10->cur_mode->hdr_mode != NO_HDR) + break; + + dev_info(&client->dev, "%s set exposure: val = 0x%x", __func__, ctrl->val); + + if (ox03c10->streaming) + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_START_DATA); + + // dcg exposure register + exp_reg = OX03C10_REG_EXPOSURE_DCG_H; + ret |= ox03c10_i2c_write_reg(client, + exp_reg, + OX03C10_REG_VALUE_16BIT, + ctrl->val); + + if (ox03c10->streaming) { + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_END_DATA); + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP_UPDATE_LAUNCH); + } + + break; + case V4L2_CID_ANALOGUE_GAIN: + if (ox03c10->cur_mode->hdr_mode != NO_HDR) + break; + /* + *[1, 1.9375, 16, 0, 1, 16, 31, + * 2, 3.875, 8, -16, 1, 32, 47, + * 4, 7.75, 4, -32, 1, 48, 63, + * 8, 15.5, 2,-48, 1, 64, 95, + * 15.5, 247.9375, 16, 0, 1, 248, 3967] + */ + // hcg real gain + if (ctrl->val < 16) { + again = 16; + } else if (ctrl->val <= 31) { + again = ctrl->val; + } else if (ctrl->val <= 47) { + again = (ctrl->val - 16) << 1; + } else if (ctrl->val <= 63) { + again = (ctrl->val - 32) << 2; + } else if (ctrl->val <= 95) { + again = (ctrl->val - 48) << 3; + } else if (ctrl->val >= 248) { + dgain = div_u64(ctrl->val * 1024, 248); + again = 248; + } else { + dev_err(&client->dev, "%s set gain val:0x%x not support", + __func__, ctrl->val); + break; + } + + if (ox03c10->streaming) + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP1_UPDATE_START_DATA); + + // lcg gain register + again_reg = OX03C10_REG_AGAIN_LCG_H; + dgain_reg = OX03C10_REG_DGAIN_LCG_H; + + ret |= ox03c10_i2c_write_reg(client, + again_reg, + OX03C10_REG_VALUE_16BIT, + (again << 4) & 0xff0); + ret |= ox03c10_i2c_write_reg(client, + dgain_reg, + OX03C10_REG_VALUE_24BIT, + (dgain << 6) & 0xfffc0); + + if (ox03c10->streaming) { + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP1_UPDATE_END_DATA); + ret |= ox03c10_i2c_write_reg(client, + OX03C10_GROUP_UPDATE_ADDRESS, + OX03C10_REG_VALUE_08BIT, + OX03C10_GROUP1_UPDATE_LAUNCH); + } + + dev_info(&client->dev, "%s set analog gain(ret = %d): val = 0x%x, again = 0x%x, dgain = 0x%x\n", + __func__, ret, ctrl->val, again, dgain); + break; + case V4L2_CID_VBLANK: + ret = ox03c10_i2c_write_reg(client, + OX03C10_REG_VTS, + OX03C10_REG_VALUE_16BIT, + (ctrl->val + ox03c10->cur_mode->height) / 2); + break; + case V4L2_CID_TEST_PATTERN: + ret = ox03c10_enable_test_pattern(ox03c10, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = ox03c10_i2c_read_reg(client, + OX03C10_VFLIP_REG, + OX03C10_REG_VALUE_08BIT, + &val); + if (ctrl->val) + val |= MIRROR_BIT_MASK; + else + val &= ~MIRROR_BIT_MASK; + ret |= ox03c10_i2c_write_reg(client, + OX03C10_VFLIP_REG, + OX03C10_REG_VALUE_08BIT, + val); + break; + case V4L2_CID_VFLIP: + ret = ox03c10_i2c_read_reg(client, + OX03C10_VFLIP_REG, + OX03C10_REG_VALUE_08BIT, + &val); + if (ctrl->val) + val |= FLIP_BIT_MASK; + else + val &= ~FLIP_BIT_MASK; + ret |= ox03c10_i2c_write_reg(client, + OX03C10_VFLIP_REG, + OX03C10_REG_VALUE_08BIT, + val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ox03c10_ctrl_ops = { + .s_ctrl = ox03c10_set_ctrl, +}; + +static int ox03c10_initialize_controls(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + const struct ox03c10_mode *mode; + struct v4l2_ctrl_handler *handler; + u64 link_freq = 0, pixel_rate = 0; + s64 exposure_max = 0, vblank_def; + u32 h_blank; + u8 data_lanes; + + int ret = 0; + + handler = &ox03c10->ctrl_handler; + mode = ox03c10->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + + handler->lock = &ox03c10->mutex; + + /* ctrl handler: link freq */ + ox03c10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, 0, + link_freq_menu_items); + v4l2_ctrl_s_ctrl(ox03c10->link_freq, mode->link_freq_idx); + link_freq = link_freq_menu_items[mode->link_freq_idx]; + dev_info(dev, "mipi_freq_idx = %d, mipi_link_freq = %lld\n", + mode->link_freq_idx, link_freq); + + /* ctrl handler: pixel rate */ + /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */ + data_lanes = ox03c10->bus_cfg.bus.mipi_csi2.num_data_lanes; + pixel_rate = (u32)link_freq / mode->bpp * 2 * data_lanes; + + ox03c10->pixel_rate = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_PIXEL_RATE, + 0, pixel_rate, 1, pixel_rate); + dev_info(dev, "pixel_rate = %lld, bpp = %d\n", pixel_rate, mode->bpp); + + /* ctrl handler: hblank */ + h_blank = mode->hts_def - mode->width; + ox03c10->hblank = v4l2_ctrl_new_std(handler, NULL, + V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (ox03c10->hblank) + ox03c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + /* ctrl handler: vblank */ + vblank_def = mode->vts_def - mode->height; + ox03c10->vblank = v4l2_ctrl_new_std(handler, &ox03c10_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + OX03C10_VTS_MAX, + 1, vblank_def); + + /* ctrl handler: exposure */ + exposure_max = mode->vts_def / 2 - 12; + dev_info(dev, "exposure_max = %lld\n", exposure_max); + ox03c10->exposure = v4l2_ctrl_new_std(handler, &ox03c10_ctrl_ops, + V4L2_CID_EXPOSURE, + OX03C10_EXPOSURE_HCG_MIN, exposure_max, + OX03C10_EXPOSURE_HCG_STEP, mode->exp_def); + + /* ctrl handler: test pattern */ + ox03c10->test_pattern = v4l2_ctrl_new_std_menu_items(handler, &ox03c10_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ox03c10_test_pattern_menu) - 1, + 0, 0, ox03c10_test_pattern_menu); + + /* ctrl handler: analogue gain */ + ox03c10->anal_gain = v4l2_ctrl_new_std(handler, &ox03c10_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, + OX03C10_GAIN_MIN, OX03C10_GAIN_MAX, + OX03C10_GAIN_STEP, OX03C10_GAIN_DEFAULT); + + /* ctrl handler: hflip */ + ox03c10->h_flip = v4l2_ctrl_new_std(handler, &ox03c10_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + /* ctrl handler: vflip */ + ox03c10->v_flip = v4l2_ctrl_new_std(handler, &ox03c10_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (handler->error) { + ret = handler->error; + dev_err(&ox03c10->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + ox03c10->subdev.ctrl_handler = handler; + ox03c10->has_init_exp = false; + ox03c10->has_init_wbgain = false; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int ox03c10_parse_dt(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + struct device_node *of_node = dev->of_node; + u32 value = 0; + int ret = 0; + + dev_info(dev, "=== ox03c10 parse dt ===\n"); + + ret = of_property_read_u32(of_node, "cam-i2c-addr-def", &value); + if (ret == 0) { + dev_info(dev, "cam-i2c-addr-def property: 0x%x", value); + ox03c10->cam_i2c_addr_def = value; + } else { + ox03c10->cam_i2c_addr_def = OX03C10_I2C_ADDR_DEF; + } + + return 0; +} + +static int ox03c10_mipi_data_lanes_parse(struct ox03c10 *ox03c10) +{ + struct device *dev = &ox03c10->client->dev; + struct device_node *endpoint = NULL; + u8 mipi_data_lanes; + int ret = 0; + + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!endpoint) { + dev_err(dev, "Failed to get endpoint\n"); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), + &ox03c10->bus_cfg); + if (ret) { + dev_err(dev, "Failed to get bus config\n"); + return -EINVAL; + } + mipi_data_lanes = ox03c10->bus_cfg.bus.mipi_csi2.num_data_lanes; + dev_info(dev, "mipi csi2 phy data lanes = %d\n", mipi_data_lanes); + + return 0; +} + +static int ox03c10_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct ox03c10 *ox03c10 = NULL; + struct v4l2_subdev *sd = NULL; + maxim_remote_ser_t *remote_ser = NULL; + char facing[2]; + u32 hdr_mode = 0, hdr_operating_mode = 0; + int ret = 0; + + dev_info(dev, "driver version: %02x.%02x.%02x", DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, DRIVER_VERSION & 0x00ff); + + ox03c10 = devm_kzalloc(dev, sizeof(*ox03c10), GFP_KERNEL); + if (!ox03c10) { + dev_err(dev, "ox03c10 probe no memory error\n"); + return -ENOMEM; + } + + ox03c10->client = client; + ox03c10->cam_i2c_addr_map = client->addr; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &ox03c10->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &ox03c10->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &ox03c10->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &ox03c10->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + // poc regulator + ox03c10->poc_regulator = devm_regulator_get(dev, "poc"); + if (IS_ERR(ox03c10->poc_regulator)) { + if (PTR_ERR(ox03c10->poc_regulator) != -EPROBE_DEFER) + dev_err(dev, "Unable to get PoC regulator (%ld)\n", + PTR_ERR(ox03c10->poc_regulator)); + else + dev_err(dev, "Get PoC regulator deferred\n"); + + ret = PTR_ERR(ox03c10->poc_regulator); + + return ret; + } + + /* hdr mode */ + ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode); + if (ret) { + hdr_mode = NO_HDR; + dev_warn(dev, "Get hdr mode failed! no hdr default\n"); + } + + if (hdr_mode != NO_HDR) { + // HDR Operating Mode + ret = of_property_read_u32(node, OF_CAMERA_HDR_OPERATING_MODE, + &hdr_operating_mode); + if (ret) + hdr_operating_mode = OX03C10_HDR3_DCG_VS_12BIT; + if (hdr_operating_mode >= OX03C10_HDR_OPERATING_MODE_MAX) + hdr_operating_mode = OX03C10_HDR3_DCG_VS_12BIT; + dev_info(dev, "HDR_COMPR mode, hdr_operating_mode: %d\n", hdr_operating_mode); + } else { + dev_info(dev, "NO_HDR mode\n"); + hdr_operating_mode = OX03C10_HDR_OPERATING_MODE_MAX; + } + + ox03c10_mipi_data_lanes_parse(ox03c10); + ox03c10->supported_modes = supported_modes; + ox03c10->cfg_modes_num = ARRAY_SIZE(supported_modes); + ox03c10->cur_mode = ox03c10_find_mode(hdr_mode, hdr_operating_mode); + + mutex_init(&ox03c10->mutex); + + ret = __ox03c10_power_on(ox03c10); + if (ret) + goto err_destroy_mutex; + + pm_runtime_set_active(dev); + pm_runtime_get_noresume(dev); + pm_runtime_enable(dev); + + sd = &ox03c10->subdev; + v4l2_i2c_subdev_init(sd, client, &ox03c10_subdev_ops); + ret = ox03c10_initialize_controls(ox03c10); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &ox03c10_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; +#endif + +#if defined(CONFIG_MEDIA_CONTROLLER) + ox03c10->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &ox03c10->pad); + if (ret < 0) + goto err_free_handler; +#endif + + v4l2_set_subdevdata(sd, ox03c10); + + memset(facing, 0, sizeof(facing)); + if (strcmp(ox03c10->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + ox03c10->module_index, facing, OX03C10_NAME, + dev_name(sd->dev)); + +#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE + ret = v4l2_async_register_subdev_sensor(sd); +#else + ret = v4l2_async_register_subdev_sensor_common(sd); +#endif + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + ox03c10_parse_dt(ox03c10); + + /* remote serializer bind */ + ox03c10->remote_ser = NULL; + remote_ser = maxim_remote_cam_bind_ser(dev); + if (remote_ser != NULL) { + dev_info(dev, "remote serializer bind success\n"); + + remote_ser->cam_i2c_addr_def = ox03c10->cam_i2c_addr_def; + remote_ser->cam_i2c_addr_map = ox03c10->cam_i2c_addr_map; + + ox03c10->remote_ser = remote_ser; + } else { + dev_err(dev, "remote serializer bind fail\n"); + } + + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + +err_free_handler: + v4l2_ctrl_handler_free(&ox03c10->ctrl_handler); + +err_power_off: + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + __ox03c10_power_off(ox03c10); + +err_destroy_mutex: + mutex_destroy(&ox03c10->mutex); + + return ret; +} + +#if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE +static int ox03c10_remove(struct i2c_client *client) +#else +static void ox03c10_remove(struct i2c_client *client) +#endif +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ox03c10 *ox03c10 = v4l2_get_subdevdata(sd); + + v4l2_async_unregister_subdev(sd); + +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&ox03c10->ctrl_handler); + + mutex_destroy(&ox03c10->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __ox03c10_power_off(ox03c10); + pm_runtime_set_suspended(&client->dev); + +#if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE + return 0; +#endif +} + +static const struct of_device_id ox03c10_of_match[] = { + { .compatible = "maxim,ovti,ox03c10" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ox03c10_of_match); + +static struct i2c_driver ox03c10_i2c_driver = { + .driver = { + .name = "maxim-ox03c10", + .pm = &ox03c10_pm_ops, + .of_match_table = of_match_ptr(ox03c10_of_match), + }, + .probe = &ox03c10_probe, + .remove = &ox03c10_remove, +}; + +module_i2c_driver(ox03c10_i2c_driver); + +MODULE_AUTHOR("Cai Wenzhong "); +MODULE_DESCRIPTION("Maxim Remote Sensor OmniVision OX03C10 Driver"); +MODULE_LICENSE("GPL"); From 074f6d9f667f276e66bdfeba0180d3daadb0fd59 Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Mon, 19 May 2025 17:42:21 +0800 Subject: [PATCH 14/25] arm64: configs: rk3576_vehicle.config: add CONFIG_VIDEO_MAXIM_CAM_OX03C10=y Signed-off-by: Cai Wenzhong Change-Id: Ic3f099bf60f6f4a67a9ef4e828ae94df4db5ad8a --- arch/arm64/configs/rk3576_vehicle.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/rk3576_vehicle.config b/arch/arm64/configs/rk3576_vehicle.config index e0424eddf58a..48d2fa06cb71 100644 --- a/arch/arm64/configs/rk3576_vehicle.config +++ b/arch/arm64/configs/rk3576_vehicle.config @@ -173,6 +173,7 @@ CONFIG_VIDEO_MAXIM_CAM_DUMMY=y # CONFIG_VIDEO_MAXIM_CAM_OS04A10 is not set CONFIG_VIDEO_MAXIM_CAM_OV231X=y CONFIG_VIDEO_MAXIM_CAM_OX01F10=y +CONFIG_VIDEO_MAXIM_CAM_OX03C10=y CONFIG_VIDEO_MAXIM_CAM_OX03J10=y CONFIG_VIDEO_MAXIM_CAM_SC320AT=y # CONFIG_VIDEO_MAXIM_DES_MAXIM2C is not set From f4ba124d0c9c177a7a39224deba9e5d56ea7a3c0 Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Mon, 19 May 2025 17:15:14 +0800 Subject: [PATCH 15/25] arm64: dts: rockchip: add rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi Signed-off-by: Cai Wenzhong Change-Id: I7b3deff0816369b97d3195867f2b59af3aac0cb6 --- ...-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi | 820 ++++++++++++++++++ 1 file changed, 820 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi new file mode 100644 index 000000000000..fbaac4e42f25 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi @@ -0,0 +1,820 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ +#include + +/* ox03c10 hdr mode enable */ +#define OX03C10_HDR_ENABLE 0 + +#if (OX03C10_HDR_ENABLE != 0) +/* ox03c10 hdr operating mode */ +#define OX03C10_HDR3_DCG_VS_12BIT 0 +#define OX03C10_HDR3_DCG_SPD_12BIT 1 + +#define OX03C10_HDR_MODE OX03C10_HDR3_DCG_VS_12BIT +#endif /* OX03C10_HDR_ENABLE */ + +/ { + max96712_dphy0_osc: max96712-dphy0-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy0-osc"; + }; + + max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc_2v0_pldo_s3>; + }; + + max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_2v0_pldo_s3>; + }; + + max96712_dphy0_pwdn_regulator: max96712-dphy0-pwdn-regulator { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_pwdn"; + gpio = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy0_pwdn>; + enable-active-high; + startup-delay-us = <10000>; + off-on-delay-us = <5000>; + }; + + max96712_dphy0_poc_regulator: max96712-dphy0-poc0-regulator { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_poc"; + gpio = <&i2c7_nca9539_gpio 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + off-on-delay-us = <5000>; + vin-supply = <&dphy0_vcc12v_buck1>; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + max96712_dphy0: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy0_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy0_errb>, <&max96712_dphy0_lock>; + power-domains = <&power RK3576_PD_VI>; + rockchip,grf = <&sys_grf>; + vcc1v2-supply = <&max96712_dphy0_vcc1v2>; + vcc1v8-supply = <&max96712_dphy0_vcc1v8>; + pwdn-supply = <&max96712_dphy0_pwdn_regulator>; + lock-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + port { + max96712_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + +#if (OX03C10_HDR_ENABLE == 0) + bus-format = ; + bpp = <10>; + exp-def = <0x0200>; + hts-def = <0x10fe>; + vts-def = <0x055c>; // 0x02ae * 2 +#else + bus-format = ; + bpp = <12>; + exp-def = <0x0200>; + hts-def = <0x10fe>; + vts-def = <0x055c>; // 0x02ae * 2 +#endif /* OX03C10_HDR_ENABLE */ + sensor-width = <1920>; + sensor-height = <1080>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + link-freq-idx = <20>; + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy0_cam0>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy0_cam1>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy0_cam2>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <1>; // 0: GMSL1, 1: GMSL2 + link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS + link-tx-rate = <0>; // 0: default for 187.5MBPS + + link-remote-cam = <&max96712_dphy0_cam3>; // remote camera + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT +#if (OX03C10_HDR_ENABLE == 0) + 09 0D 2b 00 00 // SRC0 VC = 0, DT = RAW10 + 09 0E 2b 00 00 // DST0 VC = 0, DT = RAW10 +#else + 09 0D 2c 00 00 // SRC0 VC = 0, DT = RAW12 + 09 0E 2c 00 00 // DST0 VC = 0, DT = RAW12 +#endif /* OX03C10_HDR_ENABLE */ + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT +#if (OX03C10_HDR_ENABLE == 0) + 09 4D 2b 00 00 // SRC0 VC = 0, DT = RAW10 + 09 4E 6b 00 00 // DST0 VC = 1, DT = RAW10 +#else + 09 4D 2c 00 00 // SRC0 VC = 0, DT = RAW12 + 09 4E 6c 00 00 // DST0 VC = 1, DT = RAW12 +#endif /* OX03C10_HDR_ENABLE */ + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT +#if (OX03C10_HDR_ENABLE == 0) + 09 8D 2b 00 00 // SRC0 VC = 0, DT = RAW10 + 09 8E ab 00 00 // DST0 VC = 2, DT = RAW10 +#else + 09 8D 2c 00 00 // SRC0 VC = 0, DT = RAW12 + 09 8E ac 00 00 // DST0 VC = 2, DT = RAW12 +#endif /* OX03C10_HDR_ENABLE */ + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT +#if (OX03C10_HDR_ENABLE == 0) + 09 CD 2b 00 00 // SRC0 VC = 0, DT = RAW10 + 09 CE eb 00 00 // DST0 VC = 3, DT = RAW10 +#else + 09 CD 2c 00 00 // SRC0 VC = 0, DT = RAW12 + 09 CE ec 00 00 // DST0 VC = 3, DT = RAW12 +#endif /* OX03C10_HDR_ENABLE */ + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes + phy-force-clock-out = <1>; // 1: default for force clock out + phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0 + phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3 + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; // 0: DPHY, 1: CPHY + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; // 0: DPHY, 1: CPHY + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* i2c-mux start */ + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // Note: Serializer node defined before camera node + max96712_dphy0_ser0: max96717@51 { + compatible = "maxim,ser,max96717"; + reg = <0x51>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0 + 03 02 10 00 00 // Improve CMU voltage performance to improve link robustness + 14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation + 14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode + 03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz + 00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output + 05 70 0c 00 00 // PIO06_SLEW = 00: MFP4 Rise and fall time speed setting, 00 is fastest + 00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled + 02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup + 02 BE 10 00 0a // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1 + ]; + }; + }; + + max96712_dphy0_cam0: ox03c10@31 { + compatible = "maxim,ovti,ox03c10"; + reg = <0x31>; + + cam-i2c-addr-def = <0x36>; + + cam-remote-ser = <&max96712_dphy0_ser0>; // remote serializer + + poc-supply = <&max96712_dphy0_poc_regulator>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + +#if (OX03C10_HDR_ENABLE != 0) + rockchip,camera-hdr-mode = <7>; // HDR_COMPR + + /* hdr operating mode + * 0: OX03C10_HDR3_DCG_VS_12BIT + * 1: OX03C10_HDR3_DCG_SPD_12BIT + */ + hdr-operating-mode = ; // 0 ~ 1 +#endif /* OX03C10_HDR_ENABLE */ + + /* port config start */ + port { + max96712_dphy0_cam0_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // Note: Serializer node defined before camera node + max96712_dphy0_ser1: max96717@52 { + compatible = "maxim,ser,max96717"; + reg = <0x52>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0 + 03 02 10 00 00 // Improve CMU voltage performance to improve link robustness + 14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation + 14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode + 03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz + 00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output + 05 70 0c 00 00 // PIO06_SLEW = 00: MFP4 Rise and fall time speed setting, 00 is fastest + 00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled + 02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup + 02 BE 10 00 0a // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1 + ]; + }; + }; + + max96712_dphy0_cam1: ox03c10@32 { + compatible = "maxim,ovti,ox03c10"; + reg = <0x32>; + + cam-i2c-addr-def = <0x36>; + + cam-remote-ser = <&max96712_dphy0_ser1>; // remote serializer + + poc-supply = <&max96712_dphy0_poc_regulator>; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + +#if (OX03C10_HDR_ENABLE != 0) + rockchip,camera-hdr-mode = <7>; // HDR_COMPR + + /* hdr operating mode + * 0: OX03C10_HDR3_DCG_VS_12BIT + * 1: OX03C10_HDR3_DCG_SPD_12BIT + */ + hdr-operating-mode = ; // 0 ~ 1 +#endif /* OX03C10_HDR_ENABLE */ + + /* port config start */ + port { + max96712_dphy0_cam1_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // Note: Serializer node defined before camera node + max96712_dphy0_ser2: max96717@53 { + compatible = "maxim,ser,max96717"; + reg = <0x53>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0 + 03 02 10 00 00 // Improve CMU voltage performance to improve link robustness + 14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation + 14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode + 03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz + 00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output + 05 70 0c 00 00 // PIO06_SLEW = 00: MFP4 Rise and fall time speed setting, 00 is fastest + 00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled + 02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup + 02 BE 10 00 0a // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1 + ]; + }; + }; + + max96712_dphy0_cam2: ox03c10@33 { + compatible = "maxim,ovti,ox03c10"; + reg = <0x33>; + + cam-i2c-addr-def = <0x36>; + + cam-remote-ser = <&max96712_dphy0_ser2>; // remote serializer + + poc-supply = <&max96712_dphy0_poc_regulator>; + + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + +#if (OX03C10_HDR_ENABLE != 0) + rockchip,camera-hdr-mode = <7>; // HDR_COMPR + + /* hdr operating mode + * 0: OX03C10_HDR3_DCG_VS_12BIT + * 1: OX03C10_HDR3_DCG_SPD_12BIT + */ + hdr-operating-mode = ; // 0 ~ 1 +#endif /* OX03C10_HDR_ENABLE */ + + /* port config start */ + port { + max96712_dphy0_cam2_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // Note: Serializer node defined before camera node + max96712_dphy0_ser3: max96717@54 { + compatible = "maxim,ser,max96717"; + reg = <0x54>; + + ser-i2c-addr-def = <0x40>; + + ser-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0 + 03 02 10 00 00 // Improve CMU voltage performance to improve link robustness + 14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation + 14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode + 03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz + 00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output + 05 70 0c 00 00 // PIO06_SLEW = 00: MFP4 Rise and fall time speed setting, 00 is fastest + 00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled + 02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup + 02 BE 10 00 0a // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1 + ]; + }; + }; + + max96712_dphy0_cam3: ox03c10@34 { + compatible = "maxim,ovti,ox03c10"; + reg = <0x34>; + + cam-i2c-addr-def = <0x36>; + + cam-remote-ser = <&max96712_dphy0_ser3>; // remote serializer + + poc-supply = <&max96712_dphy0_poc_regulator>; + + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + +#if (OX03C10_HDR_ENABLE != 0) + rockchip,camera-hdr-mode = <7>; // HDR_COMPR + + /* hdr operating mode + * 0: OX03C10_HDR3_DCG_VS_12BIT + * 1: OX03C10_HDR3_DCG_SPD_12BIT + */ + hdr-operating-mode = ; // 0 ~ 1 +#endif /* OX03C10_HDR_ENABLE */ + + /* port config start */ + port { + max96712_dphy0_cam3_out: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + /* port config end */ + }; + }; + }; + /* i2c-mux end */ + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi1_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi1_in: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dphy0 { + max96712_dphy0_pwdn: max96712-dphy0-pwdn { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy0_errb: max96712-dphy0-errb { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy0_lock: max96712-dphy0-lock { + rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; From 0e3575487cc79fe2865649db38f13476c5b9fa1e Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Mon, 19 May 2025 17:20:27 +0800 Subject: [PATCH 16/25] arm64: dts: rockchip: rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi: enable multi raw sensor mode Note: multiple raw sensor link to isp depend on config MULTI_RAW_SENSOR_LINK_TO_ISP Signed-off-by: Cai Wenzhong Change-Id: I700fcc8b94b0c993b125ca8cba60f1148f38900f --- ...-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi | 217 ++++++++++++++++++ 1 file changed, 217 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi index fbaac4e42f25..54b52de232ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03c10.dtsi @@ -16,6 +16,9 @@ #define OX03C10_HDR_MODE OX03C10_HDR3_DCG_VS_12BIT #endif /* OX03C10_HDR_ENABLE */ +/* Multiple raw sensor link to RK ISP: 0 = disable, 1 = enable */ +#define MULTI_RAW_SENSOR_LINK_TO_ISP 1 + / { max96712_dphy0_osc: max96712-dphy0-oscillator { compatible = "fixed-clock"; @@ -159,6 +162,10 @@ serdes-local-device { status = "okay"; +#if MULTI_RAW_SENSOR_LINK_TO_ISP + remote-routing-to-isp = <1>; /* remote camera route to ISP */ +#endif + /* GMSL LINK config start */ gmsl-links { status = "okay"; @@ -523,6 +530,10 @@ /* port config start */ port { max96712_dphy0_cam0_out: endpoint { +#if MULTI_RAW_SENSOR_LINK_TO_ISP + remote-endpoint = <&mipi_lvds1_sditf_in>; +#endif + data-lanes = <1 2 3 4>; }; }; @@ -591,6 +602,10 @@ /* port config start */ port { max96712_dphy0_cam1_out: endpoint { +#if MULTI_RAW_SENSOR_LINK_TO_ISP + remote-endpoint = <&mipi_lvds1_sditf_vir1_in>; +#endif + data-lanes = <1 2 3 4>; }; }; @@ -659,6 +674,10 @@ /* port config start */ port { max96712_dphy0_cam2_out: endpoint { +#if MULTI_RAW_SENSOR_LINK_TO_ISP + remote-endpoint = <&mipi_lvds1_sditf_vir2_in>; +#endif + data-lanes = <1 2 3 4>; }; }; @@ -727,6 +746,10 @@ /* port config start */ port { max96712_dphy0_cam3_out: endpoint { +#if MULTI_RAW_SENSOR_LINK_TO_ISP + remote-endpoint = <&mipi_lvds1_sditf_vir3_in>; +#endif + data-lanes = <1 2 3 4>; }; }; @@ -772,6 +795,10 @@ &rkcif_mipi_lvds1 { status = "okay"; +#if MULTI_RAW_SENSOR_LINK_TO_ISP + camera-over-bridge; // serdes multi raw camera to isp +#endif + /* parameters for do cif reset detecting: * index0: monitor mode, 0 for idle, @@ -794,6 +821,130 @@ }; }; +#if MULTI_RAW_SENSOR_LINK_TO_ISP +&rkcif_mipi_lvds1_sditf { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_cam0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_vir0_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf_vir1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_cam1_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_vir1_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf_vir2 { + address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_cam2_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir2: endpoint { + remote-endpoint = <&isp_vir2_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf_vir3 { + address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir3_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_cam3_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds1_sditf_vir3: endpoint { + remote-endpoint = <&isp_vir3_in0>; + }; + }; + }; +}; +#endif /* MULTI_RAW_SENSOR_LINK_TO_ISP */ + &rkcif { status = "okay"; rockchip,android-usb-camerahal-enable; @@ -803,6 +954,72 @@ status = "okay"; }; +#if MULTI_RAW_SENSOR_LINK_TO_ISP +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + +&rkisp_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir1_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf_vir1>; + }; + }; +}; + +&rkisp_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir2_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf_vir2>; + }; + }; +}; + +&rkisp_vir3 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir3_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf_vir3>; + }; + }; +}; +#endif /* MULTI_RAW_SENSOR_LINK_TO_ISP */ + &pinctrl { max96712-dphy0 { max96712_dphy0_pwdn: max96712-dphy0-pwdn { From 96ffea5334a374e3b4d2bc8fbafeacaba669ac73 Mon Sep 17 00:00:00 2001 From: "hangyu.li" Date: Thu, 26 Jun 2025 14:24:21 +0800 Subject: [PATCH 17/25] ARM: configs: rv1126b-cvr add cvr configuration Configuration file generation method: make ARCH=arm mrproper make ARCH=arm rv1126b_defconfig cp .config rv1126b.config make ARCH=arm rv1126b_defconfig rv1126b-evb.config make ARCH=arm menuconfig ./scripts/diffconfig -m rv1126b.config .config > arch/arm/configs/rv1126b-cvr.config Signed-off-by: hangyu.li Change-Id: Ib5bcbd48db3308de57afc3e99ecc8591764d705a --- arch/arm/configs/rv1126b-cvr.config | 1091 +++++++++++++++++++++++++++ 1 file changed, 1091 insertions(+) create mode 100644 arch/arm/configs/rv1126b-cvr.config diff --git a/arch/arm/configs/rv1126b-cvr.config b/arch/arm/configs/rv1126b-cvr.config new file mode 100644 index 000000000000..d0022605523a --- /dev/null +++ b/arch/arm/configs/rv1126b-cvr.config @@ -0,0 +1,1091 @@ +CONFIG_CONFIGFS_FS=y +CONFIG_CRC16=y +CONFIG_CRYPTO=y +CONFIG_DEBUG_FS=y +CONFIG_ELF_CORE=y +CONFIG_EXFAT_FS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_EXT4_FS=y +CONFIG_EXTCON=y +CONFIG_FILE_LOCKING=y +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_MUX=y +CONFIG_INPUT=y +CONFIG_IPV6=m +CONFIG_JFFS2_FS=y +CONFIG_KCMP=y +CONFIG_KEYS=y +CONFIG_MMC=y +CONFIG_MSDOS_PARTITION=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_UBI=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NVMEM_SYSFS=y +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_ON_OOPS_VALUE=1 +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y +CONFIG_RK_CMA_PROCFS=y +CONFIG_RK_DMABUF_PROCFS=y +CONFIG_RK_MEMBLOCK_PROCFS=y +CONFIG_ROCKCHIP_DEBUG=y +CONFIG_ROCKCHIP_OPP=y +CONFIG_ROCKCHIP_RGA_PROC_FS=y +CONFIG_ROCKCHIP_VENDOR_STORAGE=y +CONFIG_SND_SOC_DUMMY_CODEC=y +CONFIG_SND_SOC_RK817=y +CONFIG_SND_SOC_RK_DSM=y +CONFIG_SND_SOC_ROCKCHIP_ASRC=y +CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SPI=y +CONFIG_USB_SUPPORT=y +CONFIG_VFAT_FS=y +CONFIG_VIDEOBUF2_DMA_SG=y +CONFIG_VIDEO_CAM_SLEEP_WAKEUP=y +CONFIG_VIDEO_GC2053=m +CONFIG_VIDEO_GC8613=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_IMX586=m +CONFIG_VIDEO_OS04A10=m +CONFIG_VIDEO_PS5458=m +# CONFIG_VIDEO_RK_IRCUT is not set +CONFIG_VIDEO_ROCKCHIP_FEC=y +CONFIG_VIDEO_SC200AI=m +CONFIG_VIDEO_SC3336=m +CONFIG_VIDEO_SC401AI=m +CONFIG_VIDEO_SC4336=m +CONFIG_VIDEO_SC450AI=m +CONFIG_VIDEO_SC530AI=m +CONFIG_VIDEO_SC635HAI=m +CONFIG_VIDEO_SC850SL=m +CONFIG_VIDEO_TECHPOINT=m +CONFIG_WIRELESS=y +CONFIG_WLAN=y +# CONFIG_6LOWPAN is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD3552R is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7293 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD74413R is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD8366 is not set +# CONFIG_AD8801 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_ADA4250 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADRF6780 is not set +# CONFIG_ADXL313_SPI is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL355_SPI is not set +# CONFIG_ADXL367_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_AFE4403 is not set +# CONFIG_AFS_FS is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_AS3935 is not set +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +# CONFIG_BCMDHD is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BMA220 is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_BMI088_ACCEL is not set +# CONFIG_BMI160_SPI is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_CEPH_FS is not set +CONFIG_CFG80211=m +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +# CONFIG_CFG80211_WEXT is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CIFS is not set +CONFIG_CLZ_TAB=y +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CODA_FS is not set +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CRYPTO_842 is not set +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ARIA is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S_ARM is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CFB=m +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +CONFIG_CRYPTO_CMAC=m +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_CTR=m +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_CURVE25519 is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_ROCKCHIP_CE=y +CONFIG_CRYPTO_DEV_ROCKCHIP_DEV=m +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_ECRDSA is not set +CONFIG_CRYPTO_ENGINE=m +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HCTR2 is not set +# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KEYWRAP is not set +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_AES=m +CONFIG_CRYPTO_LIB_ARC4=m +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_SHA256=m +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_OFB=m +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_ARM is not set +# CONFIG_CRYPTO_RMD160 is not set +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA1_ARM is not set +CONFIG_CRYPTO_SHA256=m +# CONFIG_CRYPTO_SHA256_ARM is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA512_ARM is not set +CONFIG_CRYPTO_SKCIPHER=m +CONFIG_CRYPTO_SKCIPHER2=y +# CONFIG_CRYPTO_SM2 is not set +CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_SM3_GENERIC is not set +CONFIG_CRYPTO_SM4=m +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_XTS=m +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_ZSTD=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_ECRYPT_FS is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_ENCX24J600 is not set +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EZX_PCAP is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +# CONFIG_FXLS8962AF_SPI is not set +# CONFIG_FXOS8700_SPI is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +CONFIG_GRACE_PERIOD=y +# CONFIG_GUP_TEST is not set +CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU=y +# CONFIG_HI8435 is not set +# CONFIG_HID is not set +# CONFIG_HID_PID is not set +# CONFIG_HISI_HIKEY_USB is not set +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set +# CONFIG_I2C_HID_OF_GOODIX is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_RK805_PWRKEY=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INV_ICM42600_SPI is not set +CONFIG_INV_ICM42670=y +CONFIG_INV_ICM42670_SPI=y +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_VTI is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_LZO is not set +# CONFIG_JFFS2_RTIME is not set +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_KEYBOARD_ADC=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_KS7010 is not set +# CONFIG_KS8851 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LMK04832 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_LOCK_EVENT_COUNTS is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2632 is not set +# CONFIG_LTC2688 is not set +# CONFIG_LTC2983 is not set +# CONFIG_LTE_GDM724X is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_MANAGER_SBS is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX11205 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX31856 is not set +# CONFIG_MAX31865 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3911 is not set +# CONFIG_MCP41010 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_RK806_SPI is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_QUEUE_DEPTH=1 +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MOST is not set +# CONFIG_MOXTET is not set +CONFIG_MPILIB=y +# CONFIG_MPL115_SPI is not set +# CONFIG_MSE102X is not set +CONFIG_MTD_BLKDEVS=y +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +CONFIG_MTD_NAND_BBT_USING_FLASH=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NAND_ATO=y +CONFIG_MTD_SPI_NAND_BIWIN=y +CONFIG_MTD_SPI_NAND_DEVICE_AUTOSELECT=y +CONFIG_MTD_SPI_NAND_DOSILICON=y +CONFIG_MTD_SPI_NAND_ESMT=y +CONFIG_MTD_SPI_NAND_ETRON=y +CONFIG_MTD_SPI_NAND_FMSH=y +CONFIG_MTD_SPI_NAND_FORESEE=y +CONFIG_MTD_SPI_NAND_GIGADEVICE=y +CONFIG_MTD_SPI_NAND_GSTO=y +CONFIG_MTD_SPI_NAND_HIKSEMI=y +CONFIG_MTD_SPI_NAND_HYF=y +CONFIG_MTD_SPI_NAND_JSC=y +CONFIG_MTD_SPI_NAND_MACRONIX=y +CONFIG_MTD_SPI_NAND_MICRON=y +CONFIG_MTD_SPI_NAND_PARAGON=y +CONFIG_MTD_SPI_NAND_SILICONGO=y +CONFIG_MTD_SPI_NAND_SKYHIGH=y +CONFIG_MTD_SPI_NAND_TOSHIBA=y +CONFIG_MTD_SPI_NAND_UNIM=y +CONFIG_MTD_SPI_NAND_WINBOND=y +CONFIG_MTD_SPI_NAND_XINCUN=y +CONFIG_MTD_SPI_NAND_XTX=y +CONFIG_MTD_SPI_NAND_ZBIT=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_ATMEL is not set +# CONFIG_MTD_SPI_NOR_BOYA is not set +# CONFIG_MTD_SPI_NOR_CATALYST is not set +# CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT is not set +# CONFIG_MTD_SPI_NOR_DOSILICON is not set +# CONFIG_MTD_SPI_NOR_EON is not set +# CONFIG_MTD_SPI_NOR_ESMT is not set +# CONFIG_MTD_SPI_NOR_EVERSPIN is not set +# CONFIG_MTD_SPI_NOR_FMSH is not set +# CONFIG_MTD_SPI_NOR_FUJITSU is not set +CONFIG_MTD_SPI_NOR_GIGADEVICE=y +# CONFIG_MTD_SPI_NOR_INTEL is not set +# CONFIG_MTD_SPI_NOR_ISSI is not set +CONFIG_MTD_SPI_NOR_MACRONIX=y +CONFIG_MTD_SPI_NOR_MISC=y +# CONFIG_MTD_SPI_NOR_NORMEM is not set +# CONFIG_MTD_SPI_NOR_PUYA is not set +# CONFIG_MTD_SPI_NOR_SPANSION is not set +# CONFIG_MTD_SPI_NOR_SST is not set +# CONFIG_MTD_SPI_NOR_STMICRO is not set +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPI_NOR_WINBOND=y +# CONFIG_MTD_SPI_NOR_XILINX is not set +# CONFIG_MTD_SPI_NOR_XMC is not set +# CONFIG_MTD_SPI_NOR_XTX is not set +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_NETDEVSIM is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NFSD is not set +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +CONFIG_NFS_FS=y +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NVME_TARGET is not set +# CONFIG_OCFS2_FS is not set +CONFIG_OID_REGISTRY=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set +# CONFIG_PI433 is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PLFXLC is not set +# CONFIG_PRINTK_INDEX is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_PWRSEQ_EMMC is not set +CONFIG_PWRSEQ_SIMPLE=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_R8188EU is not set +# CONFIG_R8712U is not set +# CONFIG_RC_CORE is not set +CONFIG_REGMAP_SPI=y +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_RMI4_CORE is not set +# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set +CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y +# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set +# CONFIG_ROCKCHIP_REMOTECTL is not set +CONFIG_ROCKCHIP_RGA_DEBUGGER=y +# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set +# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTL8723BS is not set +# CONFIG_RTLLIB is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SENSOR_DEVICE is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SGL_ALLOC=y +# CONFIG_SHRINKER_DEBUG is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set +# CONFIG_SMB_SERVER is not set +# CONFIG_SND_BCD2000 is not set +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y +# CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE is not set +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +CONFIG_SPI_ROCKCHIP=y +# CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI is not set +# CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI is not set +# CONFIG_SPI_ROCKCHIP_MISCDEV is not set +CONFIG_SPI_ROCKCHIP_SFC=y +# CONFIG_SPI_ROCKCHIP_SLAVE is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +CONFIG_SUNRPC_GSS=y +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_9551R is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5 is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELAN5515 is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FT5726 is not set +# CONFIG_TOUCHSCREEN_FTS is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GSL3673 is not set +# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set +# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set +CONFIG_TOUCHSCREEN_GT1X=y +# CONFIG_TOUCHSCREEN_GT9XX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set +# CONFIG_TOUCHSCREEN_HYN is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set +# CONFIG_TOUCHSCREEN_IMAGIS is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PARADE is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_W9013 is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +# CONFIG_TRUSTED_KEYS is not set +# CONFIG_TYPEC is not set +# CONFIG_UBIFS_ATIME_SUPPORT is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +# CONFIG_UBIFS_FS_AUTHENTICATION is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_ZSTD is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_USB=y +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_AUDIO is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=y +CONFIG_USB_CONFIGFS=y +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +# CONFIG_USB_CONFIGFS_EEM is not set +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_UVC=y +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_OBEX is not set +# CONFIG_USB_CONFIGFS_RNDIS is not set +# CONFIG_USB_CONFIGFS_SERIAL is not set +CONFIG_USB_CONFIGFS_UEVENT=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_OF_SIMPLE=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +CONFIG_USB_F_FS=y +CONFIG_USB_F_HID=y +CONFIG_USB_F_UAC1=y +CONFIG_USB_F_UAC2=y +CONFIG_USB_F_UVC=y +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=500 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_HID is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LEGOTOWER is not set +CONFIG_USB_LIBCOMPOSITE=y +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3420_UDC is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAW_GADGET is not set +CONFIG_USB_ROLE_SWITCH=y +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_ULPI_BUS is not set +CONFIG_USB_U_AUDIO=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZERO is not set +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_ROCKCHIP_PREISP is not set +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_VT6656 is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +# CONFIG_WFX is not set +CONFIG_WIFI_BUILD_MODULE=y +# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set +# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +# CONFIG_WLAN_VENDOR_ATH is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +CONFIG_WL_ROCKCHIP=m +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_XILLYUSB is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +# CONFIG_ZRAM is not set +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y From 1eb37c3f47cbb5c65c34c986c6a29683add76671 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 24 Jun 2025 11:27:34 +0800 Subject: [PATCH 18/25] dt-bindings: display: add Fast Boot Display mode define Signed-off-by: Sandy Huang Change-Id: I22005163ec8d1b5f154fa74345ee444e894a28c5 --- include/dt-bindings/display/rockchip_vop.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/dt-bindings/display/rockchip_vop.h b/include/dt-bindings/display/rockchip_vop.h index 3761072e6b11..87cd94de08e5 100644 --- a/include/dt-bindings/display/rockchip_vop.h +++ b/include/dt-bindings/display/rockchip_vop.h @@ -28,6 +28,22 @@ #define ROCKCHIP_VOP2_PHY_ID_INVALID -1 +/* + * FBD: Fast Boot Display + * + * ROCKCHIP_DRM_FBD_FROM_UBOOT: + * show logo.bmp from uboot and show logo_kernel.bmp after enter kernel; + * ROCKCHIP_DRM_FBD_FROM_UBOOT_TO_RTOS: + * crtc/connector/panel will be init at uboot, and update plane at rtos; + * ROCKCHIP_DRM_FBD_FROM_RTOS: + * crtc/connector/panel will be init at rtos, uboot no need to do any hardware + * config, but need to pass the logic state to kernel to ensure pd/clk/drm + * state is continuous. + */ +#define ROCKCHIP_DRM_FBD_FROM_UBOOT 0 +#define ROCKCHIP_DRM_FBD_FROM_UBOOT_TO_RTOS 1 +#define ROCKCHIP_DRM_FBD_FROM_RTOS 2 + /* mcu_data[23:0] */ #define ROCKCHIP_MCU_DATA_MAP_DATA_1x24 0 /* From fc46321d50a7634e782bc8a4dfeb3a19649597d7 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Wed, 30 Apr 2025 10:58:59 +0800 Subject: [PATCH 19/25] drm/rockchip: vop2: add support reserved plane display reserved plane display will be enabled as following config at dts, then the reserved plane will be update by other OS, and the reverved plane zpos is always at the top of other planes. example: &vp1 { rockchip,drm-fbd-mode = ; rockchip,reserved-plane = ; }; If userspace want to exit from reserved plane, you can set the property: RESERVED_PLANE_MASK to 0, and the reverved plane will become the normal plane. Signed-off-by: Sandy Huang Change-Id: I34e7a7470e2f6685aea5a228b58bdb84eb9c1e92 --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 111 ++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 69 ++++++++++-- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + 4 files changed, 169 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index f39b9748ca3d..87243ee72c93 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -914,6 +914,7 @@ struct vop2_win_regs { struct vop2_video_port_regs { struct vop_reg cfg_done; + struct vop_reg sys_cfg_done; struct vop_reg overlay_mode; struct vop_reg dsp_background; struct vop_reg port_mux; @@ -1234,6 +1235,7 @@ struct vop2_win_data { uint8_t axi_uv_id; uint8_t possible_vp_mask; uint8_t dci_rid_id; + uint8_t reg_done_bit; uint32_t base; enum drm_plane_type type; @@ -1464,6 +1466,7 @@ struct vop_data { struct vop2_ctrl { struct vop_reg cfg_done_en; struct vop_reg wb_cfg_done; + struct vop_reg win_cfg_done; struct vop_reg auto_gating_en; struct vop_reg aclk_pre_auto_gating_en; struct vop_reg dma_finish_mode; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 2e13cd9dbccd..3bfd50b3d342 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -458,6 +458,7 @@ struct vop2_win { uint8_t axi_uv_id; uint8_t scale_engine_num; uint8_t possible_vp_mask; + uint8_t reg_done_bit; enum drm_plane_type type; unsigned int max_upscale_factor; unsigned int max_downscale_factor; @@ -781,6 +782,11 @@ struct vop2_video_port { * @plane_mask_prop: plane mask interaction with userspace */ struct drm_property *plane_mask_prop; + /** + * @reserved_plane_mask_prop: reserved plane mask interaction with userspace + */ + struct drm_property *reserved_plane_mask_prop; + /** * @feature_prop: crtc feature interaction with userspace */ @@ -835,6 +841,12 @@ struct vop2_video_port { */ int primary_plane_phy_id; + /** + * @reserved_plane_phy_id: reserved plane is used by third party OS, + * reserved plane is always on the top of overlay. + */ + int reserved_plane_phy_id; + struct post_acm acm_info; struct post_csc csc_info; @@ -872,6 +884,11 @@ struct vop2_video_port { * we configure whether sharp is disabled in dts */ bool sharp_disabled; + + /** + * @win_cfg_done_bits: control reg done bit for each win + */ + u32 win_cfg_done_bits; }; struct vop2_extend_pll { @@ -956,6 +973,7 @@ struct vop2 { unsigned long aclk_current_freq; enum rockchip_drm_vop_aclk_mode aclk_mode; bool merge_irq; + bool enable_reserved_plane; const struct vop2_data *data; /* Number of win that registered as plane, @@ -1929,8 +1947,15 @@ static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc) val |= BIT(vp_data->splice_vp_id) | (BIT(vp_data->splice_vp_id) << 16); rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val); + if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + val = vp->win_cfg_done_bits; + VOP_CTRL_SET(vop2, win_cfg_done, val); + VOP_CTRL_SET(vop2, wb_cfg_done, 1); + VOP_MODULE_SET(vop2, vp, sys_cfg_done, 1); + } else { + vop2_writel(vop2, 0, val); + } - vop2_writel(vop2, 0, val); } static inline void vop2_wb_cfg_done(struct vop2_video_port *vp) @@ -2201,6 +2226,8 @@ static void vop2_win_multi_area_disable(struct vop2_win *parent) static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win) { struct vop2 *vop2 = win->vop2; + struct vop2_video_port *vp = NULL; + uint32_t vp_id; /* Disable the right splice win */ if (win->splice_win && !skip_splice_win) { @@ -2257,6 +2284,15 @@ static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win) win->pd->vp_mask &= ~win->vp_mask; } } + + vp_id = ffs(win->vp_mask) - 1; + if (vp_id >= ROCKCHIP_MAX_CRTC) { + DRM_ERROR("Unsupported vp_id: %d\n", vp_id); + return; + } + vp = &vop2->vps[vp_id]; + if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) + vp->win_cfg_done_bits |= BIT(win->reg_done_bit); } if (win->left_win && win->splice_mode_right) { @@ -7122,6 +7158,7 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1); VOP_CLUSTER_SET(vop2, win, dma_stride_4k_disable, 1); } + vp->win_cfg_done_bits |= BIT(win->reg_done_bit); spin_unlock(&vop2->reg_lock); } @@ -12142,10 +12179,18 @@ static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp, struct vop2_win *win; u32 layer_sel = 0; u8 layer_sel_id; - u8 layer_sel_none = 0xff; + u8 layer_sel_none = 0xf; int i; + int nr_layers = vop2->data->nr_layers; - for (i = 0; i < vop2->data->nr_layers; i++) { + if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + /* set reserved layer at the top layer */ + nr_layers -= 1; + win = vop2_find_win_by_phys_id(vop2, vp->reserved_plane_phy_id); + layer_sel = win->layer_sel_id[vp->id] << nr_layers * 4; + } + + for (i = 0; i < nr_layers; i++) { layer_sel_id = layer_sel_none; if (i < vp->nr_layers) { zpos = &vop2_zpos[i]; @@ -13476,6 +13521,7 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_stat spin_lock_irqsave(&vop2->irq_lock, flags); vop2_wb_commit(crtc); vop2_cfg_done(crtc); + vp->win_cfg_done_bits = 0; if (vp->mcu_timing.mcu_pix_total) VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0); @@ -13764,6 +13810,11 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc, return 0; } + if (property == vp->reserved_plane_mask_prop) { + *val = BIT(vp->reserved_plane_phy_id); + return 0; + } + if (property == vp->hdr_ext_data_prop) { *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0; return 0; @@ -13805,6 +13856,7 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc, struct drm_mode_config *mode_config = &drm_dev->mode_config; struct vop2_video_port *vp = to_vop2_video_port(crtc); struct vop2 *vop2 = vp->vop2; + const struct vop2_data *vop2_data = vop2->data; bool replaced = false; int ret; @@ -13894,6 +13946,14 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc, return 0; } + if (property == vp->reserved_plane_mask_prop) { + if (!val || hweight32(val) > 1 || !(val & vop2_data->plane_mask_base)) + vp->reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID; + else + vp->reserved_plane_phy_id = ilog2(val); + return 0; + } + if (property == vp->hdr_ext_data_prop) { ret = vop2_atomic_replace_property_blob_from_id(drm_dev, &vcstate->hdr_ext_data, @@ -14798,6 +14858,38 @@ static int vop2_gamma_init(struct vop2 *vop2) return 0; } +static int vop2_crtc_create_reserved_plane_mask_property(struct vop2 *vop2, + struct drm_crtc *crtc) +{ + struct drm_property *prop; + struct vop2_video_port *vp = to_vop2_video_port(crtc); + + static const struct drm_prop_enum_list props[] = { + { ROCKCHIP_VOP2_CLUSTER0, "Cluster0" }, + { ROCKCHIP_VOP2_CLUSTER1, "Cluster1" }, + { ROCKCHIP_VOP2_ESMART0, "Esmart0" }, + { ROCKCHIP_VOP2_ESMART1, "Esmart1" }, + { ROCKCHIP_VOP2_SMART0, "Smart0" }, + { ROCKCHIP_VOP2_SMART1, "Smart1" }, + { ROCKCHIP_VOP2_CLUSTER2, "Cluster2" }, + { ROCKCHIP_VOP2_CLUSTER3, "Cluster3" }, + { ROCKCHIP_VOP2_ESMART2, "Esmart2" }, + { ROCKCHIP_VOP2_ESMART3, "Esmart3" }, + }; + + prop = drm_property_create_bitmask(vop2->drm_dev, 0, "RESERVED_PLANE_MASK", + props, ARRAY_SIZE(props), 0xffffffff); + if (!prop) { + DRM_DEV_ERROR(vop2->dev, "create reserved_plane_mask prop for vp%d failed\n", vp->id); + return -ENOMEM; + } + + vp->reserved_plane_mask_prop = prop; + drm_object_attach_property(&crtc->base, vp->reserved_plane_mask_prop, BIT(vp->reserved_plane_phy_id)); + + return 0; +} + static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2, struct drm_crtc *crtc, uint32_t plane_mask) @@ -15246,6 +15338,10 @@ static int vop2_create_crtc(struct vop2 *vop2, uint8_t enabled_vp_mask) */ if (plane_mask && !is_vop3(vop2)) vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask); + + if (vp->reserved_plane_phy_id != ROCKCHIP_VOP2_PHY_ID_INVALID) + vop2_crtc_create_reserved_plane_mask_property(vop2, crtc); + vop2_crtc_create_feature_property(vop2, crtc); vop2_crtc_create_vrr_property(vop2, crtc); @@ -15477,6 +15573,7 @@ static int vop2_win_init(struct vop2 *vop2) win->axi_yrgb_id = win_data->axi_yrgb_id; win->axi_uv_id = win_data->axi_uv_id; win->possible_vp_mask = win_data->possible_vp_mask; + win->reg_done_bit = win_data->reg_done_bit; if (win_data->pd_id) win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id); @@ -16316,6 +16413,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) for_each_child_of_node(vop_out_node, child) { u32 plane_mask = 0; u32 primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID; + u32 reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID; u32 vp_id = 0; u32 val = 0; @@ -16330,7 +16428,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) vop2->vps[vp_id].primary_plane_phy_id = primary_plane_phy_id; else vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID; - + if (!of_property_read_u32(child, "rockchip,reserved-plane", &reserved_plane_phy_id)) { + vop2->vps[vp_id].reserved_plane_phy_id = reserved_plane_phy_id; + vop2->enable_reserved_plane = true; + } else { + vop2->vps[vp_id].reserved_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID; + } vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable"); ret = of_clk_set_defaults(child, false); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 2c4957ad8100..b684cefbb2ae 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -1022,7 +1022,8 @@ static const struct vop2_wb_data rk3576_vop_wb_data = { }; static const struct vop2_video_port_regs rk3528_vop_vp0_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4), .overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0), @@ -1100,7 +1101,8 @@ static const struct vop2_video_port_regs rk3528_vop_vp0_regs = { }; static const struct vop2_video_port_regs rk3528_vop_vp1_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5), .overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0), @@ -1236,7 +1238,8 @@ static const struct vop2_video_port_data rk3528_vop_video_ports[] = { }; static const struct vop2_video_port_regs rk3562_vop_vp0_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4), .overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0), @@ -1326,6 +1329,7 @@ static const struct vop2_video_port_data rk3562_vop_video_ports[] = { static const struct vop2_video_port_regs rk3568_vop_vp0_regs = { .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 4), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0x3fffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0), @@ -1413,6 +1417,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = { static const struct vop2_video_port_regs rk3568_vop_vp1_regs = { .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), + .sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 5), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1), .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0x3fffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4), @@ -1467,6 +1472,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = { static const struct vop2_video_port_regs rk3568_vop_vp2_regs = { .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2), + .sys_cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 6), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0x3fffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8), @@ -1559,7 +1565,8 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = { }; static const struct vop2_video_port_regs rk3576_vop_vp0_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4), .overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0), @@ -1678,7 +1685,8 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = { }; static const struct vop2_video_port_regs rk3576_vop_vp1_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5), .overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0), @@ -1769,7 +1777,8 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = { }; static const struct vop2_video_port_regs rk3576_vop_vp2_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 2), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 6), .overlay_mode = VOP_REG(RK3576_OVL_PORT2_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0), .out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0), @@ -1935,7 +1944,8 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = { }; static const struct vop2_video_port_regs rk3588_vop_vp0_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 0), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 4), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0), .dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0), @@ -2040,7 +2050,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = { * same eotf curve with VP1. */ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 1), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 5), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1), .dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4), @@ -2132,7 +2143,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = { }; static const struct vop2_video_port_regs rk3588_vop_vp2_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 2), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 6), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8), @@ -2195,7 +2207,8 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = { }; static const struct vop2_video_port_regs rk3588_vop_vp3_regs = { - .cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 3), + .cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 3), + .sys_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 7), .overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 3), .port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 12), .dsp_background = VOP_REG(RK3588_VP3_DSP_BG, 0xffffffff, 0), @@ -3143,6 +3156,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 4, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3172,6 +3186,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x08, .axi_uv_id = 0x09, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 5, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3201,6 +3216,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), + .reg_done_bit = 6, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3230,6 +3246,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1), + .reg_done_bit = 7, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3256,6 +3273,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x02, .axi_uv_id = 0x03, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 0, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 27, 21 }, @@ -3282,6 +3300,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_yrgb_id = 0x04, .axi_uv_id = 0x05, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 0, .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3325,6 +3344,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_yrgb_id = 0x02, .axi_uv_id = 0x03, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 4, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3352,6 +3372,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_yrgb_id = 0x04, .axi_uv_id = 0x05, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 5, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3379,6 +3400,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 6, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3406,6 +3428,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_yrgb_id = 0x08, .axi_uv_id = 0x0d, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), + .reg_done_bit = 7, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3801,6 +3824,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x10, .axi_uv_id = 0x11, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2), + .reg_done_bit = 4, .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH, @@ -3830,6 +3854,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x12, .axi_uv_id = 0x13, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2), + .reg_done_bit = 5, .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3859,6 +3884,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2), + .reg_done_bit = 6, .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3888,6 +3914,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2), + .reg_done_bit = 7, .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3914,6 +3941,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_uv_id = 0x0b, .dci_rid_id = 0x4,/* dci axi id length is 4 bits */ .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), + .reg_done_bit = 0, .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3940,6 +3968,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), + .reg_done_bit = 0, .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3966,6 +3995,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */ + .reg_done_bit = 1, .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3991,6 +4021,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x08, .axi_uv_id = 0x09, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */ + .reg_done_bit = 1, .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -4288,6 +4319,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 3, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 0, .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29, 4, 35, 3, 5 }, @@ -4314,6 +4346,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 5, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 0, .max_upscale_factor = 4, .max_downscale_factor = 4, .type = DRM_PLANE_TYPE_OVERLAY, @@ -4342,6 +4375,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .type = DRM_PLANE_TYPE_OVERLAY, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 1, .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29, 4, 35, 3, 5 }, @@ -4368,6 +4402,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 9, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 1, .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4396,6 +4431,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 3, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 2, .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29, 4, 35, 3, 5 }, @@ -4422,6 +4458,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 5, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 2, .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4449,6 +4486,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 7, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 3, .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29, 4, 35, 3, 5 }, @@ -4475,6 +4513,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 9, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 3, .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4503,6 +4542,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 0x0b, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 4, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48, 23, 54, 22, 24 }, @@ -4533,6 +4573,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 0x0b, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 6, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48, 23, 54, 22, 24 }, @@ -4562,6 +4603,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 0x01, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 5, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48, 23, 54, 22, 24 }, @@ -4591,6 +4633,7 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_uv_id = 0x0d, .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), + .reg_done_bit = 7, .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48, 23, 54, 22, 24 }, @@ -4599,8 +4642,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { }; static const struct vop2_ctrl rk3528_vop_ctrl = { - .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15), + .cfg_done_en = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 15), .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14), + .win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0), .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31), .aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7), .if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28), @@ -4638,6 +4682,7 @@ static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = { static const struct vop2_ctrl rk3562_vop_ctrl = { .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15), .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14), + .win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0), .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31), .aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7), .if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28), @@ -4748,6 +4793,7 @@ static const struct vop2_ctrl rk3576_vop_ctrl = { .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15), .reg_done_frm = VOP_REG_MASK(RK3576_SYS_PORT_CTRL_IMD, 0x7, 0), .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14), + .win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0), .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31), .aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7), .version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16), @@ -4882,6 +4928,7 @@ static const struct vop_grf_ctrl rk3588_vo1_grf_ctrl = { static const struct vop2_ctrl rk3588_vop_ctrl = { .cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15), .wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14), + .win_cfg_done = VOP_REG_MASK(RK3588_SYS_WIN_REG_CFG_DONE, 0xffffffff, 0), .auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31), .dma_finish_mode = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x3, 0), .axi_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 2), diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index fa58867b243e..0e92d434aa64 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1064,6 +1064,7 @@ #define RK3568_VOP2_GLB_CFG_DONE_EN BIT(15) #define RK3568_VERSION_INFO 0x004 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 +#define RK3588_SYS_WIN_REG_CFG_DONE 0x00c #define RK3576_SYS_AXI_HURRY_CTRL0_IMD 0x014 #define RK3576_SYS_AXI_HURRY_CTRL1_IMD 0x018 #define RK3576_SYS_MMU_CTRL_IMD 0x020 From 2d33531068480ee893fde48de2fd3074acc40ba5 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 10 Jun 2025 16:40:53 +0800 Subject: [PATCH 20/25] drm/rockchip: vop2: use rkiommu 1.0 for rk3576 reserved plane mode reserved plane mode will enable iommu bypass for rtos reserved plane display, but rkiommu 2.0 can't support iommu bypass function, so use rkiommu 1.0 at reserved plane mode by default, others will use rkiommu 2.0 by default. Signed-off-by: Sandy Huang Change-Id: I68f2ae66e4e0d7eec45264c39a7f23deab01c8eb --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 3bfd50b3d342..d57bf7c676a1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4712,8 +4712,14 @@ static void vop2_initial(struct drm_crtc *crtc) vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true); if (vop2->version == VOP_VERSION_RK3576) { - /* Default use rkiommu 2.0 for axi0 */ - VOP_CTRL_SET(vop2, rkmmu_v2_en, 1); + /* reserved plane mode will enable iommu bypass for rtos reserved plane display, + * but rkiommu 2.0 can't support iommu bypass function, so use rkiommu 1.0 + * at reserved plane mode by default, others will use rkiommu 2.0 by default. + */ + if (vop2->enable_reserved_plane) + VOP_CTRL_SET(vop2, rkmmu_v2_en, 0); + else /* Default use rkiommu 2.0 for axi0 */ + VOP_CTRL_SET(vop2, rkmmu_v2_en, 1); if (vop2->merge_irq == true) VOP_CTRL_SET(vop2, vp_intr_merge_en, 1); From 9226dd6523528d0151f54d72129dd37000464c5a Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Sat, 21 Jun 2025 11:02:04 +0800 Subject: [PATCH 21/25] media: i2c: os12d40 fixes error bayer pattern when mirror/flip change Change-Id: I423d30c146baa934b0b060ef8618138de6910339 Signed-off-by: Zefa Chen --- drivers/media/i2c/os12d40.c | 79 ++++++++++++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/os12d40.c b/drivers/media/i2c/os12d40.c index 72ae0c02be5d..7eb784d0ed80 100644 --- a/drivers/media/i2c/os12d40.c +++ b/drivers/media/i2c/os12d40.c @@ -73,6 +73,16 @@ #define ANALOG_GAIN_DEFAULT 1024 #define OS12D40_REG_GROUP 0x3208 +#define OS12D40_GROUP_UPDATE_START_DATA 0x00 +#define OS12D40_GROUP_UPDATE_END_DATA 0x10 +#define OS12D40_GROUP_UPDATE_LAUNCH 0xA0 + +#define OS12D40_GROUP1_UPDATE_START_DATA 0x01 +#define OS12D40_GROUP1_UPDATE_END_DATA 0x11 +#define OS12D40_GROUP1_UPDATE_LAUNCH 0xA1 + +#define OS12D40_REG_XOFFSET_L 0x3811 +#define OS12D40_REG_YOFFSET_L 0x3813 #define OS12D40_REG_FLIP 0x3820 #define OS12D40_REG_MIRROR 0x3821 #define MIRROR_BIT_MASK BIT(2) @@ -1931,7 +1941,7 @@ static const struct regval os12d40_2256x1256_regs_4lane[] = { static const struct os12d40_mode supported_modes_4lane[] = { { - .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10, + .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, .width = 2256, .height = 1256, .max_fps = { @@ -2774,6 +2784,7 @@ static int os12d40_set_ctrl(struct v4l2_ctrl *ctrl) int ret = 0; u32 again = 0; u32 dgain = 0; + u32 offset = 0; /* Propagate change of current control to all related controls */ switch (ctrl->id) { @@ -2833,25 +2844,81 @@ static int os12d40_set_ctrl(struct v4l2_ctrl *ctrl) ret = os12d40_read_reg(os12d40->client, OS12D40_REG_MIRROR, OS12D40_REG_VALUE_08BIT, &val); - if (ctrl->val) - val |= MIRROR_BIT_MASK; - else + if (ctrl->val) { val &= ~MIRROR_BIT_MASK; + if (os12d40->cur_mode->width == 2256) + offset = 0x22; + else + offset = 0x40; + } else { + val |= MIRROR_BIT_MASK; + if (os12d40->cur_mode->width == 2256) + offset = 0x21; + else +#if USE_4_CELL + offset = 0x3e; +#else + offset = 0x3f; +#endif + } + if (os12d40->streaming) + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP_UPDATE_START_DATA); + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_XOFFSET_L, + OS12D40_REG_VALUE_08BIT, + offset); ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_MIRROR, OS12D40_REG_VALUE_08BIT, val); + if (os12d40->streaming) { + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP_UPDATE_END_DATA); + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP_UPDATE_LAUNCH); + } break; case V4L2_CID_VFLIP: ret = os12d40_read_reg(os12d40->client, OS12D40_REG_FLIP, OS12D40_REG_VALUE_08BIT, &val); - if (ctrl->val) + if (ctrl->val) { val |= FLIP_BIT_MASK; - else + if (os12d40->cur_mode->width == 2256) + offset = 0x05; + else +#if USE_4_CELL + offset = 0x06; +#else + offset = 0x07; +#endif + } else { val &= ~FLIP_BIT_MASK; + if (os12d40->cur_mode->width == 2256) + offset = 0x04; + else + offset = 0x08; + } + if (os12d40->streaming) + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP1_UPDATE_START_DATA); + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_YOFFSET_L, + OS12D40_REG_VALUE_08BIT, + offset); ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_FLIP, OS12D40_REG_VALUE_08BIT, val); + if (os12d40->streaming) { + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP1_UPDATE_END_DATA); + ret |= os12d40_write_reg(os12d40->client, OS12D40_REG_GROUP, + OS12D40_REG_VALUE_08BIT, + OS12D40_GROUP1_UPDATE_LAUNCH); + } break; default: dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", From 32383822b45a3a4ff2b66ff808145e5da90492a0 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 9 Jun 2025 15:25:30 +0800 Subject: [PATCH 22/25] arm64: dts: rockchip: rk3576: remove unnecessary references to rkcif_mmu Change-Id: I7381c1ec02633dec28c4349114cddc7081225989 Signed-off-by: Zefa Chen --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 1ce7b608be9d..c1e0e7e525be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1444,7 +1444,6 @@ rkcif_dvp: rkcif-dvp { compatible = "rockchip,rkcif-dvp"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -1457,7 +1456,6 @@ rkcif_mipi_lvds: rkcif-mipi-lvds { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -1488,7 +1486,6 @@ rkcif_mipi_lvds1: rkcif-mipi-lvds1 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -1519,7 +1516,6 @@ rkcif_mipi_lvds2: rkcif-mipi-lvds2 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -1550,7 +1546,6 @@ rkcif_mipi_lvds3: rkcif-mipi-lvds3 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -1581,7 +1576,6 @@ rkcif_mipi_lvds4: rkcif-mipi-lvds4 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; From d04f7171f7ed64f42c5842c2439014a2010f2f7a Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 9 Jun 2025 15:32:17 +0800 Subject: [PATCH 23/25] arm64: dts: rockchip: rk3588: remove unnecessary references to rkcif_mmu Change-Id: I39484b36cd98959c5aa5bc1eee051f7e0dee8bd8 Signed-off-by: Zefa Chen --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 523cfa1d70bb..e0f96ab2e0da 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -2509,7 +2509,6 @@ rkcif_dvp: rkcif-dvp { compatible = "rockchip,rkcif-dvp"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2522,7 +2521,6 @@ rkcif_mipi_lvds: rkcif-mipi-lvds { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2553,7 +2551,6 @@ rkcif_mipi_lvds1: rkcif-mipi-lvds1 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2584,7 +2581,6 @@ rkcif_mipi_lvds2: rkcif-mipi-lvds2 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2615,7 +2611,6 @@ rkcif_mipi_lvds3: rkcif-mipi-lvds3 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2646,7 +2641,6 @@ rkcif_mipi_lvds4: rkcif-mipi-lvds4 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; @@ -2677,7 +2671,6 @@ rkcif_mipi_lvds5: rkcif-mipi-lvds5 { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <&rkcif>; - iommus = <&rkcif_mmu>; status = "disabled"; }; From cf902d807ced0751171f07488a200ee4ec25305e Mon Sep 17 00:00:00 2001 From: Jian zheng Date: Tue, 24 Jun 2025 09:39:11 +0800 Subject: [PATCH 24/25] ARM: configs: add rv1126b cvr fastboot configuration Configuration file generation method: make ARCH=arm mrproper make ARCH=arm rv1126b_defconfig cp .config rv1126b.config make ARCH=arm rv1126b_defconfig rv1126b-fastboot.config make ARCH=arm menuconfig ./scripts/diffconfig -m rv1126b.config .config > arch/arm/configs/rv1126b-cvr-fastboot.config Signed-off-by: Jian zheng Change-Id: I3933bcc64814b0a416fd4f9539fe9f0f52a26261 --- arch/arm/configs/rv1126b-cvr-fastboot.config | 1126 ++++++++++++++++++ 1 file changed, 1126 insertions(+) create mode 100644 arch/arm/configs/rv1126b-cvr-fastboot.config diff --git a/arch/arm/configs/rv1126b-cvr-fastboot.config b/arch/arm/configs/rv1126b-cvr-fastboot.config new file mode 100644 index 000000000000..51ac619083ea --- /dev/null +++ b/arch/arm/configs/rv1126b-cvr-fastboot.config @@ -0,0 +1,1126 @@ +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CONFIGFS_FS=m +CONFIG_CRC16=y +CONFIG_CRYPTO=y +CONFIG_DAX=y +CONFIG_DRM=y +CONFIG_ELF_CORE=y +CONFIG_EROFS_FS=y +CONFIG_EXT4_FS=m +CONFIG_EXTCON=y +CONFIG_FILE_LOCKING=y +CONFIG_INPUT=y +CONFIG_JFFS2_FS=y +CONFIG_KCMP=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_LIBCRC32C=y +CONFIG_MMC=y +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MTD_BLOCK=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m +CONFIG_RK_DMABUF_PROCFS=y +CONFIG_ROCKCHIP_DVBM=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_ROCKCHIP_MULTI_RGA=y +CONFIG_ROCKCHIP_OPP=y +CONFIG_ROCKCHIP_RAMDISK=y +CONFIG_ROCKCHIP_RGA_PROC_FS=y +CONFIG_ROCKCHIP_THUNDER_BOOT=y +CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y +CONFIG_ROCKCHIP_VENDOR_STORAGE=m +# CONFIG_SLUB_SYSFS is not set +# CONFIG_SND_SIMPLE_CARD is not set +CONFIG_SND_SOC_DUMMY_CODEC=m +CONFIG_SND_SOC_RK_DSM=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_ASRC=m +CONFIG_SND_SOC_ROCKCHIP_PDM_V2=m +CONFIG_SND_SOC_ROCKCHIP_SAI=m +CONFIG_SPI=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_USB_SUPPORT=y +CONFIG_VFAT_FS=m +CONFIG_VIDEOBUF2_DMA_SG=m +# CONFIG_VIDEO_RK_IRCUT is not set +CONFIG_VIDEO_ROCKCHIP_AIISP=y +CONFIG_VIDEO_ROCKCHIP_AVSP=y +CONFIG_VIDEO_ROCKCHIP_CIF=y +CONFIG_VIDEO_ROCKCHIP_FEC=y +CONFIG_VIDEO_ROCKCHIP_ISP=y +CONFIG_VIDEO_ROCKCHIP_VPSS=y +CONFIG_VIDEO_SC200AI=y +CONFIG_VIDEO_SC450AI=y +CONFIG_VIDEO_SC850SL=y +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD3552R is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7293 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD74413R is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD8366 is not set +# CONFIG_AD8801 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_ADA4250 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADRF6780 is not set +# CONFIG_ADXL313_SPI is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL355_SPI is not set +# CONFIG_ADXL367_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_AFE4403 is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_AS3935 is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BMA220 is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_BMI088_ACCEL is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_CHARGER_BQ24190 is not set +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_TI is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ARIA is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S_ARM is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_HCTR2 is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_UTILS=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_ARM is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA256_ARM is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA512_ARM is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_ZSTD is not set +# CONFIG_DLM is not set +# CONFIG_DM9051 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_ARMADA is not set +CONFIG_DRM_BRIDGE=y +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_DP is not set +CONFIG_DRM_DW_MIPI_DSI=y +# CONFIG_DRM_EDID is not set +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_FSL_DCU is not set +CONFIG_DRM_GEM_DMA_HELPER=y +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_SIL164 is not set +CONFIG_DRM_IGNORE_IOTCL_PERMIT=y +# CONFIG_DRM_ITE_IT6161 is not set +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_ITE_IT66121 is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_KOMEDA is not set +# CONFIG_DRM_LEGACY is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_MAXIM_MAX96745 is not set +# CONFIG_DRM_MAXIM_MAX96755F is not set +# CONFIG_DRM_MCDE is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_NOMODESET=y +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_OMAP is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set +# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set +# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SIMPLE_OF_ONLY=y +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set +# CONFIG_DRM_RK1000_TVE is not set +CONFIG_DRM_ROCKCHIP=y +# CONFIG_DRM_ROCKCHIP_VKMS is not set +# CONFIG_DRM_ROHM_BU18XL82 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SIMPLEDRM is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_STI is not set +# CONFIG_DRM_STM is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TVE200 is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_EROFS_FS_DEBUG is not set +# CONFIG_EROFS_FS_XATTR is not set +# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EZX_PCAP is not set +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="cp936" +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_FAT_FS=m +CONFIG_FB_CMDLINE=y +CONFIG_FS_DAX=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=m +# CONFIG_FXLS8962AF_SPI is not set +# CONFIG_FXOS8700_SPI is not set +CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_HI8435 is not set +CONFIG_HID=m +# CONFIG_HIDRAW is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_ALPS is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +CONFIG_HID_GENERIC=m +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MCP2221 is not set +# CONFIG_HID_MEGAWORLD_FF is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PID is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_SIGMAMICRO is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPRE is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_VRC2 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_XIAOMI is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set +# CONFIG_I2C_HID_OF_GOODIX is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +CONFIG_INITCALL_ASYNC=y +# CONFIG_INITRAMFS_FORCE is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_INPUT_MATRIXKMAP is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_INV_ICM42600_SPI is not set +# CONFIG_INV_ICM42670_SPI is not set +# CONFIG_INV_MPU6050_SPI is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_LZO is not set +# CONFIG_JFFS2_RTIME is not set +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_KEYBOARD_ADC=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KS8851 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LMK04832 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2632 is not set +# CONFIG_LTC2688 is not set +# CONFIG_LTC2983 is not set +# CONFIG_LTE_GDM724X is not set +CONFIG_LZ4_DECOMPRESS=y +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX11205 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX31856 is not set +# CONFIG_MAX31865 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3911 is not set +# CONFIG_MCP41010 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_RK806_SPI is not set +# CONFIG_MFD_RSMU_SPI is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_DW=m +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_ROCKCHIP=m +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_QUEUE_DEPTH=1 +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MOST is not set +# CONFIG_MOXTET is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MSE102X is not set +CONFIG_MTD_BLKDEVS=m +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_ATMEL is not set +# CONFIG_MTD_SPI_NOR_BOYA is not set +# CONFIG_MTD_SPI_NOR_CATALYST is not set +# CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT is not set +# CONFIG_MTD_SPI_NOR_DOSILICON is not set +# CONFIG_MTD_SPI_NOR_EON is not set +# CONFIG_MTD_SPI_NOR_ESMT is not set +# CONFIG_MTD_SPI_NOR_EVERSPIN is not set +# CONFIG_MTD_SPI_NOR_FMSH is not set +# CONFIG_MTD_SPI_NOR_FUJITSU is not set +CONFIG_MTD_SPI_NOR_GIGADEVICE=y +# CONFIG_MTD_SPI_NOR_INTEL is not set +# CONFIG_MTD_SPI_NOR_ISSI is not set +CONFIG_MTD_SPI_NOR_MACRONIX=y +CONFIG_MTD_SPI_NOR_MISC=y +# CONFIG_MTD_SPI_NOR_NORMEM is not set +# CONFIG_MTD_SPI_NOR_PUYA is not set +# CONFIG_MTD_SPI_NOR_SPANSION is not set +# CONFIG_MTD_SPI_NOR_SST is not set +# CONFIG_MTD_SPI_NOR_STMICRO is not set +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPI_NOR_WINBOND=y +# CONFIG_MTD_SPI_NOR_XILINX is not set +# CONFIG_MTD_SPI_NOR_XMC is not set +# CONFIG_MTD_SPI_NOR_XTX is not set +# CONFIG_MTD_SST25L is not set +CONFIG_NET_VENDOR_ADI=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NVME_TARGET is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=m +# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set +# CONFIG_PI433 is not set +# CONFIG_PWRSEQ_EMMC is not set +CONFIG_PWRSEQ_SIMPLE=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_RC_CORE is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_ZSTD is not set +CONFIG_REGMAP_SPI=y +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_RMI4_CORE is not set +# CONFIG_ROCKCHIP_ANALOGIX_DP is not set +# CONFIG_ROCKCHIP_CDN_DP is not set +# CONFIG_ROCKCHIP_DP_MST_AUX_CLIENT is not set +# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set +# CONFIG_ROCKCHIP_DRM_TVE is not set +# CONFIG_ROCKCHIP_DW_DP is not set +# CONFIG_ROCKCHIP_DW_HDCP2 is not set +# CONFIG_ROCKCHIP_DW_HDMI is not set +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set +# CONFIG_ROCKCHIP_INNO_HDMI is not set +# CONFIG_ROCKCHIP_LVDS is not set +# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set +CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m +# CONFIG_ROCKCHIP_PANEL_NOTIFIER is not set +# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set +# CONFIG_ROCKCHIP_REMOTECTL is not set +CONFIG_ROCKCHIP_RGA_DEBUGGER=y +CONFIG_ROCKCHIP_RGB=y +# CONFIG_ROCKCHIP_RK3066_HDMI is not set +# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set +CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y +CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y +# CONFIG_ROCKCHIP_VCONN is not set +CONFIG_ROCKCHIP_VOP=y +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCA3300 is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SENSOR_DEVICE is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=m +# CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AMD is not set +# CONFIG_SPI_AX88796C is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MICROCHIP_CORE is not set +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_MUX is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI is not set +# CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI is not set +CONFIG_SPI_ROCKCHIP_SFC=y +# CONFIG_SPI_ROCKCHIP_SLAVE is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS131E08 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TSC2046 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_9551R is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5 is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELAN5515 is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FT5726 is not set +# CONFIG_TOUCHSCREEN_FTS is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GSL3673 is not set +# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set +# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set +CONFIG_TOUCHSCREEN_GT1X=y +# CONFIG_TOUCHSCREEN_GT9XX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set +# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_ILITEK is not set +# CONFIG_TOUCHSCREEN_IMAGIS is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MSG2638 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PARADE is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_W9013 is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +# CONFIG_TYPEC is not set +# CONFIG_UHID is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_USB=m +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_AUDIO is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_COMMON=m +CONFIG_USB_CONFIGFS=m +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +# CONFIG_USB_CONFIGFS_EEM is not set +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_UVC=y +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_OBEX is not set +CONFIG_USB_CONFIGFS_RNDIS=y +# CONFIG_USB_CONFIGFS_SERIAL is not set +CONFIG_USB_CONFIGFS_UEVENT=y +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_OF_SIMPLE=m +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +CONFIG_USB_F_FS=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HID=m +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LEGOTOWER is not set +CONFIG_USB_LIBCOMPOSITE=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3420_UDC is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RAW_GADGET is not set +CONFIG_USB_ROLE_SWITCH=m +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_ULPI_BUS is not set +CONFIG_USB_U_AUDIO=m +CONFIG_USB_U_ETHER=m +# CONFIG_USB_WDM is not set +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=m +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZERO is not set +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_ROCKCHIP_PREISP is not set +# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set +CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP=y +# CONFIG_VIDEO_S5C73M3 is not set +# CONFIG_XILLYUSB is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y From f133c251b13655afb15cba35920f02c147a62f9a Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 25 Jun 2025 11:01:20 +0800 Subject: [PATCH 25/25] drm/rockchip: dsi2: add support split mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit <-2HxV-> <------------- H x V --------------> <-H x V-> ┌───────┐ ┌───────┐ ┌───────────┐ ┌───────┐ │ DSC0 ├───►│dsi0 tx├──►│lcd dsi0 rx│──►│lcd dsc│ ┌─────┐ /└───────┘ └───────┘ └───────────┘ └───────┘ │ │/ │ VP │\ ┌───────┐ ┌───────┐ ┌───────────┐ ┌───────┐ └─────┘ \│ DSC1 ├───►│dsi1 tx├──►│lcd dsi1 rx│──►│lcd dsc│ └───────┘ └───────┘ └───────────┘ └───────┘ Change-Id: I7a12d3bccd44934dddb8422c184aceed353b0e8a Signed-off-by: Guochun Huang --- .../gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 34 +++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c index 92a19144dbae..3abd81a8481b 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c @@ -281,6 +281,9 @@ struct dw_mipi_dsi2 { struct gpio_desc *te_gpio; + /* rockchip,split-mode */ + bool split_mode; + /* split with other display interface */ bool dual_connector_split; bool left_display; @@ -1211,14 +1214,27 @@ dw_mipi_dsi2_encoder_helper_funcs = { static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector) { struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); + struct drm_display_info *di = &connector->display_info; + int num_modes = 0; if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_MODES)) - return drm_bridge_get_modes(dsi2->bridge, connector); + num_modes = drm_bridge_get_modes(dsi2->bridge, connector); if (dsi2->panel) - return drm_panel_get_modes(dsi2->panel, connector); + num_modes = drm_panel_get_modes(dsi2->panel, connector); - return -EINVAL; + if (!num_modes) + return -EINVAL; + + if (dsi2->split_mode && dsi2->slave) { + struct drm_display_mode *mode; + + di->width_mm *= 2; + list_for_each_entry(mode, &connector->probed_modes, head) + drm_mode_convert_to_split_mode(mode); + } + + return num_modes; } static enum drm_mode_status @@ -1382,7 +1398,8 @@ static struct dw_mipi_dsi2 *dw_mipi_dsi2_find_by_id(struct device_driver *drv, static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2) { - if (of_property_read_bool(dsi2->dev->of_node, "rockchip,dual-channel")) { + if (of_property_read_bool(dsi2->dev->of_node, "rockchip,dual-channel") || + of_property_read_bool(dsi2->dev->of_node, "rockchip,split-mode")) { dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node, "rockchip,data-swap"); @@ -1390,8 +1407,13 @@ static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2) if (!dsi2->slave) return -EPROBE_DEFER; + if (of_property_read_bool(dsi2->dev->of_node, "rockchip,split-mode")) + dsi2->split_mode = true; + dsi2->slave->master = dsi2; - dsi2->lanes /= 2; + + if (!dsi2->split_mode) + dsi2->lanes /= 2; dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; dsi2->slave->lanes = dsi2->lanes; @@ -1491,7 +1513,7 @@ static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2, dsi2->pps = pps; - if (dsi2->slave) { + if (dsi2->slave && !dsi2->split_mode) { u16 pic_width = be16_to_cpu(pps->pic_width) / 2; dsi2->pps->pic_width = cpu_to_be16(pic_width);