From aaf9c163ea8ea125e31b39551bbcef1bd4548d83 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Thu, 16 Mar 2023 03:51:23 +0000 Subject: [PATCH] arm64: dts: rockchip: rk3562-evb2: add fast image reverse support Change-Id: Ic240f2680e221aaadf40303d3367fcf604e03100 Signed-off-by: Jianwei Fan --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3562-evb2-ddr4-v10-image-reverse.dts | 11 ++ .../rockchip/rk3562-evb2-image-reverse.dtsi | 171 ++++++++++++++++++ .../dts/rockchip/rk3562-evb2-nvp6324.dtsi | 140 ++++++++++++++ 4 files changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-image-reverse.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3562-evb2-nvp6324.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index fd1f24b1da12..2fed26724f96 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-dual-camera.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-image-reverse.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-pdm-mic-array.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-image-reverse.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-image-reverse.dts new file mode 100644 index 000000000000..864807b6884d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-ddr4-v10-image-reverse.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" +#include "rk3562-evb2-nvp6324.dtsi" +#include "rk3562-evb2-image-reverse.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi new file mode 100644 index 000000000000..561128b91645 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-image-reverse.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/{ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_vehicle: drm-vehicle@0{ + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M + linux,cma-default; + }; + }; + + gpio_det: gpio-det { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&vehicle_gpios>; + + /*if use the reverse, please config this*/ + car-reverse { + car-reverse-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,debounce-ms = <5>; + label = "car-reverse"; + gpio,wakeup; + }; + }; + + vehicle: vehicle { + compatible = "rockchip,vehicle"; + status = "okay"; + + // pinctrl-names = "default"; + // pinctrl-0 = <&camm0_clk0_out>; + + clocks = <&cru ACLK_VICAP>, + <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, + <&cru CSIRX0_CLK_DATA>, + <&cru CSIRX1_CLK_DATA>, + <&cru CSIRX2_CLK_DATA>, + <&cru CSIRX3_CLK_DATA>; + clock-names = "aclk_cif", + "hclk_cif", + "dclk_cif", + "csirx0_data", + "csirx1_data", + "csirx2_data", + "csirx3_data"; + resets = <&cru SRST_A_VICAP>, + <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, + <&cru SRST_I0_VICAP>, + <&cru SRST_I1_VICAP>, + <&cru SRST_I2_VICAP>, + <&cru SRST_I3_VICAP>; + reset-names = "rst_cif_a", + "rst_cif_h", + "rst_cif_d", + "rst_cif_i0", + "rst_cif_i1", + "rst_cif_i2", + "rst_cif_i3"; + power-domains = <&power RK3562_PD_VI>; + cif,drop-frames = <4>; //frames to drop + cif,chip-id = <2>; /*0:rk3568 1:rk3588 2:rk3562*/ + rockchip,grf = <&sys_grf>; + rockchip,cru = <&cru>; + rockchip,cif = <&rkcif>; + rockchip,gpio-det = <&gpio_det>; + rockchip,cif-sensor = <&cif_sensor>; + rockchip,cif-phy = <&cif_phy>; + ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 + /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ + vehicle,rotate-mirror = <0x00>; + vehicle,crtc_name = "video_port0"; + vehicle,plane_name = "Esmart0-win0"; + }; + + cif_phy: cif_phy { + status = "okay"; + + csi2_dphy0 { + status = "okay"; + clocks = <&cru CLK_CAM0_OUT2IO>, + <&cru PCLK_CSIPHY0>, + <&cru PCLK_CSIHOST0>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_P_CSIPHY0>, + <&cru SRST_P_CSIHOST0>; + reset-names = "srst_p_csiphy", + "srst_csihost_p"; + csihost-idx = <0>; + rockchip,csi2-dphy = <&csi2_dphy0_hw>; + rockchip,csi2 = <&mipi0_csi2>; + }; + csi2_dphy3 { + status = "disabled"; + clocks = <&cru CLK_CAM2_OUT2IO>, + <&cru PCLK_CSIPHY1>, + <&cru PCLK_CSIHOST2>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_P_CSIPHY1>, + <&cru SRST_P_CSIHOST2>; + reset-names = "srst_p_csiphy", + "srst_csihost_p"; + csihost-idx = <2>; + rockchip,csi2-dphy = <&csi2_dphy1_hw>; + rockchip,csi2 = <&mipi2_csi2>; + }; + }; + + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "okay"; + + nvp6324 { + status = "okay"; + // dphy0 + powerdown-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pwdn_active = <1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + rst_active = <1>; + // dphy3 + // powerdown-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + // pwdn_active = <1>; + // reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + // rst_active = <1>; + + orientation = <90>; + i2c_add = <0x60>; + i2c_chl = <4>; + cif_chl = <0>; + ad_chl = <0>; + mclk_rate = <24>; + rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_vehicle>; + memory-region-names = "drm-logo", "drm-vehicle"; +}; + +&i2c4 { + status = "okay"; +}; + +&pinctrl { + vehicle { + vehicle_gpios: vehicle-pins { + /* gpios */ + rockchip,pins = + /* car-reverse */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-nvp6324.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-evb2-nvp6324.dtsi new file mode 100644 index 000000000000..07b53bfa55c1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-nvp6324.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&n4_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + jaguar1: jaguar1@30 { + compatible = "jaguar1-v4l2"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pd-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "jaguar1"; + rockchip,camera-module-lens-name = "jaguar1"; + rockchip,default_rect= <1920 1080>; // default resolution + port { + n4_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; +