From ab4677495ed60fb6953c7c64f81e44a43b02631b Mon Sep 17 00:00:00 2001 From: Jihong Sui Date: Tue, 17 Sep 2019 13:48:14 +0800 Subject: [PATCH] deinterlace: fix blend setting err [1/1] PD#SWPL-8980 Problem: 0x170d[16] can't set; Solution: Correct logic errors according to Feijun's suggestions Verify: TL1 Change-Id: If1ba9494d49b5614aac7571c3ee0e6ddb3fb6245 Signed-off-by: Jihong Sui --- drivers/amlogic/media/deinterlace/deinterlace_hw.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 6cda21b6fa1d..082b96f2f033 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -3842,25 +3842,29 @@ void pulldown_vof_win_config(struct pulldown_detected_s *wins) (wins->regs[0].win_ve > wins->regs[0].win_vs) ? 1 : 0, 16, 1); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, - wins->regs[0].blend_mode, 8, 2); + /*wins->regs[0].blend_mode*/ + 0x03, 8, 2); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, (wins->regs[1].win_ve > wins->regs[1].win_vs) ? 1 : 0, 17, 1); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, - wins->regs[1].blend_mode, 10, 2); + /*wins->regs[1].blend_mode*/ + 0x03, 10, 2); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, (wins->regs[2].win_ve > wins->regs[2].win_vs) ? 1 : 0, 18, 1); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, - wins->regs[2].blend_mode, 12, 2); + /*wins->regs[2].blend_mode*/ + 0x03, 12, 2); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, (wins->regs[3].win_ve > wins->regs[3].win_vs) ? 1 : 0, 19, 1); DI_VSYNC_WR_MPEG_REG_BITS(DI_BLEND_CTRL, - wins->regs[3].blend_mode, 14, 2); + /*wins->regs[3].blend_mode*/ + 0x03, 14, 2); }