From c1ea5f751eff48b7aa9954ff40dca91e80ae4670 Mon Sep 17 00:00:00 2001 From: Zhibin Huang Date: Wed, 21 Feb 2024 18:21:22 +0800 Subject: [PATCH 01/10] misc: rk628: bt1120-2-hdmi: set bus_format for bt1120 Type: Fix Redmine ID: N/A Associated modifications: N/A Test: N/A Signed-off-by: Zhibin Huang Change-Id: I5e285e5c14e639a552936835b726da6e71a2e998 --- drivers/misc/rk628/rk628_hdmitx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/rk628/rk628_hdmitx.c b/drivers/misc/rk628/rk628_hdmitx.c index abd86c8d936e..b5d7ab46a631 100644 --- a/drivers/misc/rk628/rk628_hdmitx.c +++ b/drivers/misc/rk628/rk628_hdmitx.c @@ -741,6 +741,17 @@ static int rk628_hdmi_bridge_attach(struct drm_bridge *bridge, return ret; } + if (rk628_input_is_bt1120(hdmi->rk628)) { + u32 bus_format = MEDIA_BUS_FMT_YUYV8_1X16; + + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + if (ret) { + dev_err(hdmi->dev, "Failed to set bus formats\n"); + return ret; + } + } + drm_connector_helper_add(connector, &rk628_hdmi_connector_helper_funcs); drm_connector_attach_encoder(connector, bridge->encoder); From 466091d79d2216352970b9fafabe56e431825f94 Mon Sep 17 00:00:00 2001 From: Jianwei Fan Date: Mon, 19 Feb 2024 16:06:19 +0800 Subject: [PATCH 02/10] arm64: dts: rockchip: rk3588-evb: rk628 change the interrupt to rise edge trigger Change-Id: I6c3905d2e1440ae82654e3a3f62b762c1f1e2ec7 Signed-off-by: Jianwei Fan --- .../boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts | 4 ++-- .../boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts index 8aa1a74159ff..eb1b5cfd95a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts @@ -108,7 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rk628_pin_1>; interrupt-parent = <&gpio1>; - interrupts = ; + interrupts = ; enable-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; @@ -148,7 +148,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rk628_pin>; interrupt-parent = <&gpio2>; - interrupts = ; + interrupts = ; enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts index a0de491c2efc..64813821ff5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts @@ -78,7 +78,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rk628_pin>; interrupt-parent = <&gpio1>; - interrupts = ; + interrupts = ; enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; plugin-det-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; From 2424e1c910554886913dc536aacfcf08966a7855 Mon Sep 17 00:00:00 2001 From: Zhibin Huang Date: Thu, 22 Feb 2024 08:28:25 +0800 Subject: [PATCH 03/10] misc: rk628: bt1120: add yc-swap and uv-swap property Type: Function Redmine ID: N/A Associated modifications: N/A Test: N/A Signed-off-by: Zhibin Huang Change-Id: Ie1c54ac3fbc01d76d32eff8d2857f68339654b70 --- drivers/misc/rk628/rk628.h | 5 ++++- drivers/misc/rk628/rk628_rgb.c | 22 ++++++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/misc/rk628/rk628.h b/drivers/misc/rk628/rk628.h index 4d58c350a53a..b870d604fcc6 100644 --- a/drivers/misc/rk628/rk628.h +++ b/drivers/misc/rk628/rk628.h @@ -135,7 +135,8 @@ #define DUAL_DATA_SWAP BIT(6) #define DEC_DUALEDGE_EN BIT(5) #define SW_PROGRESS_EN BIT(4) -#define SW_YC_SWAP BIT(3) +#define SW_BT1120_YC_SWAP BIT(3) +#define SW_BT1120_UV_SWAP BIT(2) #define SW_CAP_EN_ASYNC BIT(1) #define SW_CAP_EN_PSYNC BIT(0) #define GRF_RGB_DEC_CON1 0x0044 @@ -541,6 +542,8 @@ struct rk628_combtxphy { struct rk628_rgb { struct regulator *vccio_rgb; bool bt1120_dual_edge; + bool bt1120_yc_swap; + bool bt1120_uv_swap; }; struct rk628 { diff --git a/drivers/misc/rk628/rk628_rgb.c b/drivers/misc/rk628/rk628_rgb.c index 8cbe0bff3ec7..dee837731c9e 100644 --- a/drivers/misc/rk628/rk628_rgb.c +++ b/drivers/misc/rk628/rk628_rgb.c @@ -16,14 +16,26 @@ int rk628_rgb_parse(struct rk628 *rk628, struct device_node *rgb_np) { int ret = 0; + /* input/output: rgb/bt1120 */ rk628->rgb.vccio_rgb = devm_regulator_get_optional(rk628->dev, "vccio-rgb"); if (IS_ERR(rk628->rgb.vccio_rgb)) rk628->rgb.vccio_rgb = NULL; + /* input/output: bt1120 */ if ((rk628_input_is_bt1120(rk628) || rk628_output_is_bt1120(rk628)) && of_property_read_bool(rk628->dev->of_node, "bt1120-dual-edge")) rk628->rgb.bt1120_dual_edge = true; + /* input: bt1120 */ + if (rk628_input_is_bt1120(rk628)) { + if (of_property_read_bool(rk628->dev->of_node, "bt1120-yc-swap")) + rk628->rgb.bt1120_yc_swap = true; + + if (of_property_read_bool(rk628->dev->of_node, "bt1120-uv-swap")) + rk628->rgb.bt1120_uv_swap = true; + } + + /* output: rgb/bt1120 */ if (rk628_output_is_bt1120(rk628) || rk628_output_is_rgb(rk628)) ret = rk628_panel_info_get(rk628, rgb_np); @@ -300,8 +312,14 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628) SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_BT1120)); rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(1)); rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0, - SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN, - SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN); + SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | + SW_PROGRESS_EN | + SW_BT1120_YC_SWAP | + SW_BT1120_UV_SWAP, + SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | + SW_PROGRESS_EN | + (rk628->rgb.bt1120_yc_swap ? SW_BT1120_YC_SWAP : 0) | + (rk628->rgb.bt1120_uv_swap ? SW_BT1120_UV_SWAP : 0)); } static void rk628_bt1120_encoder_enable(struct rk628 *rk628) From fbdf3d8d033633a2f96a1eb55d55dd48ba61aa5d Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Tue, 23 Jan 2024 13:20:18 +0000 Subject: [PATCH 04/10] ASoC: rockchip: rk817-codec: fix pop from DAC_DIG_CLK_DIS and DAC_DIG_CLK_EN Signed-off-by: Binyuan Lan Change-Id: Idfa31a4f3484f1641ebcf46d237244e98e378e93 --- sound/soc/codecs/rk817_codec.c | 142 ++++++++++++++++++++++----------- 1 file changed, 94 insertions(+), 48 deletions(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index 8c767cec57ac..627d16b6dd67 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -238,16 +238,22 @@ static int rk817_codec_ctl_gpio(struct rk817_codec_priv *rk817, { if ((gpio & CODEC_SET_SPK) && rk817->spk_ctl_gpio) { + if (level && rk817->spk_mute_delay) + msleep(rk817->spk_mute_delay); gpiod_set_value(rk817->spk_ctl_gpio, level); DBG("%s set spk clt %d\n", __func__, level); - msleep(rk817->spk_mute_delay); + if (!level && rk817->spk_mute_delay) + msleep(rk817->spk_mute_delay); } if ((gpio & CODEC_SET_HP) && rk817->hp_ctl_gpio) { + if (level && rk817->hp_mute_delay) + msleep(rk817->hp_mute_delay); gpiod_set_value(rk817->hp_ctl_gpio, level); DBG("%s set hp clt %d\n", __func__, level); - msleep(rk817->hp_mute_delay); + if (!level && rk817->hp_mute_delay) + msleep(rk817->hp_mute_delay); } return 0; @@ -267,12 +273,12 @@ static int rk817_reset(struct snd_soc_component *component) snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x00); snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00); if (rk817->chip_ver <= 0x4) { - DBG("%s (%d): SMIC TudorAG and previous versions\n", + DBG("%s (%d): 0x4 and previous versions\n", __func__, __LINE__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95); } else { - DBG("%s (%d): SMIC TudorAG version later\n", + DBG("%s (%d): 0x4 version later\n", __func__, __LINE__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); @@ -282,6 +288,77 @@ static int rk817_reset(struct snd_soc_component *component) return 0; } +static int rk817_restart_dac_digital_clk(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_MASK, PWD_DACBIAS_DOWN); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN); + DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_MASK, PWD_DACBIAS_ON); + + return 0; +} + +static int rk817_restart_dac_digital_clk_and_apll(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_MASK, PWD_DACBIAS_DOWN); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN); + DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_DOWN); + usleep_range(50, 60); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_UP); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_ADAC_CFG1, + PWD_DACBIAS_MASK, PWD_DACBIAS_ON); + + return 0; +} + +static int rk817_restart_adc_digital_clk(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN); + DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__); + + return 0; +} + +static int rk817_restart_adc_digital_clk_and_apll(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS); + usleep_range(500, 600); + snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, + ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN); + DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_DOWN); + usleep_range(50, 60); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_UP); + usleep_range(500, 600); + + return 0; +} + static struct rk817_reg_val_typ playback_power_up_list[] = { {RK817_CODEC_AREF_RTCFG1, 0x40}, {RK817_CODEC_DDAC_POPD_DACST, 0x02}, @@ -380,22 +457,16 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type) /* configure APLL CFG0/4 */ if (rk817->chip_ver <= 0x4) { - DBG("%s (%d): SMIC TudorAG and previous versions\n", + DBG("%s (%d): 0x4 and previous versions\n", __func__, __LINE__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95); } else { - DBG("%s: SMIC TudorAG version later\n", __func__); + DBG("%s: 0x4 version later\n", __func__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); } - - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS); - usleep_range(2000, 2500); - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN); - DBG("%s: %d - Playback DIG CLK OPS\n", __func__, __LINE__); + rk817_restart_dac_digital_clk(component); } if (type & RK817_CODEC_CAPTURE) { @@ -411,22 +482,17 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type) /* configure APLL CFG0/4 */ if (rk817->chip_ver <= 0x4) { - DBG("%s (%d): SMIC TudorAG and previous versions\n", + DBG("%s (%d): 0x4 and previous versions\n", __func__, __LINE__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95); } else { - DBG("%s: SMIC TudorAG version later\n", __func__); + DBG("%s: 0x4 version later\n", __func__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); } - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - ADC_DIG_CLK_MASK, ADC_DIG_CLK_DIS); - usleep_range(2000, 2500); - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - ADC_DIG_CLK_MASK, ADC_DIG_CLK_EN); - DBG("%s: %d - Capture DIG CLK OPS\n", __func__, __LINE__); + rk817_restart_adc_digital_clk(component); if (rk817->mic_in_differential) snd_soc_component_update_bits(component, @@ -948,25 +1014,19 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, unsigned int rate = params_rate(params); unsigned char apll_cfg3_val; unsigned char dtop_digen_sr_lmt0; - unsigned char dtop_digen_clke; DBG("%s : sample rate = %dHz\n", __func__, rate); if (rk817->chip_ver <= 0x4) { - DBG("%s: SMIC TudorAG and previous versions\n", __func__); + DBG("%s: 0x4 and previous versions\n", __func__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x0c); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0x95); } else { - DBG("%s: SMIC TudorAG version later\n", __func__); + DBG("%s: 0x4 version later\n", __func__); snd_soc_component_write(component, RK817_CODEC_APLL_CFG0, 0x04); snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); } - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - dtop_digen_clke = DAC_DIG_CLK_EN; - else - dtop_digen_clke = ADC_DIG_CLK_EN; - switch (rate) { case 8000: apll_cfg3_val = 0x03; @@ -998,19 +1058,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, */ if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) { snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val); - /* The 0x00 contains ADC_DIG_CLK_DIS and DAC_DIG_CLK_DIS */ - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - dtop_digen_clke, 0x00); snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0, DACSRT_MASK, dtop_digen_sr_lmt0); - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - dtop_digen_clke, dtop_digen_clke); - snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, - PLL_PW_DOWN, PLL_PW_DOWN); - usleep_range(50, 60); - snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, - PLL_PW_DOWN, PLL_PW_UP); - usleep_range(500, 600); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + rk817_restart_dac_digital_clk_and_apll(component); + else + rk817_restart_adc_digital_clk_and_apll(component); } switch (params_format(params)) { @@ -1048,14 +1101,7 @@ static int rk817_digital_mute_dac(struct snd_soc_dai *dai, int mute, int stream) snd_soc_component_update_bits(component, RK817_CODEC_DDAC_MUTE_MIXCTL, DACMT_ENABLE, DACMT_ENABLE); - snd_soc_component_write(component, RK817_CODEC_ADAC_CFG1, - PWD_DACBIAS_DOWN | PWD_DACD_DOWN | - PWD_DACL_DOWN | PWD_DACR_DOWN); - /* Reset DAC DTOP_DIGEN_CLKE for playback stopped */ - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - DAC_DIG_CLK_EN, DAC_DIG_CLK_DIS); - snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, - DAC_DIG_CLK_EN, DAC_DIG_CLK_EN); + rk817_restart_dac_digital_clk(component); snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, I2SRX_EN_MASK, I2SRX_DIS); } else { From 4422957f7533d7a974b543a715347b722c0e7f80 Mon Sep 17 00:00:00 2001 From: Cody Xie Date: Tue, 23 Jan 2024 10:35:24 +0800 Subject: [PATCH 05/10] arm64: dts: rockchip: rk3588-vehicle-evb-v21/v22: Use vehicle dummy driver for gear selection Change-Id: I2ed1289f3a14361af15f09def32b654363c8a82a Signed-off-by: Cody Xie --- .../dts/rockchip/rk3588-vehicle-evb-v21.dts | 21 +++++-------------- .../dts/rockchip/rk3588-vehicle-evb-v22.dts | 21 +++++-------------- 2 files changed, 10 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts index 258ec54f349b..7d198395247a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts @@ -35,23 +35,12 @@ #sound-dai-cells = <1>; status = "okay"; }; - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - reverse { - label = "GPIO Key Reverse"; - linux,code = ; - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - - park { - label = "GPIO Key Park"; - linux,code = ; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; + vehicle_dummy: vehicle_dummy { + status = "okay"; + compatible = "rockchip,vehicle-dummy-gpio"; + reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts index f1ec17c12157..626273eb1029 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts @@ -299,23 +299,12 @@ #sound-dai-cells = <1>; status = "okay"; }; - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - reverse { - label = "GPIO Key Reverse"; - linux,code = ; - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - - park { - label = "GPIO Key Park"; - linux,code = ; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; + vehicle_dummy: vehicle_dummy { + status = "okay"; + compatible = "rockchip,vehicle-dummy-gpio"; + reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; }; vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { From 3c7417b499e34fe0d841a408bf9e0959b808d13f Mon Sep 17 00:00:00 2001 From: Luo Wei Date: Mon, 26 Feb 2024 17:16:21 +0800 Subject: [PATCH 06/10] arm64: dts: rockchip: rk3588-vehicle-evb: maxim support 1080p display dsi0-> ->max96752->720P max96789 dsi1-> ->max96752->1080P dp0/edp0-> ->max96752->720P max96745 edp1/edp1-> ->max96752->720P Signed-off-by: Luo Wei Change-Id: I6f3c51ce40a6f11f0e135a6e649b2f5e7a8ba752 --- ...ehicle-serdes-mfd-display-maxim-split.dtsi | 78 +++++++++---------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi index 7dd62e5150fe..44d71e44dd78 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi @@ -489,57 +489,57 @@ 0322 0024 //Init Default 0326 00E4 - //HSYNC_WIDTH_L - 0385 0038 - //VSYNC_WIDTH_L - 0386 0008 + //HSYNC_WIDTH_L HSYNC=32 + 0385 0020 + //VSYNC_WIDTH_L VSYNC=2 + 0386 0002 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0387 0000 - //VFP_L + //VFP_L VFP=200 03A5 00C8 //VBP_H 03A7 0000 - //VFP_H/VBP_L - 03A6 0020 - //VRES_L + //VFP_H/VBP_L VBP=8 + 03A6 0008 + //VRES_L VRES=0X02D0=720 03A8 00D0 //VRES_H 03A9 0002 - //HFP_L + //HFP_L HFP=56 03AA 0038 //HBP_H - 03AC 0002 - //HFP_H/HBP_L - 03AB 0000 - //HRES_L + 03AC 0003 + //HFP_H/HBP_L(4bit) HBP=56 + 03AB 0008 + //HRES_L HRES=0X0780=1920 03AD 0080 //HRES_H 03AE 0007 //Disable FIFO/DESKEW_EN 03A4 00C0 - //HSYNC_WIDTH_L - 0395 0038 - //VSYNC_WIDTH_L - 0396 0008 + //HSYNC_WIDTH_L HSYNC=40 + 0395 0028 + //VSYNC_WIDTH_L VSYNC=20 + 0396 0014 //HSYNC_WIDTH_H/VSYNC_WIDTH_H 0397 0000 - //VFP_L - 03B1 00C8 + //VFP_L VFP=15 + 03B1 000F //VBP_H 03B3 0000 - //VFP_H/VBP_L - 03B2 0020 - //VRES_L - 03B4 00D0 + //VFP_H/VBP_L VBP=10 + 03B2 000A + //VRES_L VRES=0X0438=1080 + 03B4 0038 //VRES_H - 03B5 0002 - //HFP_L - 03B6 0038 + 03B5 0004 + //HFP_L HFP=140 + 03B6 008C //HBP_H - 03B8 0002 - //HFP_H/HBP_L - 03B7 0000 - //HRES_L + 03B8 0006 + //HFP_H/HBP_L HBP=100 + 03B7 0004 + //HRES_L HRES=0X0780=1920 03B9 0080 //HRES_H 03BA 0007 @@ -870,15 +870,15 @@ panel-size= <346 194>; panel-timing { - clock-frequency = <115200000>; + clock-frequency = <148500000>; hactive = <1920>; - vactive = <720>; - hfront-porch = <56>; - hsync-len = <32>; - hback-porch = <56>; - vfront-porch = <200>; - vsync-len = <2>; - vback-porch = <8>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; @@ -2434,5 +2434,5 @@ &vp3 { assigned-clocks = <&cru DCLK_VOP3>; - assigned-clock-parents = <&cru PLL_V0PLL>; + assigned-clock-parents = <&cru PLL_GPLL>; }; From e4247367325a5aa175be7f762dc0a5303e0c620b Mon Sep 17 00:00:00 2001 From: Herman Chen Date: Mon, 26 Feb 2024 14:50:40 +0800 Subject: [PATCH 07/10] video: rockchip: mpp: rkvenc2: Fix rw_sem error Use the pointer copy to replace rwsem entry copy. https://redmine.rock-chips.com/issues/461476 DEBUG_RWSEMS_WARN_ON(sem->magic != sem): count = 0x100, magic = 0xffffff81036e2a80, owner = 0xffffff81037f8001, curr 0xffffff81037f8000, list not empty WARNING: CPU: 0 PID: 171 at kernel/locking/rwsem.c:1468 __up_read+0x1dc/0x264 Modules linked in: bcmdhd(O) dhd_static_buf CPU: 0 PID: 171 Comm: irq/47-fdbe0000 Tainted: G O 5.10.160 #13 Hardware name: Rockchip RK3588S TABLET V11 Board (DT) pstate: 60c00009 (nZCv daif +PAN +UAO TCO BTYPE=-) pc : __up_read+0x1dc/0x264 lr : __up_read+0x1dc/0x264 sp : ffffffc00ca83bb0 x29: ffffffc00ca83bb0 x28: 0000000000000000 x27: ffffffc0080e1000 x26: ffffffc0080e16e0 x25: ffffffc0080e17c0 x24: ffffff8103504080 x23: ffffff8299eeec00 x22: ffffff817ecf8038 x21: ffffff817ecf8088 x20: ffffffc00a725000 x19: ffffff81036e3280 x18: 0000000000000030 x17: 0000000000004d49 x16: 0000000000021f36 x15: ffffffc00a746570 x14: 0000000000000086 x13: ffffffc00964a930 x12: 0000000000000003 x11: fffffffffffe5a28 x10: fffffffffffe5a08 x9 : ffffffc0081b3290 x8 : ffffffc00a748b78 x7 : ffffffc00a7f8b78 x6 : 0000000000000001 x5 : 0000000000000000 x4 : ffffff84fd5b5df8 x3 : ffffff84fd5c6730 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff81037f8000 Call trace: __up_read+0x1dc/0x264 up_read+0x44/0x70 mpp_task_finalize+0x6c/0xb4 rkvenc_free_task+0x20/0x7c mpp_free_task+0x50/0x114 mpp_taskqueue_pop_running.isra.0+0x80/0xbc mpp_task_finish+0xb8/0x180 rkvenc_isr+0xd0/0x2ec mpp_dev_isr_sched+0x70/0xd0 irq_thread_fn+0x30/0xa0 irq_thread+0x1d4/0x2d0 kthread+0x150/0x154 ret_from_fork+0x10/0x1c Fixes: 99582ba73a65 ("video: rockchip: mpp: rkvenc2: Fix dual core issue") Signed-off-by: Herman Chen Change-Id: Id3ecd4b03a9676183a80774fd571f86918281cb9 --- drivers/video/rockchip/mpp/mpp_iommu.c | 3 ++- drivers/video/rockchip/mpp/mpp_iommu.h | 11 ++++++----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/video/rockchip/mpp/mpp_iommu.c b/drivers/video/rockchip/mpp/mpp_iommu.c index 1abbfb74f4e2..b19da6e67c0a 100644 --- a/drivers/video/rockchip/mpp/mpp_iommu.c +++ b/drivers/video/rockchip/mpp/mpp_iommu.c @@ -529,7 +529,8 @@ mpp_iommu_probe(struct device *dev) goto err_put_group; } - init_rwsem(&info->rw_sem); + init_rwsem(&info->rw_sem_self); + info->rw_sem = &info->rw_sem_self; spin_lock_init(&info->dev_lock); info->dev = dev; info->pdev = pdev; diff --git a/drivers/video/rockchip/mpp/mpp_iommu.h b/drivers/video/rockchip/mpp/mpp_iommu.h index 87d1b5c612d2..2787fc069df7 100644 --- a/drivers/video/rockchip/mpp/mpp_iommu.h +++ b/drivers/video/rockchip/mpp/mpp_iommu.h @@ -68,7 +68,8 @@ struct mpp_rk_iommu { struct mpp_dev; struct mpp_iommu_info { - struct rw_semaphore rw_sem; + struct rw_semaphore *rw_sem; + struct rw_semaphore rw_sem_self; struct device *dev; struct platform_device *pdev; @@ -126,7 +127,7 @@ int mpp_iommu_dev_deactivate(struct mpp_iommu_info *info, struct mpp_dev *dev); static inline int mpp_iommu_down_read(struct mpp_iommu_info *info) { if (info) - down_read(&info->rw_sem); + down_read(info->rw_sem); return 0; } @@ -134,7 +135,7 @@ static inline int mpp_iommu_down_read(struct mpp_iommu_info *info) static inline int mpp_iommu_up_read(struct mpp_iommu_info *info) { if (info) - up_read(&info->rw_sem); + up_read(info->rw_sem); return 0; } @@ -142,7 +143,7 @@ static inline int mpp_iommu_up_read(struct mpp_iommu_info *info) static inline int mpp_iommu_down_write(struct mpp_iommu_info *info) { if (info) - down_write(&info->rw_sem); + down_write(info->rw_sem); return 0; } @@ -150,7 +151,7 @@ static inline int mpp_iommu_down_write(struct mpp_iommu_info *info) static inline int mpp_iommu_up_write(struct mpp_iommu_info *info) { if (info) - up_write(&info->rw_sem); + up_write(info->rw_sem); return 0; } From 3402a5b4343b453b897d668a0d2bf5d7ad727a10 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 19 Jan 2024 16:18:00 +0800 Subject: [PATCH 08/10] soc: rockchip: power-domain: Add pd status module param for debug Change-Id: I9edf5741a95f877dda22b2fa75eabe288403ed33 Signed-off-by: Finley Xiao --- drivers/soc/rockchip/pm_domains.c | 90 +++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 5a60ae717ad4..066e059ea27e 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -132,6 +132,96 @@ module_param_named(always_on, pm_domain_always_on, bool, 0644); MODULE_PARM_DESC(always_on, "Always keep pm domains power on except for system suspend."); +#if 0 +#define NAME_LEN 20 + +static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd); +static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on); +static void rockchip_pmu_lock(struct rockchip_pm_domain *pd); +static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd); + +/* + * power on : echo gpu 1 > /sys/module/pm_domains/parameters/status + * power off: echo gpu 0 > /sys/module/pm_domains/parameters/status + */ +static int pd_set_status(const char *val, const struct kernel_param *kp) +{ + struct generic_pm_domain *genpd; + struct rockchip_pm_domain *pd; + char name[NAME_LEN] = { 0 }; + int status = 0; + int i; + bool is_on; + + if (!g_pmu) + return 0; + + if (strlen(val) > (NAME_LEN - 2)) + return -EINVAL; + + if (sscanf(val, "%s %d", name, &status) != 2) { + pr_info("power on : echo gpu 1 > /sys/module/pm_domains/parameters/status\n"); + pr_info("power off: echo gpu 0 > /sys/module/pm_domains/parameters/status\n"); + return -EINVAL; + } + + for (i = 0; i < g_pmu->genpd_data.num_domains; i++) { + genpd = g_pmu->genpd_data.domains[i]; + if (!genpd) + continue; + if (strncmp(genpd->name, name, strlen(name))) + continue; + pd = container_of(genpd, struct rockchip_pm_domain, genpd); + pr_info("set %s %d\n", genpd->name, status); + if (!rockchip_pd_power(pd, status)) { + rockchip_pmu_lock(pd); + is_on = rockchip_pmu_domain_is_on(pd); + rockchip_pmu_unlock(pd); + pr_info("get %s %d\n", genpd->name, is_on); + } + break; + } + + return 0; +} + +/* + * cat /sys/module/pm_domains/parameters/status + */ +static int pd_get_status(char *buffer, const struct kernel_param *kp) +{ + struct generic_pm_domain *genpd; + struct rockchip_pm_domain *pd; + int i; + int len = 0; + bool is_on; + + if (!g_pmu) + return 0; + + for (i = 0; i < g_pmu->genpd_data.num_domains; i++) { + genpd = g_pmu->genpd_data.domains[i]; + if (!genpd) + continue; + pd = container_of(genpd, struct rockchip_pm_domain, genpd); + rockchip_pmu_lock(pd); + is_on = rockchip_pmu_domain_is_on(pd); + rockchip_pmu_unlock(pd); + len += sprintf(buffer + len, "%s %d\n", genpd->name, is_on); + } + + return len; +} + +static const struct kernel_param_ops pd_status_ops = { + .set = pd_set_status, + .get = pd_get_status, +}; + +module_param_cb(status, &pd_status_ops, NULL, 0600); +MODULE_PARM_DESC(status, "Change pd status."); +#endif + static void rockchip_pmu_lock(struct rockchip_pm_domain *pd) { mutex_lock(&pd->pmu->mutex); From 8679c3ff3cd2bb8074aa2c354ee2d62886e8eee1 Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Wed, 7 Feb 2024 14:47:18 +0800 Subject: [PATCH 09/10] arm64: dts: rockchip: rk3568-amp: add configs for amp irqs Signed-off-by: Zain Wang Change-Id: I9509b9dbaffc081aefe53e4ca1bf97cff7a339c0 --- arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi | 115 ++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi index 8de181dd05cf..53b1f54156ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi @@ -3,6 +3,22 @@ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. */ +#include + +#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 8) +#define RSVD0_IRQn 283 +#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N)) +#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */ +#define GIC_TOUCH_REQ_IRQ(cpu) (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */ +#define GPIO_IRQ_GROUP_DISABLE 0x0 +#define GPIO_IRQ_GROUP_EN_BANK_TYPE 0x1 +#define GPIO_IRQ_GROUP_EN_GROUP_TYPE 0x2 +#define GPIO4_IRQn 69 +#define GPIO3_IRQn 68 +#define GPIO2_IRQn 67 +#define GPIO1_IRQn 66 +#define GPIO0_IRQn 65 + / { rockchip_amp: rockchip-amp { compatible = "rockchip,rk3568-amp"; @@ -14,11 +30,108 @@ pinctrl-0 = <&uart4m1_xfer>; status = "okay"; + amp-irqs = /bits/ 64 < + GIC_AMP_IRQ_CFG_ROUTE(152, 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(AMP_CPUOFF_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(GIC_TOUCH_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0))>; + + gpio-group-banks = <5>; + gpio-group { + status = "disabled"; + amp-gpio0 { + gpio-bank-id = <0>; + group-irq-en = ; + bank-type-cfg { + hw-irq = ; + hw-irq-cpu-aff = /bits/ 64 ; + prio = <0xd0>; + status = "disabled"; + }; + }; + amp-gpio1 { + gpio-bank-id = <1>; + group-irq-en = ; + bank-type-cfg { + hw-irq = ; + hw-irq-cpu-aff = /bits/ 64 ; + prio = <0xd0>; + status = "disabled"; + }; + }; + amp-gpio2 { + gpio-bank-id = <2>; + group-irq-en = ; + bank-type-cfg { + hw-irq = ; + hw-irq-cpu-aff = /bits/ 64 ; + prio = <0xd0>; + status = "disabled"; + }; + }; + + amp-gpio3 { + gpio-bank-id = <3>; + group-irq-en = ; + bank-type-cfg { + hw-irq = ; + hw-irq-cpu-aff = /bits/ 64 ; + prio = <0xd0>; + status = "disabled"; + }; + }; + + amp-gpio4 { + gpio-bank-id = <4>; + group-irq-en = ; + bank-type-cfg { + hw-irq = ; + hw-irq-cpu-aff = /bits/ 64 ; + prio = <0xd0>; + status = "disabled"; + }; + + prio-group0 { + group-prio = <0x80>; + group-irq-id = ; + group-irq-aff = /bits/ 64 ; + group-irq-en = <0x1 0x1 0x1 0x1>; + status = "disabled"; + }; + prio-group1 { + group-prio = <0x90>; + group-irq-id = ; + group-irq-aff = /bits/ 64 ; + group-irq-en = <0x0 0x1 0x1 0x1>; + status = "disabled"; + }; + + prio-group2 { + group-prio = <0xA0>; + group-irq-id = ; + group-irq-aff = /bits/ 64 ; + group-irq-en = <0x1 0x1 0x1 0x1>; + status = "disabled"; + }; + }; + }; + amp_cpus: amp-cpus { amp-cpu3 { id = <0x0 0x300>; entry = <0x0 0x2800000>; - boot-on = <0>; + boot-on = <1>; mode = <0>; }; }; From df9eb20bbf8104f56f2168cbebba212512cb39a4 Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Wed, 21 Feb 2024 17:04:27 +0800 Subject: [PATCH 10/10] arm64: dts: rockchip: rk3588-amp: add configs for amp irqs Signed-off-by: Zain Wang Change-Id: Ia925cbce88d38fe22a61de3be5ffdd1936fe1119 --- arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi index 1d5e50466286..a02840811a54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi @@ -5,6 +5,8 @@ #include +#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 8) + / { rockchip_amp: rockchip-amp { compatible = "rockchip,amp"; @@ -17,6 +19,18 @@ pinctrl-names = "default"; pinctrl-0 = <&uart5m0_xfer>; + amp-irqs = /bits/ 64 < + /* GPIO EXT */ + GIC_AMP_IRQ_CFG_ROUTE(314, 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(315, 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(316, 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(317, 0xd0, CPU_GET_AFFINITY(3, 0)) + GIC_AMP_IRQ_CFG_ROUTE(318, 0xd0, CPU_GET_AFFINITY(3, 0)) + /* UART5 */ + GIC_AMP_IRQ_CFG_ROUTE(368, 0xd0, CPU_GET_AFFINITY(3, 0)) + /* MAILBOX */ + GIC_AMP_IRQ_CFG_ROUTE(100, 0xd0, CPU_GET_AFFINITY(3, 0))>; + status = "okay"; };