From ac1e59c0c77f356f161394c0cdfa3e0dbce0ccae Mon Sep 17 00:00:00 2001
From: David Wu <david.wu@rock-chips.com>
Date: Fri, 17 Dec 2021 15:50:50 +0800
Subject: [PATCH] arm64: dts: rockchip: Fix rmii clock mode for
 px30-evb-ddr3-v10

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ie5c07e88c989ed95ebea6882b6a11c13563877b0
---
 .../dts/rockchip/px30-evb-ddr3-v10-avb.dts    |  13 +
 .../dts/rockchip/px30-evb-ddr3-v10-linux.dts  | 276 ++++++++++++++----
 .../boot/dts/rockchip/px30-evb-ddr3-v10.dts   |  13 +
 3 files changed, 249 insertions(+), 53 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts
index 4f25c485d15b..e9a56be8c394 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts
@@ -296,6 +296,19 @@
 	};
 };
 
+&gmac {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "input";
+	assigned-clocks = <&cru SCLK_GMAC>;
+	assigned-clock-parents = <&gmac_clkin>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins &mac_refclk>;
+	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 50000>;
+	status = "okay";
+};
+
 &pinctrl {
 	headphone {
 		hp_det: hp-det {
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dts
index 92e2075b9231..7e1353f1dd59 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-linux.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
  */
 
 /dts-v1/;
@@ -178,8 +178,8 @@
 		pinctrl-names = "default","rts_gpio";
 		pinctrl-0 = <&uart1_rts>;
 		pinctrl-1 = <&uart1_rts_gpio>;
-		BT,reset_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-		BT,wake_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
+		BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
 		BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
 		status = "okay";
 	};
@@ -193,16 +193,16 @@
 	status = "okay";
 
 	panel@0 {
-		compatible = "sitronix,st7703", "simple-panel-dsi";
+		compatible = "simple-panel-dsi";
 		reg = <0>;
 		power-supply = <&vcc3v3_lcd>;
 		backlight = <&backlight>;
-		prepare-delay-ms = <2>;
-		reset-delay-ms = <1>;
-		init-delay-ms = <20>;
-		enable-delay-ms = <120>;
-		disable-delay-ms = <50>;
-		unprepare-delay-ms = <20>;
+		prepare-delay-ms = <0>;
+		reset-delay-ms = <0>;
+		init-delay-ms = <80>;
+		enable-delay-ms = <0>;
+		disable-delay-ms = <10>;
+		unprepare-delay-ms = <60>;
 
 		width-mm = <68>;
 		height-mm = <121>;
@@ -213,46 +213,212 @@
 		dsi,lanes = <4>;
 
 		panel-init-sequence = [
-			05 fa 01 11
-			39 00 04 b9 f1 12 83
-			39 00 1c ba 33 81 05 f9 0e 0e 00 00 00
-				 00 00 00 00 00 44 25 00 91 0a
-				 00 00 02 4f 01 00 00 37
-			15 00 02 b8 25
-			39 00 04 bf 02 11 00
-			39 00 0b b3 0c 10 0a 50 03 ff 00 00 00
-				 00
-			39 00 0a c0 73 73 50 50 00 00 08 70 00
-			15 00 02 bc 46
-			15 00 02 cc 0b
-			15 00 02 b4 80
-			39 00 04 b2 c8 12 30
-			39 00 0f e3 07 07 0b 0b 03 0b 00 00 00
-				 00 ff 00 c0 10
-			39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67
-				 77 33 33
-			39 00 07 c6 00 00 ff ff 01 ff
-			39 00 03 b5 09 09
-			39 00 03 b6 87 95
-			39 00 40 e9 c2 10 05 05 10 05 a0 12 31
-				 23 3f 81 0a a0 37 18 00 80 01
-				 00 00 00 00 80 01 00 00 00 48
-				 f8 86 42 08 88 88 80 88 88 88
-				 58 f8 87 53 18 88 88 81 88 88
-				 88 00 00 00 01 00 00 00 00 00
-				 00 00 00 00
-			39 00 3e ea 00 1a 00 00 00 00 02 00 00
-				 00 00 00 1f 88 81 35 78 88 88
-				 85 88 88 88 0f 88 80 24 68 88
-				 88 84 88 88 88 23 10 00 00 1c
-				 00 00 00 00 00 00 00 00 00 00
-				 00 00 00 00 00 30 05 a0 00 00
-				 00 00
-			39 00 23 e0 00 06 08 2a 31 3f 38 36 07
-				 0c 0d 11 13 12 13 11 18 00 06
-				 08 2a 31 3f 38 36 07 0c 0d 11
-				 13 12 13 11 18
-			05 32 01 29
+			39 00 04 ff 98 81 03
+			15 00 02 01 00
+			15 00 02 02 00
+			15 00 02 03 53
+			15 00 02 04 53
+			15 00 02 05 13
+			15 00 02 06 04
+			15 00 02 07 02
+			15 00 02 08 02
+			15 00 02 09 00
+			15 00 02 0a 00
+			15 00 02 0b 00
+			15 00 02 0c 00
+			15 00 02 0d 00
+			15 00 02 0e 00
+			15 00 02 0f 00
+
+			15 00 02 10 00
+			15 00 02 11 00
+			15 00 02 12 00
+			15 00 02 13 00
+			15 00 02 14 00
+			15 00 02 15 08
+			15 00 02 16 10
+			15 00 02 17 00
+			15 00 02 18 08
+			15 00 02 19 00
+			15 00 02 1a 00
+			15 00 02 1b 00
+			15 00 02 1c 00
+			15 00 02 1d 00
+			15 00 02 1e c0
+			15 00 02 1f 80
+
+			15 00 02 20 02
+			15 00 02 21 09
+			15 00 02 22 00
+			15 00 02 23 00
+			15 00 02 24 00
+			15 00 02 25 00
+			15 00 02 26 00
+			15 00 02 27 00
+			15 00 02 28 55
+			15 00 02 29 03
+			15 00 02 2a 00
+			15 00 02 2b 00
+			15 00 02 2c 00
+			15 00 02 2d 00
+			15 00 02 2e 00
+			15 00 02 2f 00
+
+			15 00 02 30 00
+			15 00 02 31 00
+			15 00 02 32 00
+			15 00 02 33 00
+			15 00 02 34 04
+			15 00 02 35 05
+			15 00 02 36 05
+			15 00 02 37 00
+			15 00 02 38 3c
+			15 00 02 39 35
+			15 00 02 3a 00
+			15 00 02 3b 40
+			15 00 02 3c 00
+			15 00 02 3d 00
+			15 00 02 3e 00
+			15 00 02 3f 00
+
+			15 00 02 40 00
+			15 00 02 41 88
+			15 00 02 42 00
+			15 00 02 43 00
+			15 00 02 44 1f
+
+			15 00 02 50 01
+			15 00 02 51 23
+			15 00 02 52 45
+			15 00 02 53 67
+			15 00 02 54 89
+			15 00 02 55 ab
+			15 00 02 56 01
+			15 00 02 57 23
+			15 00 02 58 45
+			15 00 02 59 67
+			15 00 02 5a 89
+			15 00 02 5b ab
+			15 00 02 5c cd
+			15 00 02 5d ef
+			15 00 02 5e 03
+			15 00 02 5f 14
+
+			15 00 02 60 15
+			15 00 02 61 0c
+			15 00 02 62 0d
+			15 00 02 63 0e
+			15 00 02 64 0f
+			15 00 02 65 10
+			15 00 02 66 11
+			15 00 02 67 08
+			15 00 02 68 02
+			15 00 02 69 0a
+			15 00 02 6a 02
+			15 00 02 6b 02
+			15 00 02 6c 02
+			15 00 02 6d 02
+			15 00 02 6e 02
+			15 00 02 6f 02
+
+			15 00 02 70 02
+			15 00 02 71 02
+			15 00 02 72 06
+			15 00 02 73 02
+			15 00 02 74 02
+			15 00 02 75 14
+			15 00 02 76 15
+			15 00 02 77 0f
+			15 00 02 78 0e
+			15 00 02 79 0d
+			15 00 02 7a 0c
+			15 00 02 7b 11
+			15 00 02 7c 10
+			15 00 02 7d 06
+			15 00 02 7e 02
+			15 00 02 7f 0a
+
+			15 00 02 80 02
+			15 00 02 81 02
+			15 00 02 82 02
+			15 00 02 83 02
+			15 00 02 84 02
+			15 00 02 85 02
+			15 00 02 86 02
+			15 00 02 87 02
+			15 00 02 88 08
+			15 00 02 89 02
+			15 00 02 8a 02
+
+			39 00 04 ff 98 81 04
+			15 00 02 00 80
+			15 00 02 70 00
+			15 00 02 71 00
+			15 00 02 66 fe
+			15 00 02 82 15
+			15 00 02 84 15
+			15 00 02 85 15
+			15 00 02 3a 24
+			15 00 02 32 ac
+			15 00 02 8c 80
+			15 00 02 3c f5
+			15 00 02 88 33
+
+			39 00 04 ff 98 81 01
+			15 00 02 22 0a
+			15 00 02 31 00
+			15 00 02 53 78
+			15 00 02 50 5b
+			15 00 02 51 5b
+			15 00 02 60 20
+			15 00 02 61 00
+			15 00 02 62 0d
+			15 00 02 63 00
+
+			15 00 02 a0 00
+			15 00 02 a1 10
+			15 00 02 a2 1c
+			15 00 02 a3 13
+			15 00 02 a4 15
+			15 00 02 a5 26
+			15 00 02 a6 1a
+			15 00 02 a7 1d
+			15 00 02 a8 67
+			15 00 02 a9 1c
+			15 00 02 aa 29
+			15 00 02 ab 5b
+			15 00 02 ac 26
+			15 00 02 ad 28
+			15 00 02 ae 5c
+			15 00 02 af 30
+			15 00 02 b0 31
+			15 00 02 b1 2e
+			15 00 02 b2 32
+			15 00 02 b3 00
+
+			15 00 02 c0 00
+			15 00 02 c1 10
+			15 00 02 c2 1c
+			15 00 02 c3 13
+			15 00 02 c4 15
+			15 00 02 c5 26
+			15 00 02 c6 1a
+			15 00 02 c7 1d
+			15 00 02 c8 67
+			15 00 02 c9 1c
+			15 00 02 ca 29
+			15 00 02 cb 5b
+			15 00 02 cc 26
+			15 00 02 cd 28
+			15 00 02 ce 5c
+			15 00 02 cf 30
+			15 00 02 d0 31
+			15 00 02 d1 2e
+			15 00 02 d2 32
+			15 00 02 d3 00
+			39 00 04 ff 98 81 00
+			05 00 01 11
+			05 01 01 29
 		];
 
 		panel-exit-sequence = [
@@ -351,7 +517,11 @@
 
 &gmac {
 	phy-supply = <&vcc_phy>;
-	clock_in_out = "output";
+	clock_in_out = "input";
+	assigned-clocks = <&cru SCLK_GMAC>;
+	assigned-clock-parents = <&gmac_clkin>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins &mac_refclk>;
 	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <0 50000 50000>;
@@ -488,7 +658,7 @@
 				};
 			};
 
-			vcc1v8_soc: LDO_REG2 {
+			vccio_sdio: vcc1v8_soc: LDO_REG2 {
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-min-microvolt = <1800000>;
@@ -703,7 +873,7 @@
 &io_domains {
 	status = "okay";
 
-	vccio1-supply = <&vcc_3v0>;
+	vccio1-supply = <&vccio_sdio>;
 	vccio2-supply = <&vccio_sd>;
 	vccio3-supply = <&vcc_3v0>;
 	vccio4-supply = <&vcc3v0_pmu>;
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
index b814812edbe9..4fe2ab7bf8ca 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts
@@ -125,3 +125,16 @@
 		};
 	};
 };
+
+&gmac {
+	phy-supply = <&vcc_phy>;
+	clock_in_out = "input";
+	assigned-clocks = <&cru SCLK_GMAC>;
+	assigned-clock-parents = <&gmac_clkin>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins &mac_refclk>;
+	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 50000>;
+	status = "okay";
+};