From ac2f0e913430748686b8f71dada72db40bc6dc4d Mon Sep 17 00:00:00 2001 From: Bencheng Jing Date: Wed, 17 Jul 2019 16:29:26 +0800 Subject: [PATCH] mcdi: keep g12a/g12b/sm1 reg_mcdi_qmeen same as gxlx2 [1/2] PD#SWPL-10411 Problem: reg_mcdi_qmeen is enable by driver Solution: disable reg_mcdi_qmeen Verify: u212 Change-Id: I02887fab37a0bbeb43bfa83a4a5a2e446bebb9c1 Signed-off-by: Bencheng Jing --- drivers/amlogic/media/deinterlace/deinterlace_hw.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 906dbb241ba2..f6e0c09ea757 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -1356,7 +1356,11 @@ void enable_mc_di_pre_g12(struct DI_MC_MIF_s *mcinford_mif, RDMA_WR_BITS(MCDI_MOTINEN, (mcdi_en?3:0), 0, 2); - RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfff7ff : 0)); + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || + is_meson_sm1_cpu()) + RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfef7ff : 0)); + else + RDMA_WR(MCDI_CTRL_MODE, (mcdi_en ? 0x1bfff7ff : 0)); RDMA_WR_BITS(DI_PRE_CTRL, (mcdi_en?3:0), 16, 2); RDMA_WR_BITS(MCINFRD_SCOPE_X, mcinford_mif->size_x, 16, 13);