From acfeb3f7074c480387f5e02d98a39b37530fce7a Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Fri, 15 Jan 2021 12:49:04 +0800
Subject: [PATCH] ARM: dts: rv1126: uvc: fix cpll to 491520000

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ibd6df2bbcb24ea5ba72c40a8146d8a6d1c3e32a7
---
 arch/arm/boot/dts/rv1126-ai-cam.dtsi  | 19 +++++++++++++++++++
 arch/arm/boot/dts/rv1126-evb-uvc.dtsi | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/rv1126-ai-cam.dtsi b/arch/arm/boot/dts/rv1126-ai-cam.dtsi
index a4f8d0797128..513df0cea4a0 100644
--- a/arch/arm/boot/dts/rv1126-ai-cam.dtsi
+++ b/arch/arm/boot/dts/rv1126-ai-cam.dtsi
@@ -99,6 +99,25 @@
 	status = "okay";
 };
 
+&cru {
+	assigned-clocks =
+		<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
+		<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
+		<&cru PLL_HPLL>, <&cru ARMCLK>,
+		<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
+		<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
+		<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
+		<&cru HCLK_PDCORE_NIU>;
+	assigned-clock-rates =
+		<32768>, <1188000000>,
+		<100000000>, <491520000>,
+		<1400000000>, <600000000>,
+		<500000000>, <200000000>,
+		<100000000>, <300000000>,
+		<200000000>, <150000000>,
+		<200000000>;
+};
+
 &csi_dphy0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/rv1126-evb-uvc.dtsi b/arch/arm/boot/dts/rv1126-evb-uvc.dtsi
index 9e5ea973c041..033477647f41 100644
--- a/arch/arm/boot/dts/rv1126-evb-uvc.dtsi
+++ b/arch/arm/boot/dts/rv1126-evb-uvc.dtsi
@@ -3,6 +3,25 @@
  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
  */
 
+&cru {
+	assigned-clocks =
+		<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
+		<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
+		<&cru PLL_HPLL>, <&cru ARMCLK>,
+		<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
+		<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
+		<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
+		<&cru HCLK_PDCORE_NIU>;
+	assigned-clock-rates =
+		<32768>, <1188000000>,
+		<100000000>, <491520000>,
+		<1400000000>, <600000000>,
+		<500000000>, <200000000>,
+		<100000000>, <300000000>,
+		<200000000>, <150000000>,
+		<200000000>;
+};
+
 &i2s0_8ch {
 	clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>,
 		 <&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>,