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scsi: ufs: rockchip: Fix compile error of module
Fix the error: ERROR: modpost: "ufshcd_send_uic_cmd" [drivers/ufs/host/ufs-rockchip.ko] undefined! Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Change-Id: Ifda88359f03c3aa70564c093dc734f9a1aff4ae7
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@@ -29,14 +29,153 @@ static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
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return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
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}
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#ifdef MODULE
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static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
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{
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#define MIN_DELAY_BEFORE_DME_CMDS_US 1000
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unsigned long min_sleep_time_us;
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if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
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return;
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/*
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* last_dme_cmd_tstamp will be 0 only for 1st call to
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* this function
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*/
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if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
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min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
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} else {
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unsigned long delta =
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(unsigned long) ktime_to_us(
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ktime_sub(ktime_get(),
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hba->last_dme_cmd_tstamp));
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if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
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min_sleep_time_us =
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MIN_DELAY_BEFORE_DME_CMDS_US - delta;
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else
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return; /* no more delay required */
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}
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/* allow sleep for extra 50us if needed */
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usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
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}
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#define UIC_CMD_TIMEOUT 500
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static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
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{
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u32 val;
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int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
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500, UIC_CMD_TIMEOUT * 1000, false, hba,
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REG_CONTROLLER_STATUS);
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return ret == 0 ? true : false;
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}
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static inline void
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ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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lockdep_assert_held(&hba->uic_cmd_mutex);
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WARN_ON(hba->active_uic_cmd);
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hba->active_uic_cmd = uic_cmd;
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/* Write Args */
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ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
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ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
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ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
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/* Write UIC Cmd */
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ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
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REG_UIC_COMMAND);
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}
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static int
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ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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int ret;
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unsigned long flags;
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lockdep_assert_held(&hba->uic_cmd_mutex);
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if (wait_for_completion_timeout(&uic_cmd->done,
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msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
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ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
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} else {
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ret = -ETIMEDOUT;
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dev_err(hba->dev,
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"uic cmd 0x%x with arg3 0x%x completion timeout\n",
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uic_cmd->command, uic_cmd->argument3);
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if (!uic_cmd->cmd_active) {
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dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
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__func__);
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ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
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}
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}
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spin_lock_irqsave(hba->host->host_lock, flags);
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hba->active_uic_cmd = NULL;
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spin_unlock_irqrestore(hba->host->host_lock, flags);
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return ret;
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}
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static int
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__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
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bool completion)
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{
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lockdep_assert_held(&hba->uic_cmd_mutex);
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if (!ufshcd_ready_for_uic_cmd(hba)) {
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dev_err(hba->dev,
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"Controller not ready to accept UIC commands\n");
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return -EIO;
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}
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if (completion)
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init_completion(&uic_cmd->done);
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uic_cmd->cmd_active = 1;
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ufshcd_dispatch_uic_cmd(hba, uic_cmd);
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return 0;
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}
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static int ufs_rockchip_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
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{
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int ret;
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if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
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return 0;
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ufshcd_hold(hba, false);
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mutex_lock(&hba->uic_cmd_mutex);
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ufshcd_add_delay_before_dme_cmd(hba);
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ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
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if (!ret)
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ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
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mutex_unlock(&hba->uic_cmd_mutex);
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ufshcd_release(hba);
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return ret;
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}
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#endif /* MODULE */
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static int ufshcd_dme_link_startup(struct ufs_hba *hba)
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{
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struct uic_command uic_cmd = {0};
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int ret;
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uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
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#ifdef MODULE
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ret = ufs_rockchip_send_uic_cmd(hba, &uic_cmd);
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#else
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ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
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#endif
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if (ret)
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dev_err(hba->dev,
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"dme-link-startup: error code %d\n", ret);
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