From adafb5ebfb7b0ac3ac2a60847ff1d91c70b70934 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 26 Jan 2021 15:00:22 +0800 Subject: [PATCH] drm/rockchip: vop2: Exit standby after display timing config done When clear standby bit, the vop post will start scan out with the old timing immediately(no need config done bit). Sometime the old timing is verery different with the current timing we want config(switch from 4K to 720P), this may cause problems at some point. So we clear standby after a new timing config done. Change-Id: Id621bea6a622c151d3e339b102c6791a6244ac08 Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 8cbb49e1d4d3..794f6f252c21 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2178,7 +2178,6 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, int sys_status = vp->id ? SYS_STATUS_LCDC1 : SYS_STATUS_LCDC0; WARN_ON(vp->event); - vop2_lock(vop2); drm_crtc_vblank_off(crtc); vop2_disable_all_planes_for_crtc(crtc); @@ -3531,7 +3530,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state hdisplay, vdisplay, interlaced ? "i" : "p", adjusted_mode->vrefresh, vcstate->output_type, vp->id); vop2_initial(crtc); - VOP_MODULE_SET(vop2, vp, standby, 0); vcstate->vdisplay = vdisplay; vcstate->mode_update = vop2_crtc_mode_update(crtc); if (vcstate->mode_update) @@ -3720,6 +3718,23 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state vop2_cfg_done(crtc); + /* + * when clear standby bits, it will take effect immediately, + * This means the vp will start scan out immediately with + * the timing it been configured before. + * So we must make sure release standby after the display + * timing is correctly configured. + * This is important when switch resolution, such as + * 4K-->720P: + * if we release standby before 720P timing is configured, + * the VP will start scan out immediately with 4K timing, + * when we switch dclk to 74.25MHZ, VP timing is still 4K, + * so VP scan out with 4K timing at 74.25MHZ dclk, this is + * very slow, than this will trigger vblank timeout. + * + */ + VOP_MODULE_SET(vop2, vp, standby, 0); + drm_crtc_vblank_on(crtc); vop2_unlock(vop2);