From addbe278d7239fdf74209bb915b296be0b9eaac8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 29 Dec 2022 18:12:02 +0800 Subject: [PATCH] arm64: dts: mediatek: mt8192: Mark scp_adsp clock as broken MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 089cd717e6ef03cf9cf7865777d67775de41339b ] The scp_adsp clock controller is under the SCP_ADSP power domain. This power domain is currently not supported nor defined. Mark the clock controller as broken for now, to avoid the system from trying to access it, and causing the CPU or bus to stall. Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: Chen-Yu Tsai Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20221229101202.1655924-1-wenst@chromium.org Signed-off-by: Matthias Brugger Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8163684a23f6..7da221924e37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -583,6 +583,8 @@ compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; #clock-cells = <1>; + /* power domain dependency not upstreamed */ + status = "fail"; }; uart0: serial@11002000 {