From ae3a28752ed345036b15f7ca5a927bb33d12ad3b Mon Sep 17 00:00:00 2001 From: William Wu Date: Mon, 5 Jun 2023 09:59:13 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Fix Rx squelch for RK3562 U3 This patch adjust the RK3562 U3 Rx squelch input filler bandwidth to 3'b110 which is used for rx_lfps, reduce the bandwidth to avoid filtering valid superspeed data. With this patch, it can fix the issue that Kingston U3 Disk (idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error on RK3562 platforms. Change-Id: Idb667d159f9dba6b1de0a9ec04af9dae2d065927 Signed-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5ba4864c9899..ca47a6264a7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -635,6 +635,9 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) /* Set PLL KVCO to min and set PLL charge pump current to max */ writel(0xf0, priv->mmio + (0xa << 2)); + /* Set Rx squelch input filler bandwidth */ + writel(0x0e, priv->mmio + (0x14 << 2)); + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);