From ae540757760d0c174fb68a473db756115dd2df9f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 27 Mar 2025 14:36:30 +0800 Subject: [PATCH] clk: rockchip: rv1126b: add sclk_ddr Change-Id: I64db75cb45a5e2704c99dd9003a3ec7e49a3c5aa Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/Kconfig | 3 ++- drivers/clk/rockchip/clk-rv1126b.c | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 517af3e28755..3f7bb1b27026 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -214,7 +214,8 @@ config ROCKCHIP_DDRCLK_SIP config ROCKCHIP_DDRCLK_SIP_V2 bool "Rockchip DDR Clk SIP V2" depends on CPU_PX30 || CPU_RK1808 || CPU_RK312X || CPU_RK322X || \ - CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126 + CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126 || \ + CPU_RV1126B default y select ROCKCHIP_DDRCLK help diff --git a/drivers/clk/rockchip/clk-rv1126b.c b/drivers/clk/rockchip/clk-rv1126b.c index bc01270f57b6..58bfcfe7fe39 100644 --- a/drivers/clk/rockchip/clk-rv1126b.c +++ b/drivers/clk/rockchip/clk-rv1126b.c @@ -22,7 +22,7 @@ #define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16)) enum rv1126b_plls { - gpll, cpll, aupll + gpll, cpll, aupll, dpll }; static struct rockchip_pll_rate_table rv1126b_pll_rates[] = { @@ -142,6 +142,7 @@ PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io", "sclk_sa PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" }; PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" }; PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" }; +PNAME(mux_ddrphy_p) = { "dpll", "aclk_sysmem" }; static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, @@ -153,6 +154,9 @@ static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = { [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0), RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates), + [dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p, + CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0), + RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK @@ -692,6 +696,9 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = { RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS), /* pd_subddr */ + COMPOSITE_DDRCLK(SCLK_DDR, "sclk_ddr", mux_ddrphy_p, CLK_GET_RATE_NOCACHE, + RV1126B_SUBDDRCLKSEL_CON(1), 1, 1, 0, 1, + ROCKCHIP_DDRCLK_SIP_V2), /* pd_ddr */ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,