From ae6dc4e3630e63b23bf5da703d0fdec7ac739493 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 8 Oct 2019 17:40:16 +0800 Subject: [PATCH] Remove rk3366 support Only remove no upstream files and changes. Change-Id: Iee793d802ce91fafce20d22e289418ce63589e43 Signed-off-by: Tao Huang --- .../bindings/clock/rockchip,rk3366-cru.txt | 58 - .../bindings/soc/rockchip/rockchip-pvtm.txt | 2 - .../bindings/video/rockchip_hdmi.txt | 1 - .../boot/dts/rockchip/rk3366-android-6.0.dtsi | 180 -- .../boot/dts/rockchip/rk3366-android.dtsi | 122 - arch/arm64/boot/dts/rockchip/rk3366-fpga.dts | 237 -- arch/arm64/boot/dts/rockchip/rk3366-sheep.dts | 885 -------- arch/arm64/boot/dts/rockchip/rk3366-tb.dts | 903 -------- arch/arm64/boot/dts/rockchip/rk3366.dtsi | 1970 ----------------- drivers/clk/rockchip/Makefile | 1 - drivers/clk/rockchip/clk-rk3366.c | 877 -------- drivers/soc/rockchip/Kconfig.cpu | 3 - drivers/soc/rockchip/rockchip_pvtm.c | 37 - include/dt-bindings/clock/rk3366-cru.h | 424 ---- 14 files changed, 5700 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366-android-6.0.dtsi delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366-android.dtsi delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366-fpga.dts delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366-sheep.dts delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366-tb.dts delete mode 100644 arch/arm64/boot/dts/rockchip/rk3366.dtsi delete mode 100644 drivers/clk/rockchip/clk-rk3366.c delete mode 100644 include/dt-bindings/clock/rk3366-cru.h diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt deleted file mode 100644 index d9d776611d5f..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3366-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3366 Clock and Reset Unit - -The RK3366 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3366-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3366-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_jtag" - external JTAG clock - optional - - "usbotg_out" - output clock of the pll in the otg phy - -Example: Clock controller node: - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3366-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt index 66fa1ec0c06f..ae0cc3aa3173 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt @@ -15,8 +15,6 @@ Required properties: - "rockchip,rk3288-pvtm" - for RK3288 SoCs. - "rockchip,rk3308-pvtm" - for RK3308 SoCs. - "rockchip,rk3308-pmu-pvtm" - for RK3308 SoCs. - - "rockchip,rk3366-pvtm" - for RK3366 SoCs. - - "rockchip,rk3366-pmu-pvtm" - for RK3366 SoCs. - "rockchip,rk3399-pvtm" - for RK3399 SoCs. - "rockchip,rk3399-pmu-pvtm" - for RK3399 SoCs. - clocks: Must contain an entry for each entry in clock-names. diff --git a/Documentation/devicetree/bindings/video/rockchip_hdmi.txt b/Documentation/devicetree/bindings/video/rockchip_hdmi.txt index a983f658ae64..893122a9e3d5 100644 --- a/Documentation/devicetree/bindings/video/rockchip_hdmi.txt +++ b/Documentation/devicetree/bindings/video/rockchip_hdmi.txt @@ -6,7 +6,6 @@ Required properties: "rockchip,rk3066-hdmi", "rockchip,rk312x-hdmi", "rockchip,rk3288-hdmi", - "rockchip,rk3366-hdmi", "rockchip,rk3368-hdmi", "rockchip,rk3399-hdmi", - reg: physical base address of the hdmi and length of memory mapped diff --git a/arch/arm64/boot/dts/rockchip/rk3366-android-6.0.dtsi b/arch/arm64/boot/dts/rockchip/rk3366-android-6.0.dtsi deleted file mode 100644 index 38b229d6c19a..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366-android-6.0.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - compatible = "rockchip,android-6.0", "rockchip,rk3366"; - - fb: fb { - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = ; - status = "disabled"; - }; - - rk_screen: screen { - compatible = "rockchip,screen"; - status = "disabled"; - }; - - vop_lite: vop@ff8f0000 { - compatible = "rockchip,rk3366-lcdc-lite"; - rockchip,grf = <&grf>; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x0 0xff8f0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, - <&cru HCLK_VOP_LITE>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, - <&cru SRST_VOP1_AHB>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - }; - - vopl_mmu: vopl-mmu { - dbgname = "vop"; - compatible = "rockchip,vopl_mmu"; - reg = <0x0 0xff8f0f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - status = "disabled"; - }; - - vop_big: vop@ff930000 { - compatible = "rockchip,rk3366-lcdc-big"; - rockchip,grf = <&grf>; - rockchip,prop = ; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x0 0xff930000 0x0 0x23f0>; - interrupts = ; - clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, - <&cru HCLK_VOP_FULL>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, - <&cru SRST_VOP0_AHB>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - }; - - rk_fb_vopb_mmu: vopb-mmu { - dbgname = "vop"; - compatible = "rockchip,vopb_mmu"; - reg = <0x0 0xff932400 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - status = "disabled"; - }; - - iep_mmu: iep-mmu { - dbgname = "iep"; - compatible = "rockchip,iep_mmu"; - reg = <0x0 0xff900800 0x0 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - status = "disabled"; - }; - - vpu_mmu: vpu_mmu { - dbgname = "vpu"; - compatible = "rockchip,vpu_mmu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - status = "disabled"; - }; - - vdec_mmu: vdec_mmu { - dbgname = "vdec"; - compatible = "rockchip,vdec_mmu"; - reg = <0x0 0xff9b0480 0x0 0x40>, - <0x0 0xff9b04c0 0x0 0x40>; - interrupts = ; - interrupt-names = "vdec_mmu"; - status = "disabled"; - }; - - dsihost0: mipi@ff960000 { - compatible = "rockchip,rk3366-dsi"; - rockchip,prop = <0>; - reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>; - reg-names = "mipi_dsi_host" ,"mipi_dsi_phy"; - interrupts = ; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, - <&cru PCLK_MIPI_DSI0>; - clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host"; - status = "disabled"; - }; - - lvds: lvds@ff968000 { - compatible = "rockchip,rk3366-lvds"; - rockchip,grf = <&grf>; - reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>; - reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; - clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk_lvds", "pclk_lvds_ctl"; - status = "disabled"; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3366-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - interrupts = , - ; - clocks = <&cru PCLK_HDMI_CTRL>, - <&cru SCLK_HDMI_HDCP>, - <&cru SCLK_HDMI_CEC>, - <&cru DCLK_HDMIPHY>; - clock-names = "pclk_hdmi", - "hdcp_clk_hdmi", - "cec_clk_hdmi", - "dclk_hdmi_phy"; - resets = <&cru SRST_HDMI>; - reset-names = "hdmi"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>; - pinctrl-1 = <&i2c5_gpio>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3366-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3366-android.dtsi deleted file mode 100644 index bdacf9e22b1f..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366-android.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - compatible = "rockchip,android", "rockchip,rk3366"; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - }; -}; - -&display_subsystem { - status = "okay"; - - logo-memory-region = <&drm_logo>; - - route { - route_dsi: route-dsi { - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vopb_out_dsi>; - status = "disabled"; - }; - - route_lvds: route-lvds { - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vopb_out_lvds>; - status = "disabled"; - }; - }; -}; - -&iep_mmu { - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&rkvdec { - status = "okay"; -}; - -&vdec_mmu { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vpu_mmu { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts b/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts deleted file mode 100644 index 4f7b0db9cfbd..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include -#include - -/ { - model = "rockchip,rk3366-fpga"; - compatible = "rockchip,rk3366"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial2 = &uart2; - }; - - chosen { - bootargs = "console=uart,mmio32,0xff690000 initrd=0x01FFFFF8,0x00800000"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x20000000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = < - GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - clocks = <&xin24m>, <&xin24m>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; - - ion { - compatible = "rockchip,ion"; - #address-cells = <1>; - #size-cells = <0>; - - cma-heap { - reg = <0x00000000 0x01000000>; - }; - - system-heap { - }; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon"; - reg = <0x0 0xff770000 0x0 0x1000>; - }; - - fb: fb { - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = ; - status = "disabled"; - }; - - rk_screen: screen { - compatible = "rockchip,screen"; - status = "disabled"; - #include - }; - - lvds: lvds@ff968000 { - compatible = "rockchip,rk3366-lvds"; - rockchip,grf = <&grf>; - reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>; - reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; - /* clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>; - * clock-names = "pclk_lvds", "pclk_lvds_ctl"; - */ - status = "disabled"; - }; - - vop_lite: vop@ff8f0000 { - compatible = "rockchip,rk3366-lcdc-lite"; - rockchip,grf = <&grf>; - rockchip,prop = ; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x0 0xff8f0000 0x0 0x1000>; - interrupts = ; - /* clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>; - * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - * resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>; - * reset-names = "axi", "ahb", "dclk"; - */ - status = "disabled"; - }; - - vopl_mmu: vopl-mmu { - dbgname = "vop"; - compatible = "rockchip,vopl_mmu"; - reg = <0x0 0xff8f0f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - status = "disabled"; - }; - - vop_big: vop@ff930000 { - compatible = "rockchip,rk3366-lcdc-big"; - rockchip,grf = <&grf>; - rockchip,prop = ; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x0 0xff930000 0x0 0x23f0>; - interrupts = ; - /* clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>; - * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - * resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>; - * reset-names = "axi", "ahb", "dclk"; - */ - status = "disabled"; - }; - - vopb_mmu: vopb-mmu { - dbgname = "vop"; - compatible = "rockchip,vopb_mmu"; - reg = <0x0 0xff932400 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - status = "disabled"; - }; - - gic: interrupt-controller@ffb70000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3366-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3366-sheep.dts deleted file mode 100644 index 30d3f38104f1..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366-sheep.dts +++ /dev/null @@ -1,885 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3366.dtsi" -#include "rk3366-android.dtsi" - -/ { - model = "Rockchip SDK sheep board"; - compatible = "rockchip,sheep", "rockchip,rk3366"; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware"; - }; - - fiq_debugger: fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - pinctrl-names = "default"; - pinctrl-0 = <&uart2_t1_xfer>; - interrupts = ; /* signal irq */ - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - }; - - dwc_control_usb: dwc-control-usb { - compatible = "rockchip,rk3368-dwc-control-usb"; - rockchip,grf = <&grf>; - grf-offset = <0x049c>; /* GRF_SOC_STATUS for USB2.0 OTG */ - interrupts = , - , - , - ; - interrupt-names = "otg_id", "otg_bvalid", - "otg_linestate", "host0_linestate"; - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>; - clock-names = "sclk_otgphy0", "otg"; - - usb_bc { - compatible = "inno,phy"; - regbase = &dwc_control_usb; - rk_usb,bvalid = <0x49c 23 1>; - rk_usb,iddig = <0x49c 26 1>; - rk_usb,vdmsrcen = <0x718 12 1>; - rk_usb,vdpsrcen = <0x718 11 1>; - rk_usb,rdmpden = <0x718 10 1>; - rk_usb,idpsrcen = <0x718 9 1>; - rk_usb,idmsinken = <0x718 8 1>; - rk_usb,idpsinken = <0x718 7 1>; - rk_usb,dpattach = <0x498 31 1>; - rk_usb,cpdet = <0x498 30 1>; - rk_usb,dcpattach = <0x498 29 1>; - }; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - ion { - compatible = "rockchip,ion"; - #address-cells = <1>; - #size-cells = <0>; - - cma-heap { - reg = <0x00000000 0x02000000>; - }; - - system-heap { - }; - }; - - io-domains { - compatible = "rockchip,rk3366-io-voltage-domain"; - rockchip,grf = <&grf>; - - lcdc-supply = <&vcc_io>; - dvpts-supply = <&vcc_18>; - wifibt-supply = <&vccio_wl>; - audio-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - tphdsor-supply = <&vcc_io>; - }; - - i2c@2 { - compatible = "i2c-gpio"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio5 16 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_gpio>; - status = "disabled"; - - mpu6050@68 { - status = "disabled"; - compatible = "invensense,mpu6050"; - pinctrl-names = "default"; - pinctrl-0 = <&mpu6500_irq_gpio>; - reg = <0x68>; - irq-gpio = <&gpio5 18 IRQ_TYPE_EDGE_RISING>; - mpu-int_config = <0x10>; - mpu-level_shifter = <0>; - mpu-orientation = <0 1 0 1 0 0 0 0 1>; - orientation-x= <0>; - orientation-y= <1>; - orientation-z= <0>; - support-hw-poweroff = <0>; - mpu-debug = <1>; - }; - }; - - i2c@4 { - compatible = "i2c-gpio"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio5 8 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_gpio>; - status = "okay"; - - gt9xx: gt9xx@14 { - compatible = "goodix,gt9xx"; - reg = <0x14>; - touch-gpio = <&gpio5 11 IRQ_TYPE_LEVEL_LOW>; - reset-gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - max-x = <1200>; - max-y = <1900>; - tp-size = <911>; - tp-supply = <&vcc_tp>; - status = "okay"; - }; - }; - - ramoops_mem: ramoops_mem { - reg = <0x0 0x100000 0x0 0x100000>; - reg-names = "ramoops_mem"; - }; - - ramoops { - compatible = "ramoops"; - record-size = <0x0 0x10000>; - console-size = <0x0 0x80000>; - ftrace-size = <0x0 0x10000>; - pmsg-size = <0x0 0x50000>; - memory-region = <&ramoops_mem>; - }; - - rk_key: rockchip-key { - compatible = "rockchip,key"; - status = "okay"; - - io-channels = <&saradc 1>; - - vol-up-key { - linux,code = <115>; - label = "volume up"; - rockchip,adc_value = <1>; - }; - - vol-down-key { - linux,code = <114>; - label = "volume down"; - rockchip,adc_value = <170>; - }; - - power-key { - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - gpio-key,wakeup; - }; - - menu-key { - linux,code = <59>; - label = "menu"; - rockchip,adc_value = <355>; - }; - - home-key { - linux,code = <102>; - label = "home"; - rockchip,adc_value = <746>; - }; - - back-key { - linux,code = <158>; - label = "back"; - rockchip,adc_value = <560>; - }; - - camera-key { - linux,code = <212>; - label = "camera"; - rockchip,adc_value = <450>; - }; - }; - - rt5640-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5640-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rt5640>; - }; - }; - - spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; - - vbus_host: vbus-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vbus_host"; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_pwr>; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk818 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; /* GPIO0_B6 */ - }; - - wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6335"; - sdio_vref = <1800>; - WIFI,host_wake_irq = <&gpio3 20 GPIO_ACTIVE_HIGH>; /* GPIO3_c4 */ - status = "okay"; - }; - - wireless-bluetooth { - compatible = "bluetooth-platdata"; - //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* GPIO3_b3 */ - pinctrl-names = "default","rts_gpio"; - pinctrl-0 = <&uart0_rts>; - pinctrl-1 = <&uart0_rts_gpio>; - //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIO3_c3 */ - BT,reset_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIO3_c3 */ - BT,wake_gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* GPIO3_c2 */ - BT,wake_host_irq = <&gpio3 21 GPIO_ACTIVE_HIGH>; /* GPIO3_c5 */ - status = "okay"; - }; -}; - -&cpu0 { - cpu-supply = <&syr827>; -}; - -&cpu1 { - cpu-supply = <&syr827>; -}; - -&cpu2 { - cpu-supply = <&syr827>; -}; - -&cpu3 { - cpu-supply = <&syr827>; -}; - -&gpu { - mali-supply = <&vdd_logic>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x25>; - rx_delay = <0x1d>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <250>; - i2c-scl-falling-time-ns = <20>; - - syr827: syr827@40 { - regulator-name = "vdd_arm"; - compatible = "silergy,syr827"; - status = "okay"; - reg = <0x40>; - regulator-compatible = "fan53555-reg"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-initial-state = <3>; - regulator-ramp-delay = <2000>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - status = "okay"; - reg = <0x1c>; - clock-output-names = "rk818-clkout1", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_codec: LDO_REG1 { - regulator-name = "vcca_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-name = "vcc_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_pmu: LDO_REG5 { - regulator-name = "vccio_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_wl: LDO_REG8 { - regulator-name = "vccio_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG9 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: SWITCH_REG { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - - battery { - compatible = "rk818-battery"; - ocv_table = <3400 3650 3693 3707 3731 3749 3760 - 3770 3782 3796 3812 3829 3852 3882 - 3915 3951 3981 4047 4086 4132 4182>; - design_capacity = <7916>; - design_qmax = <8708>; - bat_res = <65>; - max_input_current = <2000>; - max_chrg_current = <1600>; - max_chrg_voltage = <4200>; - sleep_enter_current = <300>; - sleep_exit_current = <300>; - power_off_thresd = <3400>; - zero_algorithm_vol = <3850>; - fb_temperature = <105>; - sample_res = <20>; - max_soc_offset = <60>; - energy_mode = <0>; - monitor_sec = <5>; - virtual_power = <0>; - power_dc2otg = <0>; - }; - }; -}; - -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <460>; - i2c-scl-falling-time-ns = <15>; - - rt5640: rt5640@1c { - #sound-dai-cells = <0>; - compatible = "realtek,rt5640"; - reg = <0x1c>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - realtek,in1-differential; - }; -}; - -&i2s_8ch { - status = "okay"; - rockchip,i2s-broken-burst-len; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; -}; - -&spdif { - status = "okay"; - #sound-dai-cells = <0>; -}; - -&dsi { - status = "okay"; - - panel@0 { - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - - prepare-delay-ms = <20>; - enable-delay-ms = <20>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; - dsi,format = ; - dsi,lanes = <4>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <135000000>; - hactive = <1200>; - vactive = <1920>; - hfront-porch = <80>; - hsync-len = <20>; - hback-porch = <80>; - vfront-porch = <21>; - vsync-len = <3>; - vback-porch = <21>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&rga { - status = "okay"; -}; - -&route_dsi { - status = "okay"; -}; - -&mipi_dphy { - status = "okay"; -}; - -&dwc_control_usb { - otg_drv_gpio = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO_B2 = 10 */ - - rockchip,remote_wakeup; - rockchip,usb_irq_wakeup; -}; - -&usb_host0_ehci { - assigned-clocks = <&cru SCLK_USBPHY480M>; - assigned-clock-parents = <&u2phy>; - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_otg { - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>; - clock-names = "usbphy_480m", "otg"; - resets = <&cru SRST_USBOTG_AHB>, - <&cru SRST_USBOTG_PHY>, - <&cru SRST_USBOTG_CON>; - reset-names = "otg_ahb", "otg_phy", "otg_controller"; - /* 0 - Normal, 1 - Force Host, 2 - Force Device */ - rockchip,usb-mode = <0>; - status = "okay"; -}; - -&u2phy_host { - phy-supply = <&vbus_host>; -}; - -&pinctrl { - mpu6500 { - mpu6500_irq_gpio: mpu6500-irq-gpio { - rockchip,pins = <5 18 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifienable-h { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart0_rts_gpio: uart0-rts-gpios { - rockchip,pins = <3 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pvtm { - status = "okay"; -}; - -&pmu_pvtm { - status = "okay"; -}; - -&emmc { - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - supports-emmc; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&nandc0 { - status = "okay"; /* enable both for emmc and nand */ -}; - -&sdmmc { - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - supports-sd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&sdio { - clock-frequency = <37500000>; - clock-freq-min-max = <200000 37500000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts deleted file mode 100644 index 45337f0d6fb3..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts +++ /dev/null @@ -1,903 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include -#include "rk3366.dtsi" -#include "rk3366-android-6.0.dtsi" - -/ { - model = "Rockchip SDK tb board"; - compatible = "rockchip,tb", "rockchip,rk3366"; - - chosen { - bootargs = "console=uart,mmio32,0xff690000"; - }; - - ion { - compatible = "rockchip,ion"; - #address-cells = <1>; - #size-cells = <0>; - - cma-heap { - reg = <0x00000000 0x02000000>; - }; - - system-heap { - }; - }; - - ramoops_mem: ramoops_mem { - reg = <0x0 0x100000 0x0 0x100000>; - reg-names = "ramoops_mem"; - }; - - ramoops { - compatible = "ramoops"; - record-size = <0x0 0x10000>; - console-size = <0x0 0x80000>; - ftrace-size = <0x0 0x10000>; - pmsg-size = <0x0 0x50000>; - memory-region = <&ramoops_mem>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - }; - - rk_key: rockchip-key { - compatible = "rockchip,key"; - status = "okay"; - - io-channels = <&saradc 1>; - - vol-up-key { - linux,code = <115>; - label = "volume up"; - rockchip,adc_value = <1>; - }; - - vol-down-key { - linux,code = <114>; - label = "volume down"; - rockchip,adc_value = <170>; - }; - - power-key { - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "power"; - gpio-key,wakeup; - }; - - menu-key { - linux,code = <59>; - label = "menu"; - rockchip,adc_value = <355>; - }; - - home-key { - linux,code = <102>; - label = "home"; - rockchip,adc_value = <746>; - }; - - back-key { - linux,code = <158>; - label = "back"; - rockchip,adc_value = <560>; - }; - - camera-key { - linux,code = <212>; - label = "camera"; - rockchip,adc_value = <450>; - }; - }; - - rt5640-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rt5640-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rt5640>; - }; - }; - - spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif"; - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vbus_host: vbus-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vbus_host"; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_pwr>; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - io-domains { - compatible = "rockchip,rk3366-io-voltage-domain"; - rockchip,grf = <&grf>; - - lcdc-supply = <&vcc_io>; - dvpts-supply = <&vcc_18>; - wifibt-supply = <&vccio_wl>; - audio-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - tphdsor-supply = <&vcc_io>; - }; - - dwc_control_usb: dwc-control-usb { - compatible = "rockchip,rk3368-dwc-control-usb"; - rockchip,grf = <&grf>; - grf-offset = <0x049c>; /* GRF_SOC_STATUS for USB2.0 OTG */ - interrupts = , - , - , - ; - interrupt-names = "otg_id", "otg_bvalid", - "otg_linestate", "host0_linestate"; - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>; - clock-names = "sclk_otgphy0", "otg"; - - usb_bc { - compatible = "inno,phy"; - regbase = &dwc_control_usb; - rk_usb,bvalid = <0x49c 23 1>; - rk_usb,iddig = <0x49c 26 1>; - rk_usb,vdmsrcen = <0x718 12 1>; - rk_usb,vdpsrcen = <0x718 11 1>; - rk_usb,rdmpden = <0x718 10 1>; - rk_usb,idpsrcen = <0x718 9 1>; - rk_usb,idmsinken = <0x718 8 1>; - rk_usb,idpsinken = <0x718 7 1>; - rk_usb,dpattach = <0x498 31 1>; - rk_usb,cpdet = <0x498 30 1>; - rk_usb,dcpattach = <0x498 29 1>; - }; - }; - - i2c@2 { - compatible = "i2c-gpio"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio5 16 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_gpio>; - status = "disabled"; - }; - - i2c@4 { - compatible = "i2c-gpio"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio5 8 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_gpio>; - status = "okay"; - - gt9xx: gt9xx@14 { - compatible = "goodix,gt9xx"; - reg = <0x14>; - touch-gpio = <&gpio5 11 IRQ_TYPE_LEVEL_LOW>; - reset-gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; - max-x = <1200>; - max-y = <1900>; - tp-size = <911>; - tp-supply = <&vcc_tp>; - status = "okay"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk818 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; /* GPIO0_B6 */ - }; - - wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6335"; - sdio_vref = <1800>; - WIFI,host_wake_irq = <&gpio3 20 GPIO_ACTIVE_HIGH>; /* GPIO3_c4 */ - status = "okay"; - }; - - wireless-bluetooth { - compatible = "bluetooth-platdata"; - //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* GPIO3_b3 */ - pinctrl-names = "default","rts_gpio"; - pinctrl-0 = <&uart0_rts>; - pinctrl-1 = <&uart0_rts_gpio>; - //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIO3_c3 */ - BT,reset_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIO3_c3 */ - BT,wake_gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* GPIO3_c2 */ - BT,wake_host_irq = <&gpio3 21 GPIO_ACTIVE_HIGH>; /* GPIO3_c5 */ - status = "okay"; - }; -}; - -&tsadc { - status = "okay"; -}; - -&nandc0 { - status = "okay"; /* enable both for emmc and nand */ -}; - -&emmc { - clock-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - supports-emmc; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - supports-sd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "disabled"; -}; - -&sdio { - clock-frequency = <37500000>; - clock-freq-min-max = <200000 37500000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; -}; - -&saradc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <250>; - i2c-scl-falling-time-ns = <20>; - - syr827: syr827@40 { - regulator-name = "vdd_arm"; - compatible = "silergy,syr827"; - status = "okay"; - reg = <0x40>; - regulator-compatible = "fan53555-reg"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-initial-state = <3>; - regulator-ramp-delay = <2000>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - status = "okay"; - reg = <0x1c>; - clock-output-names = "rk818-clkout1", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_codec: LDO_REG1 { - regulator-name = "vcca_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG2 { - regulator-name = "vcc_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_pmu: LDO_REG5 { - regulator-name = "vccio_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_wl: LDO_REG8 { - regulator-name = "vccio_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG9 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: SWITCH_REG { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - - battery { - compatible = "rk818-battery"; - ocv_table = <3400 3650 3693 3707 3731 3749 3760 - 3770 3782 3796 3812 3829 3852 3882 - 3915 3951 3981 4047 4086 4132 4182>; - design_capacity = <7916>; - design_qmax = <8708>; - bat_res = <65>; - max_input_current = <2000>; - max_chrg_current = <1600>; - max_chrg_voltage = <4200>; - sleep_enter_current = <300>; - sleep_exit_current = <300>; - power_off_thresd = <3400>; - zero_algorithm_vol = <3850>; - fb_temperature = <105>; - sample_res = <20>; - max_soc_offset = <60>; - energy_mode = <0>; - monitor_sec = <5>; - virtual_power = <0>; - power_dc2otg = <0>; - }; - }; -}; - -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <460>; - i2c-scl-falling-time-ns = <15>; - - rt5640: rt5640@1c { - #sound-dai-cells = <0>; - compatible = "realtek,rt5640"; - reg = <0x1c>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - realtek,in1-differential; - }; -}; - -&i2s_8ch { - status = "okay"; - rockchip,i2s-broken-burst-len; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; -}; - -&spdif { - status = "okay"; - #sound-dai-cells = <0>; -}; - -&pwm0 { - status = "okay"; -}; - -&rga { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&fb { - status = "okay"; - rockchip,disp-mode = ; - rockchip,uboot-logo-on = <0>; -}; - -&rk_screen { - status = "okay"; - #include - /* #include */ -}; - -&lvds { - pinctrl-names = "lcdc", "sleep"; - pinctrl-0 = <&lcdc_lcdc>; - pinctrl-1 = <&lcdc_gpio>; - status = "disabled"; -}; - -&dsihost0 { - status = "okay"; -}; - -&hdmi { - status = "okay"; - rockchip,hdmi_video_source = ; - rockchip,phy_table = - <148500000 0 0 17 18 18 18>, - <297000000 1 1 17 14 14 14>, - <594000000 1 1 16 5 5 5>; -}; - -&vop_lite { - status = "okay"; - rockchip,prop = ; - rockchip,mirror = ; - rockchip,cabc_mode = <0>; - rockchip,fb-win-map = ; -}; - -&vopl_mmu { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&vpu_mmu { - status = "okay"; -}; - -&vdec_mmu { - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&vpu { - status = "okay"; -}; - -&rkvdec { - status = "okay"; -}; - -&vop_big { - status = "okay"; - rockchip,prop = ; - backlight = <&backlight>; - rockchip,mirror = ; - rockchip,cabc_mode = <0>; - rockchip,fb-win-map = ; - power_ctr: power_ctr { - rockchip,debug = <0>; - lcd_en: lcd-en { - rockchip,power_type = ; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* GPIO_B4 = 12 */ - rockchip,delay = <10>; - }; - - lcd_cs: lcd-cs { - rockchip,power_type = ; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; /* GPIO_D0 = 24 */ - rockchip,delay = <10>; - }; - - /* lcd_rst: lcd-rst { - * rockchip,power_type = ; - * gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; - * rockchip,delay = <5>; - * }; - */ - }; -}; - -&vopb_mmu { - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifienable-h { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart0_rts_gpio: uart0-rts-gpios { - rockchip,pins = <3 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x25>; - rx_delay = <0x1d>; - status = "okay"; -}; - -&u2phy_host { - phy-supply = <&vbus_host>; -}; - -&dwc_control_usb { - otg_drv_gpio = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO_B2 = 10 */ - - rockchip,remote_wakeup; - rockchip,usb_irq_wakeup; -}; - -&usb_host0_ehci { - assigned-clocks = <&cru SCLK_USBPHY480M>; - assigned-clock-parents = <&u2phy>; - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_otg { - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_OTG>; - clock-names = "usbphy_480m", "otg"; - resets = <&cru SRST_USBOTG_AHB>, - <&cru SRST_USBOTG_PHY>, - <&cru SRST_USBOTG_CON>; - reset-names = "otg_ahb", "otg_phy", "otg_controller"; - /* 0 - Normal, 1 - Force Host, 2 - Force Device */ - rockchip,usb-mode = <0>; - status = "okay"; -}; - -&scr { - status = "disabled"; -}; - -&cpu0 { - cpu-supply = <&syr827>; -}; - -&gpu { - mali-supply = <&vdd_logic>; - status = "okay"; -}; - -&pvtm { - status = "okay"; -}; - -&pmu_pvtm { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi deleted file mode 100644 index 3121f43ffd18..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ /dev/null @@ -1,1970 +0,0 @@ -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3366"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <166>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "cpu_leakage"; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000 950000 1250000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1250000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000 1000000 1250000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1075000 1075000 1250000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1175000 1175000 1250000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1250000 1250000 1250000>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - gic: interrupt-controller@ffb71000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>, - <0x0 0xffb74000 0x0 0x2000>, - <0x0 0xffb76000 0x0 0x2000>; - interrupts = ; - }; - - nandc0: nandc@ff0c0000 { - compatible = "rockchip,rk-nandc"; - reg = <0x0 0xff0c0000 0x0 0x4000>; - interrupts = ; - nandc_id = <0>; - clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; - clock-names = "clk_nandc", "hclk_nandc"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff110000 0x0 0x1000>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff120000 0x0 0x1000>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scr: rkscr@ff1d0000 { - compatible = "rockchip-scr"; - reg = <0x0 0xff1d0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>; - clocks = <&cru PCLK_SIM>; - clock-names = "g_pclk_sim_card"; - status = "disabled"; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - sustainable-power = <1600>; /* milliwatts */ - - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - target: trip-point-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <115000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&target>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - }; - }; - - tsadc: tsadc@ff260000 { - compatible = "rockchip,rk3366-tsadc"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "gpio", "otpout"; - pinctrl-0 = <&tsadc_gpio>; - pinctrl-1 = <&tsadc_int>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <120000>; - status = "disabled"; - }; - - sdmmc: dwmmc@ff400000 { - compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff400000 0x0 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@ff410000 { - compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff410000 0x0 0x4000>; - status = "disabled"; - }; - - emmc: dwmmc@ff420000 { - compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff420000 0x0 0x4000>; - status = "disabled"; - }; - - gmac: eth@ff440000 { - compatible = "rockchip,rk3366-gmac"; - reg = <0x0 0xff440000 0x0 0x10000>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, - <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff728000 0x0 0x1000>; - clocks = <&cru PCLK_I2C0>; - clock-names = "i2c"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff140000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff480000 { - compatible = "generic-ehci"; - reg = <0x0 0xff480000 0x0 0x20000>; - interrupts = ; - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; - clock-names = "usbphy_480m", "hclk_host0"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff4a0000 { - compatible = "generic-ohci"; - reg = <0x0 0xff4a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>; - clock-names = "usbphy_480m", "hclk_host0"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_otg: usb@ff4c0000 { - compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff4c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - status = "disabled"; - }; - - i2c1: i2c@ff660000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - efuse: efuse@ff670000 { - compatible = "rockchip,rk3366-efuse"; - reg = <0x0 0xff670000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - - /* Data cells */ - cpu_leakage: cpu-leakage { - reg = <0x17 0x1>; - }; - gpu_leakage: gpu-leakage { - reg = <0x18 0x1>; - }; - logic_leakage: logic-leakage { - reg = <0x19 0x1>; - }; - wafer_info: wafer-info { - reg = <0x1c 0x1>; - }; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm3_t2_pin>; - clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_t1_xfer>; - status = "disabled"; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff730000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3366-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC. - * ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC. - * ACLK_ISP is on ACLK_ISP_NOC. - * ACLK_HDCP is on ACLK_HDCP_NOC. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_DPHY* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI/LVDS - */ - pd_vio@RK3366_PD_VIO { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_HDCP>, - <&cru ACLK_VOP_FULL>, - <&cru ACLK_VOP_LITE>, - <&cru ACLK_VOP_IEP>, - <&cru DCLK_VOP_FULL>, - <&cru DCLK_VOP_LITE>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VOP_FULL>, - <&cru HCLK_VOP_LITE>, - <&cru HCLK_VIO_HDCPMMU>, - <&cru PCLK_DPHYTX>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_HDCP>, - <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_VOP_FULL_PWM>, - <&cru SCLK_HDCP>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>, - <&cru SCLK_HDMI_CEC>, - <&cru SCLK_HDMI_HDCP>; - pm_qos = <&qos_iep>, <&qos_isp_r0>, - <&qos_isp_r1>, <&qos_isp_w0>, - <&qos_isp_w1>, <&qos_vop0_w>, - <&qos_rga_r>, <&qos_rga_w>, - <&qos_vop0_r>, <&qos_vop1_r>, - <&qos_hdcp>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks - * that on the ACLK_VCODEC_NOC and - * HCLK_VCODEC_NOC. - */ - pd_vpu@RK3366_PD_VPU { - reg = ; - clocks = <&cru ACLK_VIDEO>, - <&cru HCLK_VIDEO>; - pm_qos = <&qos_vpu_r>, <&qos_vpu_w>; - }; - - /* - * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC - * clocks that on the ACLK_RKVDEC_NOC and - * HCLK_RKVDEC_NOC. - */ - pd_rkvdec@RK3366_PD_RKVDEC { - reg = ; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>; - }; - - /* - * Note: ACLK_GPU is the GPU clock - * that on the ACLK_GPU_NOC. - */ - pd_gpu@RK3366_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - }; - - pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff738000 0x0 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-normal = ; - mode-recovery = ; - mode-fastboot = ; - mode-loader = ; - }; - - pmu_pvtm: pmu-pvtm { - compatible = "rockchip,rk3366-pmu-pvtm"; - clocks = <&cru SCLK_PVTM_PMU>; - clock-names = "pmu"; - status = "disabled"; - }; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC_PERI>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; - - dmac_bus: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC_BUS>; - clock-names = "apb_pclk"; - peripherals-req-type-burst; - }; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3366-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>, - <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>, - <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>, - <&cru SCLK_SPDIF_8CH_SRC>, - <&cru PLL_CPLL>, <&cru PLL_GPLL>, - <&cru PLL_NPLL>, <&cru PLL_MPLL>, - <&cru PLL_WPLL>, <&cru PLL_BPLL>, - <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>, - <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>, - <&cru ACLK_BUS>, <&cru ACLK_PERI0>, - <&cru ACLK_PERI1>; - assigned-clock-rates = - <0>, <0>, - <0>, <0>, - <0>, <0>, - <0>, - <750000000>, <576000000>, - <594000000>, <594000000>, - <960000000>, <520000000>, - <375000000>, <288000000>, - <100000000>, <100000000>, - <288000000>, <288000000>, - <144000000>; - assigned-clock-parents = - <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>, - <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>, - <&cru PLL_GPLL>, <&cru PLL_GPLL>, - <&cru PLL_GPLL>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@700 { - compatible = "rockchip,rk3366-usb2phy"; - reg = <0x700 0x2c>; - clocks = <&cru SCLK_OTG_PHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "sclk_otgphy0_480m"; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "okay"; - }; - }; - - pvtm: pvtm { - compatible = "rockchip,rk3366-pvtm"; - clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>; - clock-names = "core", "gpu"; - status = "disabled"; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - rktimer: rktimer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - spdif: spdif@ff880000 { - compatible = "rockchip,rk3366-spdif"; - reg = <0x0 0xff880000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 3>; - dma-names = "tx"; - clock-names = "mclk", "hclk"; - clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_bus>; - status = "disabled"; - }; - - i2s_2ch: i2s-2ch@ff890000 { - compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 6>, <&dmac_bus 7>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; - resets = <&cru SRST_I2S2CH>; - reset-names = "reset-m"; - status = "disabled"; - }; - - i2s_8ch: i2s-8ch@ff898000 { - compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff898000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 0>, <&dmac_bus 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; - resets = <&cru SRST_I2S8CH>; - reset-names = "reset-m"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_8ch_bus>; - status = "disabled"; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopb_out>, <&vopl_out>; - status = "disabled"; - }; - - vopl: vop@ff8f0000 { - compatible = "rockchip,rk3366-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x900>; - interrupts = ; - clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, - <&cru HCLK_VOP_LITE>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, - <&cru SRST_VOP1_AHB>; - reset-names = "axi", "ahb", "dclk"; - power-domains = <&power RK3366_PD_VIO>; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopl>; - }; - - vopl_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff8f0f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff8f0f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3366_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - iep: iep@ff900000 { - compatible = "rockchip,iep"; - iommu_enabled = <1>; - iommus = <&iep_mmu>; - reg = <0x0 0xff900000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk_iep", "hclk_iep"; - power-domains = <&power RK3366_PD_VIO>; - allocator = <1>; - version = <2>; - status = "disabled"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - power-domains = <&power RK3366_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@ff920000 { - compatible = "rockchip,rga2"; - dev_mode = <1>; - reg = <0x0 0xff920000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk_rga", "hclk_rga", "clk_rga"; - power-domains = <&power RK3366_PD_VIO>; - dma-coherent; - status = "disabled"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3366-vop"; - reg = <0x0 0xff930000 0x0 0x1ffc>; - interrupts = ; - clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, - <&cru HCLK_VOP_FULL>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3366_PD_VIO>; - resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, - <&cru SRST_VOP0_AHB>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopb>; - }; - - vopb_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_in_vopb>; - }; - - vopb_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff932400 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff932400 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3366_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - dsi: dsi@ff960000 { - compatible = "rockchip,rk3366-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x4000>; - interrupts = ; - clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>; - clock-names = "pclk", "hs_clk"; - resets = <&cru SRST_MIPIDSI0>; - reset-names = "apb"; - phys = <&mipi_dphy>; - phy-names = "mipi_dphy"; - power-domains = <&power RK3366_PD_VIO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - port { - #address-cells = <1>; - #size-cells = <0>; - - dsi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dsi>; - }; - dsi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dsi>; - }; - }; - }; - }; - - mipi_dphy: mipi-dphy@ff968000 { - compatible = "rockchip,rk3366-mipi-dphy"; - reg = <0x0 0xff968000 0x0 0x4000>; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>; - clock-names = "ref", "pclk"; - clock-output-names = "mipi_dphy_pll"; - #clock-cells = <0>; - resets = <&cru SRST_MIPIDPHYTX>; - reset-names = "apb"; - power-domains = <&power RK3366_PD_VIO>; - rockchip,grf = <&grf>; - #phy-cells = <0>; - status = "disabled"; - }; - - lvds: lvds@ff968000 { - compatible = "rockchip,rk3366-lvds"; - reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>; - reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; - clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk_lvds", "pclk_lvds_ctl"; - power-domains = <&power RK3366_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3366-dw-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - reg-io-width = <4>; - interrupts = , - ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, - <&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>; - clock-names = "iahb", "isfr", "cec", "dclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>; - resets = <&cru SRST_HDMI>; - reset-names = "hdmi"; - //power-domains = <&power RK3366_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - port { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - }; - }; - }; - - vpu: vpu_service@ff9a0000 { - compatible = "rockchip,vpu_service"; - rockchip,grf = <&grf>; - iommu_enabled = <1>; - iommus = <&vpu_mmu>; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "irq_dec", "irq_enc"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - power-domains = <&power RK3366_PD_VPU>; - resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>; - reset-names = "video_h", "video_a"; - name = "vpu_service"; - dev_mode = <0>; - /* 0 means ion, 1 means drm */ - allocator = <1>; - status = "disabled"; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3366_PD_VPU>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rkvdec: rkvdec@ff9b0000 { - compatible = "rockchip,rkvdec"; - rockchip,grf = <&grf>; - iommus = <&vdec_mmu>; - iommu_enabled = <1>; - reg = <0x0 0xff9b0000 0x0 0x400>; - interrupts = ; - interrupt-names = "irq_dec"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>; - clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; - power-domains = <&power RK3366_PD_RKVDEC>; - resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>; - reset-names = "video_h", "video_a"; - dev_mode = <2>; - name = "rkvdec"; - /* 0 means ion, 1 means drm */ - allocator = <1>; - status = "disabled"; - }; - - vdec_mmu: iommu@ff9b0480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9b0480 0x0 0x40>, - <0x0 0xff9b04c0 0x0 0x40>; - interrupts = ; - interrupt-names = "vdec_mmu"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3366_PD_RKVDEC>; - #iommu-cells = <0>; - status = "disabled"; - }; - - qos_iep: qos@ffad0000 { - compatible = "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_isp_r0: qos@ffad0080 { - compatible = "syscon"; - reg = <0x0 0xffad0080 0x0 0x20>; - }; - - qos_isp_r1: qos@ffad0100 { - compatible = "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_isp_w0: qos@ffad0180 { - compatible = "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_isp_w1: qos@ffad0200 { - compatible = "syscon"; - reg = <0x0 0xffad0200 0x0 0x20>; - }; - - qos_vop0_w: qos@ffad0300 { - compatible = "syscon"; - reg = <0x0 0xffad0300 0x0 0x20>; - }; - - qos_rga_r: qos@ffad0380 { - compatible = "syscon"; - reg = <0x0 0xffad0380 0x0 0x20>; - }; - - qos_rga_w: qos@ffad0400 { - compatible = "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vop0_r: qos@ffad0480 { - compatible = "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vop1_r: qos@ffad0580 { - compatible = "syscon"; - reg = <0x0 0xffad0580 0x0 0x20>; - }; - - qos_hdcp: qos@ffad0600 { - compatible = "syscon"; - reg = <0x0 0xffad0600 0x0 0x20>; - }; - - qos_rkvdec_r: qos@ffae0000 { - compatible = "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_rkvdec_w: qos@ffae0080 { - compatible = "syscon"; - reg = <0x0 0xffae0080 0x0 0x20>; - }; - - qos_vpu_r: qos@ffae0100 { - compatible = "syscon"; - reg = <0x0 0xffae0100 0x0 0x20>; - }; - - qos_vpu_w: qos@ffae0180 { - compatible = "syscon"; - reg = <0x0 0xffae0180 0x0 0x20>; - }; - - qos_gpu: qos@ffaf0000 { - compatible = "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3366-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <0x2>; - #size-cells = <0x2>; - ranges; - - gpio0: gpio0@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - clocks = <&cru PCLK_GPIO0>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio1: gpio1@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff758000 0x0 0x100>; - clocks = <&cru PCLK_GPIO1>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio2: gpio2@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - clocks = <&cru PCLK_GPIO2>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio3: gpio3@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO3>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio4: gpio4@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7b0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO4>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio5: gpio5@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7c0000 0x0 0x100>; - clocks = <&cru PCLK_GPIO5>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 4 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <2 26 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = - <2 27 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <2 18 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <2 18 RK_FUNC_2 &pcfg_pull_up>, - <2 19 RK_FUNC_2 &pcfg_pull_up>, - <2 20 RK_FUNC_2 &pcfg_pull_up>, - <2 21 RK_FUNC_2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <2 18 RK_FUNC_2 &pcfg_pull_up>, - <2 19 RK_FUNC_2 &pcfg_pull_up>, - <2 20 RK_FUNC_2 &pcfg_pull_up>, - <2 21 RK_FUNC_2 &pcfg_pull_up>, - <2 22 RK_FUNC_2 &pcfg_pull_up>, - <2 23 RK_FUNC_2 &pcfg_pull_up>, - <2 24 RK_FUNC_2 &pcfg_pull_up>, - <2 25 RK_FUNC_2 &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>, - <5 1 RK_FUNC_1 &pcfg_pull_up>, - <5 2 RK_FUNC_1 &pcfg_pull_up>, - <5 3 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - sdio { - sdio_bus1: sdio-bus1 { - rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>, - <3 13 RK_FUNC_1 &pcfg_pull_up>, - <3 14 RK_FUNC_1 &pcfg_pull_up>, - <3 15 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_clk: sdio-clk { - rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - sdio_cd: sdio-cd { - rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_wp: sdio-wp { - rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_int: sdio-int { - rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio_pwr: sdio-pwr { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = - <5 13 RK_FUNC_2 &pcfg_pull_none>, - <5 14 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = - <5 12 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <0 3 RK_FUNC_1 &pcfg_pull_none>, - <0 4 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <4 25 RK_FUNC_1 &pcfg_pull_none>, - <4 26 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <5 15 RK_FUNC_2 &pcfg_pull_none>, - <5 16 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2_gpio: i2c2-gpio { - rockchip,pins = - <5 15 RK_FUNC_GPIO &pcfg_pull_none>, - <5 16 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - <2 16 RK_FUNC_2 &pcfg_pull_none>, - <2 17 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = - <5 8 RK_FUNC_1 &pcfg_pull_none>, - <5 9 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2c4_gpio: i2c4-gpio { - rockchip,pins = - <5 8 RK_FUNC_GPIO &pcfg_pull_none>, - <5 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = - <5 13 RK_FUNC_1 &pcfg_pull_none>, - <5 14 RK_FUNC_1 &pcfg_pull_none>; - }; - i2c5_gpio: i2c5-gpio { - rockchip,pins = - <5 13 RK_FUNC_GPIO &pcfg_pull_none>, - <5 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2s { - i2s_8ch_bus: i2s-8ch-bus { - rockchip,pins = - <4 16 RK_FUNC_1 &pcfg_pull_none>, - <4 17 RK_FUNC_1 &pcfg_pull_none>, - <4 18 RK_FUNC_1 &pcfg_pull_none>, - <4 19 RK_FUNC_1 &pcfg_pull_none>, - <4 20 RK_FUNC_1 &pcfg_pull_none>, - <4 21 RK_FUNC_1 &pcfg_pull_none>, - <4 22 RK_FUNC_1 &pcfg_pull_none>, - <4 23 RK_FUNC_1 &pcfg_pull_none>, - <4 24 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_bus: spdif-bus { - rockchip,pins = - <5 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 29 RK_FUNC_2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = - <2 24 RK_FUNC_3 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = - <2 25 RK_FUNC_3 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = - <2 23 RK_FUNC_3 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = - <2 22 RK_FUNC_3 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <2 4 RK_FUNC_3 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = - <2 5 RK_FUNC_3 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = - <2 6 RK_FUNC_3 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = - <2 7 RK_FUNC_3 &pcfg_pull_up>; - }; - }; - - scr { - scr_clk: scr-clk { - rockchip,pins = - <5 8 RK_FUNC_2 &pcfg_pull_none>; - }; - - scr_io: scr-io { - rockchip,pins = - <5 9 RK_FUNC_2 &pcfg_pull_up>; - }; - - scr_rst: scr-rst { - rockchip,pins = - <5 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - scr_detect: scr-detect { - rockchip,pins = - <5 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <3 8 RK_FUNC_1 &pcfg_pull_up>, - <3 9 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <3 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <3 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2_t0 { - uart2_t0_xfer: uart2_t0-xfer { - rockchip,pins = - <0 22 RK_FUNC_1 &pcfg_pull_up>, - <0 21 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart2_t1 { - uart2_t1_xfer: uart2_t1-xfer { - rockchip,pins = - <5 0 RK_FUNC_2 &pcfg_pull_up>, - <5 1 RK_FUNC_2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart2_t2 { - uart2_t2_xfer: uart2_t2-xfer { - rockchip,pins = - <5 14 RK_FUNC_3 &pcfg_pull_up>, - <5 13 RK_FUNC_3 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <5 15 RK_FUNC_1 &pcfg_pull_up>, - <5 16 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = - <5 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = - <5 18 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 8 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <1 6 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2_t0 { - pwm2_t0_pin: pwm2_t0-pin { - rockchip,pins = - <2 15 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - pwm2_t1 { - pwm2_t1_pin: pwm2_t1-pin { - rockchip,pins = - <5 17 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3_t0 { - pwm3_t0_pin: pwm3_t0-pin { - rockchip,pins = - <1 0 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3_t1 { - pwm3_t1_pin: pwm3_t1-pin { - rockchip,pins = - <0 21 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3_t2 { - pwm3_t2_pin: pwm3_t2-pin { - rockchip,pins = - <5 18 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_lcdc: lcdc-lcdc { - rockchip,pins = - <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */ - <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */ - <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */ - <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */ - <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */ - <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */ - <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */ - <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */ - <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */ - <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */ - <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */ - <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */ - <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */ - <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */ - <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */ - <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */ - <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */ - <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */ - }; - - lcdc_gpio: lcdc-gpio { - rockchip,pins = - <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */ - <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */ - <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ - <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ - <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ - <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ - <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ - <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ - <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ - <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ - <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ - <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ - <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ - <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ - <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ - <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */ - <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */ - <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */ - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = - /* mac_rxd3 */ - <2 7 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd2 */ - <2 6 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd3 */ - <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd2 */ - <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_rxd1 */ - <2 3 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <2 2 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <2 0 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txclkout */ - <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_crs */ - /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */ - /* mac_rxclkin */ - <2 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdio */ - <2 13 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_clk */ - <2 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxer */ - /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */ - /* mac_rxdv */ - <2 9 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <2 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_rxd1 */ - <2 3 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <2 2 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <2 1 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd0 */ - <2 0 RK_FUNC_1 &pcfg_pull_none>, - /* mac_crs */ - /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */ - /* mac_rxclkin */ - <2 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdio */ - <2 13 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <2 12 RK_FUNC_1 &pcfg_pull_none>, - /* mac_clk */ - <2 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxer */ - /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */ - /* mac_rxdv */ - <2 9 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <2 8 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = - <0 25 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tsadc_pin { - tsadc_gpio: tsadc-gpio { - rockchip,pins = - <0 22 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - tsadc_int: tsadc-int { - rockchip,pins = - <0 22 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <0 16 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - }; - - gpu: gpu@ffa30000 { - compatible = "arm,malit764", - "arm,malit76x", - "arm,malit7xx", - "arm,mali-midgard"; - - reg = <0x0 0xffa30000 0 0x10000>; - - interrupts = , - , - ; - interrupt-names = "GPU", "MMU", "JOB"; - - clocks = <&cru ACLK_GPU>; - clock-names = "clk_mali"; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3366_PD_GPU>; - operating-points-v2 = <&gpu_opp_table>; - status = "disabled"; - - power_model { - compatible = "arm,mali-simple-power-model"; - voltage = <900>; - frequency = <500>; - static-power = <300>; - dynamic-power = <1780>; - ts = <32000 4700 (-80) 2>; - thermal-zone = "gpu-thermal"; - }; - }; - - gpu_opp_table: gpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-96000000 { - opp-hz = /bits/ 64 <96000000>; - opp-microvolt = <1100000>; - }; - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <1100000>; - }; - opp-288000000 { - opp-hz = /bits/ 64 <288000000>; - opp-microvolt = <1100000>; - }; - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - opp-microvolt = <1125000>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1200000>; - }; - }; -}; diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index bec6ea102904..7dc2c435a878 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -24,6 +24,5 @@ obj-$(CONFIG_CPU_RK322X) += clk-rk3228.o obj-$(CONFIG_CPU_RK3288) += clk-rk3288.o obj-$(CONFIG_CPU_RK3308) += clk-rk3308.o obj-$(CONFIG_CPU_RK3328) += clk-rk3328.o -obj-$(CONFIG_CPU_RK3366) += clk-rk3366.o obj-$(CONFIG_CPU_RK3368) += clk-rk3368.o obj-$(CONFIG_CPU_RK3399) += clk-rk3399.o diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c deleted file mode 100644 index 89bcd1e32b64..000000000000 --- a/drivers/clk/rockchip/clk-rk3366.c +++ /dev/null @@ -1,877 +0,0 @@ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Xiao Feng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "clk.h" - -#define RK3366_GRF_SOC_STATUS0 0x480 -#define RK3366_I2S_FRAC_MAX_PRATE 600000000 -#define RK3366_UART_FRAC_MAX_PRATE 600000000 -#define RK3366_SPDIF_FRAC_MAX_PRATE 600000000 - -enum rk3366_plls { - apll, dpll, cpll, gpll, npll, mpll, wpll, bpll, -}; - -static struct rockchip_pll_rate_table rk3366_pll_rates[] = { - /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ - RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), - RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), - RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), - RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), - RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), - RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), - RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), - RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), - RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), - RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), - RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), - RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), - RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), - RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), - RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), - RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), - RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), - RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), - RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), - RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), - RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), - RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), - RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), - RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), - RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), - RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), - RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), - RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), - RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), - RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), - RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), - RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), - RK3036_PLL_RATE( 750000000, 2, 125, 2, 1, 1, 0), - RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), - RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), - RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), - RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), - RK3036_PLL_RATE( 576000000, 1, 96, 4, 1, 1, 0), - RK3036_PLL_RATE( 520000000, 1, 65, 3, 1, 1, 0), - RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), - RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), - RK3036_PLL_RATE( 480000000, 1, 80, 4, 1, 1, 0), - RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), - RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), - RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), - RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), - - { /* sentinel */ }, -}; - -PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; -PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; -PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" }; -PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; -PNAME(mux_pll_src_dmynpll_cpll_gpll_gpll_p) = { "dummy_npll", "cpll", "gpll", "gpll" }; -PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" }; -PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m", - "usbphy_480m" }; -PNAME(mux_pll_src_cpll_gpll_usb_dmynpll_p) = { "cpll", "gpll", "usbphy_480m", - "dummy_npll" }; -PNAME(mux_pll_src_cpll_gpll_dmynpll_dmynpll_p) = { "cpll", "gpll", "dummy_npll", "dummy_npll" }; -PNAME(mux_pll_src_cpll_gpll_dmynpll_usb_p) = { "cpll", "gpll", "dummy_npll", - "usbphy_480m" }; -PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll_src" }; -PNAME(mux_vop_full_pwm_p) = { "xin24m", "cpll", "gpll", "dummy_npll" }; -PNAME(mux_clk_32k_p) = { "xin32k", "clk_32k_intr" }; -PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac", - "ext_i2s", "xin12m" }; -PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" }; -PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac", - "dummy", "xin12m" }; -PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", - "ext_i2s", "xin12m" }; -PNAME(mux_vip_out_p) = { "vip_src", "xin24m" }; -PNAME(mux_usb3_suspend_p) = { "clk_32k", "xin24m" }; -PNAME(mux_usbphy480m_p) = { "xin24m", "sclk_otgphy0_480m" }; -PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m", "xin24m" }; -PNAME(mux_uart2_p) = { "uart2_src", "xin24m" }; -PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m", "xin24m" }; -PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; -PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" }; -PNAME(mux_bt_p) = { "bpll", "btclk520_pll" }; -PNAME(mux_wifi_pll_p) = { "wpll_wiff", "usbphy_480m_wifi" }; - -static struct rockchip_pll_clock rk3366_pll_clks[] __initdata = { - [apll] = PLL(pll_rk3366, PLL_APLL, "apll", mux_pll_p, 0, RK3368_PLL_CON(0), - RK3368_PLL_CON(3), 8, 0, 0, rk3366_pll_rates), - [dpll] = PLL(pll_rk3366, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8), - RK3368_PLL_CON(11), 8, 1, 0, NULL), - [cpll] = PLL(pll_rk3366, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12), - RK3368_PLL_CON(15), 8, 2, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), - [gpll] = PLL(pll_rk3366, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16), - RK3368_PLL_CON(19), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), - [npll] = PLL(pll_rk3366, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20), - RK3368_PLL_CON(23), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), - [mpll] = PLL(pll_rk3366, PLL_MPLL, "mpll", mux_pll_p, 0, RK3368_PLL_CON(24), - RK3368_PLL_CON(27), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), - [wpll] = PLL(pll_rk3366, PLL_WPLL, "wpll", mux_pll_p, 0, RK3368_PLL_CON(28), - RK3368_PLL_CON(31), 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), - [bpll] = PLL(pll_rk3366, PLL_BPLL, "bpll", mux_pll_p, 0, RK3368_PLL_CON(32), - RK3368_PLL_CON(35), 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates), -}; - -static struct clk_div_table div_ddrphy_t[] = { - { .val = 0, .div = 1 }, - { .val = 1, .div = 2 }, - { .val = 3, .div = 4 }, - { /* sentinel */ }, -}; - -#define MFLAGS CLK_MUX_HIWORD_MASK -#define DFLAGS CLK_DIVIDER_HIWORD_MASK -#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) -#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK - -static const struct rockchip_cpuclk_reg_data rk3366_cpuclk_data = { - .core_reg = RK3368_CLKSEL_CON(0), - .div_core_shift = 0, - .div_core_mask = 0x1f, - .mux_core_alt = 1, - .mux_core_main = 0, - .mux_core_shift = 6, - .mux_core_mask = 0x1, -}; - -#define RK3366_DIV_ACLKM_MASK 0x1f -#define RK3366_DIV_ACLKM_SHIFT 8 -#define RK3366_DIV_ATCLK_MASK 0x1f -#define RK3366_DIV_ATCLK_SHIFT 0 -#define RK3366_DIV_PCLK_DBG_MASK 0x1f -#define RK3366_DIV_PCLK_DBG_SHIFT 8 - -#define RK3366_CLKSEL0(_offs, _aclkm) \ - { \ - .reg = RK3368_CLKSEL_CON(0 + _offs), \ - .val = HIWORD_UPDATE(_aclkm, RK3366_DIV_ACLKM_MASK, \ - RK3366_DIV_ACLKM_SHIFT), \ - } -#define RK3366_CLKSEL1(_offs, _atclk, _pdbg) \ - { \ - .reg = RK3368_CLKSEL_CON(1 + _offs), \ - .val = HIWORD_UPDATE(_atclk, RK3366_DIV_ATCLK_MASK, \ - RK3366_DIV_ATCLK_SHIFT) | \ - HIWORD_UPDATE(_pdbg, RK3366_DIV_PCLK_DBG_MASK, \ - RK3366_DIV_PCLK_DBG_SHIFT), \ - } - -/* cluster_b: aclkm in clksel0, rest in clksel1 */ -#define RK3366_CPUCLK_RATE(_prate, _aclkm, _atclk, _pdbg) \ - { \ - .prate = _prate, \ - .divs = { \ - RK3366_CLKSEL0(0, _aclkm), \ - RK3366_CLKSEL1(0, _atclk, _pdbg), \ - }, \ - } - -static struct rockchip_cpuclk_rate_table rk3366_cpuclk_rates[] __initdata = { - RK3366_CPUCLK_RATE(1512000000, 1, 5, 5), - RK3366_CPUCLK_RATE(1488000000, 1, 4, 4), - RK3366_CPUCLK_RATE(1416000000, 1, 4, 4), - RK3366_CPUCLK_RATE(1296000000, 1, 4, 4), - RK3366_CPUCLK_RATE(1200000000, 1, 3, 3), - RK3366_CPUCLK_RATE(1104000000, 1, 3, 3), - RK3366_CPUCLK_RATE(1008000000, 1, 3, 3), - RK3366_CPUCLK_RATE( 816000000, 1, 2, 2), - RK3366_CPUCLK_RATE( 696000000, 1, 2, 2), - RK3366_CPUCLK_RATE( 600000000, 1, 1, 1), - RK3366_CPUCLK_RATE( 408000000, 1, 1, 1), - RK3366_CPUCLK_RATE( 312000000, 1, 1, 1), - RK3366_CPUCLK_RATE( 216000000, 1, 1, 1), -}; - -static struct rockchip_clk_branch rk3366_i2s_8ch_fracmux __initdata = - MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(27), 8, 2, MFLAGS); - -static struct rockchip_clk_branch rk3366_spdif_8ch_fracmux __initdata = - MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(31), 8, 2, MFLAGS); - -static struct rockchip_clk_branch rk3366_i2s_2ch_fracmux __initdata = - MUX(0, "i2s_2ch_mux", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(53), 8, 2, MFLAGS); - -static struct rockchip_clk_branch rk3366_uart0_fracmux __initdata = - MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(33), 8, 2, MFLAGS); - -static struct rockchip_clk_branch rk3366_uart3_fracmux __initdata = - MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(39), 8, 2, MFLAGS); - -static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = { - /* - * Clock-Architecture Diagram 1 - */ - - GATE(SCLK_MPLL_SRC, "mpll_src", "mpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(2), 11, GFLAGS), - - /* - * Clock-Architecture Diagram 2 - */ - - MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, 0, - RK3368_CLKSEL_CON(13), 6, 1, MFLAGS), - - DIV(SCLK_32K_INTR, "clk_32k_intr", "xin24m", 0, - RK3368_CLKSEL_CON(7), 0, 10, DFLAGS), - MUX(SCLK_32K, "clk_32k", mux_clk_32k_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(7), 15, 1, MFLAGS), - - GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(0), 0, GFLAGS), - GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(0), 1, GFLAGS), - GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(0), 2, GFLAGS), - - DIV(0, "aclkm_core", "armclk", 0, - RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY), - DIV(0, "atclk_core", "armclk", 0, - RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY), - DIV(0, "pclk_dbg", "armclk", 0, - RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY), - - COMPOSITE_NOMUX(0, "sclk_cs_pre", "armclk", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(4), 0, 5, DFLAGS, - RK3368_CLKGATE_CON(0), 11, GFLAGS), - COMPOSITE_NOMUX(0, "clkin_trace", "armclk", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(14), 8, 5, DFLAGS, - RK3368_CLKGATE_CON(0), 13, GFLAGS), - - GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, - RK3368_CLKGATE_CON(7), 10, GFLAGS), - - GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(1), 8, GFLAGS), - GATE(0, "gpll_ddr", "gpll", 0, - RK3368_CLKGATE_CON(1), 9, GFLAGS), - GATE(0, "apll_ddr", "apll", 0, - RK3368_CLKGATE_CON(1), 7, GFLAGS), - COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(13), 4, 2, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t), - - GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(1), 10, GFLAGS), - GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(1), 11, GFLAGS), - COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS), - - GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(1), 0, GFLAGS), - COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(8), 12, 3, DFLAGS, - RK3368_CLKGATE_CON(1), 2, GFLAGS), - COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(8), 8, 2, DFLAGS, - RK3368_CLKGATE_CON(1), 1, GFLAGS), - - COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(7), 2, GFLAGS), - - COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(1), 3, GFLAGS), - - COMPOSITE(SCLK_I2S_8CH_SRC, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(6), 1, GFLAGS), - COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(28), 0, - RK3368_CLKGATE_CON(6), 2, GFLAGS, - &rk3366_i2s_8ch_fracmux, RK3366_I2S_FRAC_MAX_PRATE), - COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0, - RK3368_CLKSEL_CON(27), 15, 1, MFLAGS, - RK3368_CLKGATE_CON(6), 0, GFLAGS), - GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT, - RK3368_CLKGATE_CON(6), 3, GFLAGS), - - COMPOSITE(SCLK_SPDIF_8CH_SRC, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(6), 4, GFLAGS), - COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(32), 0, - RK3368_CLKGATE_CON(6), 5, GFLAGS, - &rk3366_spdif_8ch_fracmux, RK3366_SPDIF_FRAC_MAX_PRATE), - GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, - RK3368_CLKGATE_CON(6), 6, GFLAGS), - - COMPOSITE(SCLK_I2S_2CH_SRC, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(5), 13, GFLAGS), - COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(54), 0, - RK3368_CLKGATE_CON(5), 14, GFLAGS, - &rk3366_i2s_2ch_fracmux, RK3366_I2S_FRAC_MAX_PRATE), - GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_mux", CLK_SET_RATE_PARENT, - RK3368_CLKGATE_CON(5), 15, GFLAGS), - - /* - * Clock-Architecture Diagram 3 - */ - - MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(35), 12, 1, MFLAGS), - COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0, - RK3368_CLKSEL_CON(37), 0, 7, DFLAGS, - RK3368_CLKGATE_CON(2), 4, GFLAGS), - MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(37), 8, 1, MFLAGS), - - COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0, - RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0, - RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 7, GFLAGS), - - /* - * We introduce a virtual node of hclk_vodec_pre_v to split one clock - * struct with a gate and a fix divider into two node in software. - */ - GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0, - RK3368_CLKGATE_CON(4), 8, GFLAGS), - - COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0, - RK3368_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3368_CLKGATE_CON(5), 8, GFLAGS), - - /* - * We introduce a virtual node of hclk_rkvdec_pre_v to split one clock - * struct with a gate and a fix divider into two node in software. - */ - GATE(0, "hclk_rkvdec_pre_v", "aclk_rkvdec_pre", 0, - RK3368_CLKGATE_CON(5), 9, GFLAGS), - - COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0, - RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(5), 1, GFLAGS), - COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_dmynpll_usb_p, 0, - RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3368_CLKGATE_CON(5), 2, GFLAGS), - - COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 0, GFLAGS), - DIV(0, "hclk_vio", "aclk_vio0", 0, - RK3368_CLKSEL_CON(21), 0, 5, DFLAGS), - - COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0, - RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 3, GFLAGS), - COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0, - RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 4, GFLAGS), - - COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_cpll_gpll_usb_p, 0, - RK3368_CLKSEL_CON(16), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 15, GFLAGS), - - COMPOSITE(DCLK_VOP_FULL, "dclk_vop_full", mux_pll_src_cpll_gpll_npll_mpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3368_CLKGATE_CON(4), 1, GFLAGS), - - COMPOSITE(SCLK_VOP_FULL_PWM, "sclk_vop_full_pwm", mux_vop_full_pwm_p, 0, - RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS, - RK3368_CLKGATE_CON(4), 2, GFLAGS), - - COMPOSITE(DCLK_VOP_LITE, "dclk_vop_lite", mux_pll_src_cpll_gpll_npll_mpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, - RK3368_CLKSEL_CON(24), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3368_CLKGATE_CON(5), 6, GFLAGS), - - COMPOSITE_NOMUX(DCLK_HDMIPHY, "dclk_hdmiphy", "mpll_src", 0, - RK3368_CLKSEL_CON(16), 8, 8, DFLAGS, - RK3368_CLKGATE_CON(5), 7, GFLAGS), - - COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0, - RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS, - RK3368_CLKGATE_CON(4), 9, GFLAGS), - - GATE(PCLK_ISP, "pclk_isp", "ext_isp", 0, - RK3368_CLKGATE_CON(17), 2, GFLAGS), - - GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, - RK3368_CLKGATE_CON(4), 13, GFLAGS), - GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "clk_32k", 0, - RK3368_CLKGATE_CON(4), 12, GFLAGS), - - MUX(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(21), 15, 1, MFLAGS), - COMPOSITE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, - RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 5, GFLAGS), - - GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS), - - /* - * Clock-Architecture Diagram 4 - */ - - COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0, - RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS, - RK3368_CLKGATE_CON(5), 5, GFLAGS), - - DIV(0, "pclk_pd_alive", "gpll", 0, - RK3368_CLKSEL_CON(10), 8, 5, DFLAGS), - - /* sclk_timer has a gate in the sgrf */ - - COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(10), 0, 5, DFLAGS, - RK3368_CLKGATE_CON(7), 9, GFLAGS), - GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0, - RK3368_CLKGATE_CON(7), 3, GFLAGS), - - COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_dmynpll_p, 0, - RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(4), 11, GFLAGS), - GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, - RK3368_CLKGATE_CON(7), 11, GFLAGS), - - COMPOSITE(0, "aclk_peri0_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(3), 0, GFLAGS), - COMPOSITE_NOMUX(PCLK_PERI0, "pclk_peri0", "aclk_peri0_src", 0, - RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, - RK3368_CLKGATE_CON(3), 3, GFLAGS), - COMPOSITE_NOMUX(HCLK_PERI0, "hclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, - RK3368_CLKGATE_CON(3), 2, GFLAGS), - GATE(ACLK_PERI0, "aclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(3), 1, GFLAGS), - - COMPOSITE(0, "aclk_peri1_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(3), 10, GFLAGS), - COMPOSITE_NOMUX(PCLK_PERI1, "pclk_peri1", "aclk_peri1_src", 0, - RK3368_CLKSEL_CON(11), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, - RK3368_CLKGATE_CON(3), 13, GFLAGS), - COMPOSITE_NOMUX(HCLK_PERI1, "hclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED, - RK3368_CLKSEL_CON(11), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, - RK3368_CLKGATE_CON(3), 12, GFLAGS), - GATE(ACLK_PERI1, "aclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(3), 11, GFLAGS), - - GATE(SCLK_USB3_REF, "sclk_usb3_ref", "xin24m", 0, - RK3368_CLKGATE_CON(3), 15, GFLAGS), - - COMPOSITE(SCLK_USB3_SUSPEND, "sclk_usb3_suspend", mux_usb3_suspend_p, 0, - RK3368_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 8, DFLAGS, - RK3368_CLKGATE_CON(3), 14, GFLAGS), - - /* ref_alt_clk_p has a mux in the grf */ - - /* - * Clock-Architecture Diagram 5 - */ - - COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(3), 7, GFLAGS), - COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS, - RK3368_CLKGATE_CON(3), 8, GFLAGS), - COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS, - RK3368_CLKGATE_CON(3), 9, GFLAGS), - - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, - RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(7), 12, GFLAGS), - COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0, - RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(7), 13, GFLAGS), - COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, - RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(7), 15, GFLAGS), - - MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0), - - MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1), - MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0), - - MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1), - MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0), - - GATE(SCLK_OTG_PHY0, "sclk_otg_phy0", "xin24m", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(8), 1, GFLAGS), - - GATE(SCLK_OTG_ADP, "sclk_otg_adp", "clk_32k", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(8), 4, GFLAGS), - - GATE(SCLK_TSADC, "sclk_tsadc", "clk_32k", 0, - RK3368_CLKGATE_CON(3), 5, GFLAGS), - - COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, - RK3368_CLKSEL_CON(25), 8, 8, DFLAGS, - RK3368_CLKGATE_CON(3), 6, GFLAGS), - - COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(7), 8, GFLAGS), - - COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0, - RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(6), 7, GFLAGS), - - COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0, - RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS, - RK3368_CLKGATE_CON(2), 0, GFLAGS), - COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(34), 0, - RK3368_CLKGATE_CON(2), 1, GFLAGS, - &rk3366_uart0_fracmux, RK3366_UART_FRAC_MAX_PRATE), - - COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, - RK3368_CLKSEL_CON(39), 0, 7, DFLAGS, - RK3368_CLKGATE_CON(2), 6, GFLAGS), - COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(40), 0, - RK3368_CLKGATE_CON(2), 7, GFLAGS, - &rk3366_uart3_fracmux, RK3366_UART_FRAC_MAX_PRATE), - - /* - * Clock-Architecture Diagram 6 - */ - - COMPOSITE(0, "mac_pll_src", mux_pll_src_dmynpll_cpll_gpll_gpll_p, 0, - RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS, - RK3368_CLKGATE_CON(3), 4, GFLAGS), - MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(43), 8, 1, MFLAGS), - GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0, - RK3368_CLKGATE_CON(7), 7, GFLAGS), - GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0, - RK3368_CLKGATE_CON(7), 6, GFLAGS), - GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0, - RK3368_CLKGATE_CON(7), 4, GFLAGS), - GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0, - RK3368_CLKGATE_CON(7), 5, GFLAGS), - - GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, - RK3368_CLKGATE_CON(7), 0, GFLAGS), - - /* - * Clock-Architecture Diagram 7 - */ - - COMPOSITE_NODIV(0, "btclk520_pll", mux_pll_src_cpll_gpll_dmynpll_dmynpll_p, 0, - RK3368_CLKSEL_CON(5), 13, 2, MFLAGS, - RK3368_CLKGATE_CON(2), 10, GFLAGS), - MUX(0, "clk_bt_pll", mux_bt_p, 0, - RK3368_CLKSEL_CON(5), 15, 1, MFLAGS), - COMPOSITE_NOMUX(SCLK_BT_52, "sclk_bt_520", "clk_bt_pll", 0, - RK3368_CLKSEL_CON(5), 0, 5, DFLAGS, - RK3368_CLKGATE_CON(8), 13, GFLAGS), - DIV(0, "pclk_btbb", "sclk_bt_520", 0, - RK3368_CLKSEL_CON(5), 10, 3, DFLAGS), - COMPOSITE_NOMUX(SCLK_BT_M0, "sclk_bt_m0", "clk_bt_pll", 0, - RK3368_CLKSEL_CON(5), 5, 5, DFLAGS, - RK3368_CLKGATE_CON(8), 14, GFLAGS), - - GATE(SCLK_WIFI_WPLL, "wpll_wiff", "wpll", 0, - RK3368_CLKGATE_CON(8), 11, GFLAGS), - GATE(SCLK_WIFI_USBPHY480M, "usbphy_480m_wifi", "usbphy_480m", 0, - RK3368_CLKGATE_CON(8), 11, GFLAGS), - COMPOSITE(SCLK_WIFIDSP, "sclk_wifidsp", mux_wifi_pll_p, 0, - RK3368_CLKSEL_CON(13), 15, 1, MFLAGS, 10, 5, DFLAGS, - RK3368_CLKGATE_CON(8), 12, GFLAGS), - DIV(0, "hclk_wifi", "sclk_wifidsp", CLK_SET_RATE_PARENT, - RK3368_CLKSEL_CON(13), 7, 3, DFLAGS), - - /* - * Clock-Architecture Diagram 8 - */ - - /* pclk_pd_pmu gates*/ - GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS), - GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS), - GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS), - GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS), - GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 4, GFLAGS), - GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS), - GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 6, GFLAGS), - - /* fclk_mcu_src gates */ - GATE(0, "fclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 7, GFLAGS), - GATE(0, "hclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 8, GFLAGS), - GATE(0, "hclk_mcu_noc", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 9, GFLAGS), - - /* pclk_pd_alive gates */ - GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS), - GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS), - GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS), - GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 4, GFLAGS), - GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 5, GFLAGS), - GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS), - GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS), - GATE(PCLK_DPHYTX, "pclk_dphytx", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 10, GFLAGS), - GATE(PCLK_DPHYRX, "pclk_dphyrx", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 11, GFLAGS), - GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS), - - /* pclk_cpu gates */ - GATE(PCLK_DMFIMON, "pclk_dmfimon", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 0, GFLAGS), - GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS), - GATE(PCLK_DFC, "pclk_dfc", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS), - GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS), - GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS), - GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS), - GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS), - GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS), - GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS), - GATE(PCLK_RKPWM, "pclk_rk_pwm", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS), - GATE(0, "pclk_ddrnoc", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 10, GFLAGS), - GATE(0, "pclk_ddr_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 11, GFLAGS), - - /* hclk_cpu gates */ - GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS), - GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS), - GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS), - GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS), - GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS), - GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS), - - /* aclk_bus gates */ - GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS), - GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS), - GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS), - GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS), - GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS), - GATE(ACLK_DFC, "aclk_dfc", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 15, GFLAGS), - GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS), - - /* clk_ddrphy gates */ - GATE(0, "clk_ddrupctl", "ddrphy_div4", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS), - - /* clk_cs_pre gates */ - GATE(0, "sclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS), - GATE(0, "hclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS), - GATE(0, "pclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 2, GFLAGS), - - /* armclk gates */ - GATE(0, "clk_core_cxcs", "armclk", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 3, GFLAGS), - - /* aclkm_core gates */ - GATE(0, "aclk_core_noc", "aclkm_core", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 4, GFLAGS), - - /* gpu gates */ - GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS), - GATE(ACLK_GPU_NOC, "aclk_gpu_noc", "sclk_gpu_core_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(18), 1, GFLAGS), - - /* aclk_peri0 gates */ - GATE(0, "aclk_peri0_axi_matrix", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS), - GATE(ACLK_USB3, "aclk_usb3", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS), - GATE(0, "aclk_peri0_noc", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS), - GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri0", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS), - - /* hclk_peri0 gates */ - GATE(HCLK_OTG, "hclk_otg", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS), - GATE(HCLK_HOST, "hclk_host", "hclk_peri0", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS), - GATE(0, "hclk_host_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS), - GATE(0, "hclk_peri0_ahb_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS), - GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS), - GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS), - GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS), - - /* pclk_peri0 gates */ - GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri0", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS), - - /* aclk_peri1 gates */ - GATE(0, "aclk_peri1_axi_matrix", "aclk_peri1", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS), - GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri1", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS), - - /* hclk_peri1 gates */ - GATE(0, "hclk_peri1_ahb_arbiter", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 8, GFLAGS), - GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS), - GATE(HCLK_SFC, "hclk_sfc", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS), - - /* pclk_peri1 gates */ - GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS), - GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS), - GATE(PCLK_UART0, "pclk_uart0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS), - GATE(PCLK_UART3, "pclk_uart3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS), - GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS), - GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS), - GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS), - GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS), - GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS), - GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri1", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS), - GATE(PCLK_SIM, "pclk_sim", "pclk_peri1", 0, RK3368_CLKGATE_CON(21), 7, GFLAGS), - - /* - * video clk gates - * aclk_video(_pre) can actually select between parents of aclk_vdpu - * and aclk_vepu by setting bit GRF_SOC_CON0[7]. - */ - GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS), - GATE(0, "aclk_video_noc", "aclk_vdpu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 4, GFLAGS), - GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS), - GATE(0, "hclk_video_noc", "hclk_video_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 5, GFLAGS), - - GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 6, GFLAGS), - GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 2, GFLAGS), - GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 3, GFLAGS), - GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 7, GFLAGS), - - /* aclk_rga_pre gates */ - GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS), - GATE(0, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS), - GATE(ACLK_VOP_LITE, "aclk_vop_lite", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 13, GFLAGS), - - /* aclk_vio0 gates */ - GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS), - GATE(ACLK_VOP_FULL, "aclk_vop_full", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS), - GATE(0, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS), - GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS), - - /* sclk_isp gates */ - GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS), - GATE(0, "hclk_isp_noc", "sclk_isp", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS), - GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS), - - /* aclk_hdcp_pre gates */ - GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS), - GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 15, GFLAGS), - - /* hclk_vio gates */ - GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS), - GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS), - GATE(HCLK_VOP_FULL, "hclk_vop_full", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS), - GATE(HCLK_VIO_AHB_ARBITER, "hclk_vio_ahb_arbiter", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS), - GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS), - GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS), - GATE(HCLK_VOP_LITE, "hclk_vop_lite", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 14, GFLAGS), - GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS), - GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS), - GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS), - GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS), - GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS), - - /* timer gates */ - GATE(SCLK_TIMER5, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS), - GATE(SCLK_TIMER4, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS), - GATE(SCLK_TIMER3, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS), - GATE(SCLK_TIMER2, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS), - GATE(SCLK_TIMER1, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS), - GATE(SCLK_TIMER0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS), -}; - -static const char *const rk3366_critical_clocks[] __initconst = { - "aclk_bus", - "aclk_peri0", - "aclk_peri1", - "aclk_video_noc", - "aclk_rkvdec_noc", - "hclk_peri0", - "hclk_peri1", - "hclk_video_noc", - "hclk_rkvdec_noc", - "pclk_peri0", - "pclk_peri1", - "pclk_rk_pwm", - "pclk_pd_pmu", - "aclk_dmac_bus", -}; - -static void __init rk3366_clk_init(struct device_node *np) -{ - struct rockchip_clk_provider *ctx; - void __iomem *reg_base; - struct clk *clk; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: could not map cru region\n", __func__); - return; - } - - ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); - if (IS_ERR(ctx)) { - pr_err("%s: rockchip clk init failed\n", __func__); - iounmap(reg_base); - return; - } - - /* xin12m is created by a cru-internal divider */ - clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - /* ddrphy_div4 is created by a cru-internal divider */ - clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock xin12m: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_register_fixed_factor(NULL, "hclk_video_pre", - "hclk_video_pre_v", 0, 1, 4); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", - __func__, PTR_ERR(clk)); - - clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre", - "hclk_rkvdec_pre_v", 0, 1, 4); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n", - __func__, PTR_ERR(clk)); - - /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */ - clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); - if (IS_ERR(clk)) - pr_warn("%s: could not register clock pclk_wdt: %ld\n", - __func__, PTR_ERR(clk)); - else - rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); - - rockchip_clk_register_plls(ctx, rk3366_pll_clks, - ARRAY_SIZE(rk3366_pll_clks), - RK3366_GRF_SOC_STATUS0); - rockchip_clk_register_branches(ctx, rk3366_clk_branches, - ARRAY_SIZE(rk3366_clk_branches)); - rockchip_clk_protect_critical(rk3366_critical_clocks, - ARRAY_SIZE(rk3366_critical_clocks)); - - rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), - &rk3366_cpuclk_data, rk3366_cpuclk_rates, - ARRAY_SIZE(rk3366_cpuclk_rates)); - - rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0), - ROCKCHIP_SOFTRST_HIWORD_MASK); - - rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL); - - rockchip_clk_of_add_provider(np, ctx); -} -CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3366-cru", rk3366_clk_init); diff --git a/drivers/soc/rockchip/Kconfig.cpu b/drivers/soc/rockchip/Kconfig.cpu index 035c354037f2..b7e871ce8501 100644 --- a/drivers/soc/rockchip/Kconfig.cpu +++ b/drivers/soc/rockchip/Kconfig.cpu @@ -43,9 +43,6 @@ config CPU_RK3308 config CPU_RK3328 bool "RK3328" -config CPU_RK3366 - bool "RK3366" - config CPU_RK3368 bool "RK3368" diff --git a/drivers/soc/rockchip/rockchip_pvtm.c b/drivers/soc/rockchip/rockchip_pvtm.c index 457d5254accc..84da125482ba 100644 --- a/drivers/soc/rockchip/rockchip_pvtm.c +++ b/drivers/soc/rockchip/rockchip_pvtm.c @@ -40,10 +40,6 @@ #define RK3288_PVTM_CORE 0 #define RK3288_PVTM_GPU 1 -#define RK3366_PVTM_CORE 0 -#define RK3366_PVTM_GPU 1 -#define RK3366_PVTM_PMU 2 - #define RK3399_PVTM_CORE_L 0 #define RK3399_PVTM_CORE_B 1 #define RK3399_PVTM_DDR 2 @@ -439,31 +435,6 @@ static const struct rockchip_pvtm_info rk3308_pmupvtm = { .get_value = rockchip_pvtm_get_value, }; -static const struct rockchip_pvtm_channel rk3366_pvtm_channels[] = { - PVTM(RK3366_PVTM_CORE, "core", 1, 0, 1, 0x4, 0, 0x4), - PVTM(RK3366_PVTM_GPU, "gpu", 1, 8, 9, 0x8, 1, 0x8), -}; - -static const struct rockchip_pvtm_info rk3366_pvtm = { - .con = 0x800, - .sta = 0x80c, - .num_channels = ARRAY_SIZE(rk3366_pvtm_channels), - .channels = rk3366_pvtm_channels, - .get_value = rockchip_pvtm_get_value, -}; - -static const struct rockchip_pvtm_channel rk3366_pmupvtm_channels[] = { - PVTM(RK3366_PVTM_PMU, "pmu", 1, 0, 1, 0x4, 0, 0x4), -}; - -static const struct rockchip_pvtm_info rk3366_pmupvtm = { - .con = 0x180, - .sta = 0x190, - .num_channels = ARRAY_SIZE(rk3366_pmupvtm_channels), - .channels = rk3366_pmupvtm_channels, - .get_value = rockchip_pvtm_get_value, -}; - static const struct rockchip_pvtm_channel rk3399_pvtm_channels[] = { PVTM(RK3399_PVTM_CORE_L, "core_l", 4, 0, 1, 0x4, 0, 0x4), PVTM(RK3399_PVTM_CORE_B, "core_b", 6, 4, 5, 0x8, 1, 0x8), @@ -525,14 +496,6 @@ static const struct of_device_id rockchip_pvtm_match[] = { .compatible = "rockchip,rk3308-pmu-pvtm", .data = (void *)&rk3308_pmupvtm, }, - { - .compatible = "rockchip,rk3366-pvtm", - .data = (void *)&rk3366_pvtm, - }, - { - .compatible = "rockchip,rk3366-pmu-pvtm", - .data = (void *)&rk3366_pmupvtm, - }, { .compatible = "rockchip,rk3399-pvtm", .data = (void *)&rk3399_pvtm, diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h deleted file mode 100644 index 31ae3993b123..000000000000 --- a/include/dt-bindings/clock/rk3366-cru.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Xiao Feng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3366_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define PLL_MPLL 6 -#define PLL_WPLL 7 -#define PLL_BPLL 8 -#define ARMCLK 9 - -/* sclk gates (special clocks) */ -#define SCLK_CRYPTO 64 -#define SCLK_I2S_8CH_OUT 65 -#define SCLK_I2S_8CH 66 -#define SCLK_I2S_2CH 67 -#define SCLK_SPDIF_8CH 68 -#define SCLK_RGA 69 -#define SCLK_VOP_FULL_PWM 70 -#define SCLK_ISP 71 -#define SCLK_HDMI_HDCP 72 -#define SCLK_HDMI_CEC 73 -#define SCLK_HDCP 75 -#define SCLK_PVTM_CORE 76 -#define SCLK_PVTM_GPU 77 -#define SCLK_SPI0 78 -#define SCLK_SPI1 79 -#define SCLK_SPI2 80 -#define SCLK_SDMMC 81 -#define SCLK_SDIO0 82 -#define SCLK_SDIO1 83 -#define SCLK_EMMC 84 -#define SCLK_SDMMC_DRV 85 -#define SCLK_SDMMC_SAMPLE 86 -#define SCLK_SDIO0_DRV 87 -#define SCLK_SDIO0_SAMPLE 88 -#define SCLK_SDIO1_DRV 89 -#define SCLK_SDIO1_SAMPLE 90 -#define SCLK_EMMC_DRV 91 -#define SCLK_EMMC_SAMPLE 92 -#define SCLK_OTG_PHY0 93 -#define SCLK_OTG_PHY1 94 -#define SCLK_OTG_ADP 95 -#define SCLK_USB3_REF 96 -#define SCLK_USB3_SUSPEND 97 -#define SCLK_TSADC 98 -#define SCLK_SARADC 99 -#define SCLK_NANDC0 100 -#define SCLK_SFC 101 -#define SCLK_UART0 102 -#define SCLK_UART1 103 -#define SCLK_UART2 104 -#define SCLK_UART3 105 -#define SCLK_UART4 106 -#define SCLK_MAC 107 -#define SCLK_MACREF_OUT 108 -#define SCLK_MACREF 109 -#define SCLK_MAC_RX 110 -#define SCLK_MAC_TX 111 -#define SCLK_BT_52 112 -#define SCLK_BT_M0 113 -#define SCLK_WIFIDSP 114 -#define SCLK_TIMER0 115 -#define SCLK_TIMER1 116 -#define SCLK_TIMER2 117 -#define SCLK_TIMER3 118 -#define SCLK_TIMER4 119 -#define SCLK_TIMER5 120 -#define SCLK_USBPHY480M 121 -#define SCLK_WIFI_WPLL 122 -#define SCLK_WIFI_USBPHY480M 123 -#define SCLK_MIPIDSI_24M 124 -#define SCLK_HEVC_CABAC 125 -#define SCLK_HEVC_CORE 126 -#define SCLK_VIP_SRC 127 -#define SCLK_VIP_OUT 128 -#define SCLK_PVTM_PMU 129 -#define SCLK_MPLL_SRC 130 -#define SCLK_32K_INTR 131 -#define SCLK_32K 132 -#define SCLK_I2S_8CH_SRC 133 -#define SCLK_I2S_2CH_SRC 134 -#define SCLK_SPDIF_8CH_SRC 135 - -#define DCLK_VOP_FULL 170 -#define DCLK_VOP_LITE 171 -#define DCLK_HDMIPHY 172 -#define MCLK_CRYPTO 173 - -/* aclk gates */ -#define ACLK_DMAC_BUS 194 -#define ACLK_DFC 195 -#define ACLK_GPU 196 -#define ACLK_GPU_NOC 197 -#define ACLK_USB3 198 -#define ACLK_GMAC 199 -#define ACLK_DMAC_PERI 200 -#define ACLK_VIDEO 201 -#define ACLK_RKVDEC 202 -#define ACLK_RGA 203 -#define ACLK_IEP 204 -#define ACLK_VOP_LITE 205 -#define ACLK_VOP_FULL 206 -#define ACLK_VOP_IEP 207 -#define ACLK_ISP 208 -#define ACLK_HDCP 209 -#define ACLK_BUS 210 -#define ACLK_PERI0 211 -#define ACLK_PERI1 212 - -/* pclk gates */ -#define PCLK_PMU 322 -#define PCLK_SGRF 323 -#define PCLK_PMUGRF 324 -#define PCLK_GPIO0 325 -#define PCLK_GPIO1 326 -#define PCLK_GPIO2 327 -#define PCLK_GPIO3 328 -#define PCLK_GPIO4 329 -#define PCLK_GPIO5 330 -#define PCLK_GRF 331 -#define PCLK_DPHYRX 332 -#define PCLK_DPHYTX 333 -#define PCLK_TIMER0 334 -#define PCLK_DMFIMON 335 -#define PCLK_MAILBOX 336 -#define PCLK_DFC 337 -#define PCLK_DDRUPCTL 338 -#define PCLK_DDRPHY 339 -#define PCLK_RKPWM 340 -#define PCLK_GMAC 341 -#define PCLK_SPI0 342 -#define PCLK_SPI1 343 -#define PCLK_I2C0 344 -#define PCLK_I2C1 345 -#define PCLK_I2C2 346 -#define PCLK_I2C3 347 -#define PCLK_I2C4 348 -#define PCLK_I2C5 349 -#define PCLK_UART0 350 -#define PCLK_UART2 351 -#define PCLK_UART3 352 -#define PCLK_SARADC 353 -#define PCLK_TSADC 354 -#define PCLK_SIM 355 -#define PCLK_HDCP 356 -#define PCLK_HDMI_CTRL 357 -#define PCLK_VIO_H2P 358 -#define PCLK_WDT 359 -#define PCLK_BUS 361 -#define PCLK_PERI0 362 -#define PCLK_PERI1 363 -#define PCLK_MIPI_DSI0 364 -#define PCLK_ISP 365 -#define PCLK_EFUSE_1024 366 -#define PCLK_EFUSE_256 367 - -/* hclk gates */ -#define HCLK_I2S_8CH 448 -#define HCLK_I2S_2CH 449 -#define HCLK_SPDIF 450 -#define HCLK_ROM 451 -#define HCLK_CRYPTO 452 -#define HCLK_OTG 453 -#define HCLK_HOST 454 -#define HCLK_SDMMC 455 -#define HCLK_SDIO 456 -#define HCLK_EMMC 457 -#define HCLK_NANDC0 458 -#define HCLK_SFC 459 -#define HCLK_VIDEO 460 -#define HCLK_RKVDEC 461 -#define HCLK_ISP 462 -#define HCLK_RGA 463 -#define HCLK_IEP 464 -#define HCLK_VOP_FULL 465 -#define HCLK_VOP_LITE 466 -#define HCLK_VIO_AHB_ARBITER 467 -#define HCLK_VIO_NOC 468 -#define HCLK_VIO_H2P 469 -#define HCLK_VIO_HDCPMMU 470 -#define HCLK_BUS 471 -#define HCLK_PERI0 472 -#define HCLK_PERI1 473 - -#define CLK_NR_CLKS (HCLK_PERI1 + 1) - -/* soft-reset indices */ - -/* cru_softrst0_con */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_SOCDBG 14 -#define SRST_CORE_DBG 15 - -/* cru_softrst1_con */ -#define SRST_DCF_AXI 16 -#define SRST_DCF_APB 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_I2S8CH 23 -#define SRST_MAILBOX 24 -#define SRST_I2S2CH 25 -#define SRST_EFUSE_256 26 -#define SRST_MCU_SYS 28 -#define SRST_MCU_PO 29 -#define SRST_MCU_NOC 30 -#define SRST_EFUSE 31 - -/* cru_softrst2_con */ -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_PMUGRF 41 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -/* cru_softrst3_con */ -#define SRST_DWPWM 48 -#define SRST_PERIPH1_AXI 50 -#define SRST_PERIPH1_AHB 51 -#define SRST_PERIPH1_APB 52 -#define SRST_PERIPH1_NIU 53 -#define SRST_PERI_AHB_ARBI1 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH0_AXI 57 -#define SRST_PERIPH0_AHB 58 -#define SRST_PERIPH0_APB 59 -#define SRST_PERIPH0_NIU 60 -#define SRST_PDPERI_AHB_ARBI0 61 -#define SRST_USBHOST0_ARBI 62 - -/* cru_softrst4_con */ -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_USB3 67 -#define SRST_USB3PHY 68 -#define SRST_RKPWM 69 -#define SRST_USBHOST0 72 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_SFC 79 - -/* cru_softrst5_con */ -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 -#define SRST_VOP1_AXI 93 -#define SRST_VOP1_AHB 94 -#define SRST_VOP1_DCLK 95 - -/* cru_softrst6_con */ -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_VOP0_AXI 100 -#define SRST_VOP0_AHB 101 -#define SRST_VOP0_DCLK 102 -#define SRST_HDCP_NIU 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 - -/* cru_softrst7_con */ -#define SRST_VIDEO_AXI 112 -#define SRST_VIDEO_AHB 113 -#define SRST_MIPIDPHYTX 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDPHYRX 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_RGA_H2P 122 -#define SRST_PMU_PVTM 123 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 -#define SRST_GPU_NOC 126 - -/* cru_softrst8_con */ -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHPHY1 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBOTG_UTMI 138 -#define SRST_USBHOST0_UTMI 139 -#define SRST_USB_ADP 141 -#define SRST_TSADC 142 - -/* cru_softrst9_con */ -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_RKVDEC_NIU_AHB 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_RKVDEC 150 -#define SRST_RKVDEC_NIU 151 -#define SRST_RKVDEC_AHB 152 -#define SRST_RKVDEC_CABAC 154 -#define SRST_RKVDEC_CORE 155 -#define SRST_GPU_CFG_NIU 157 -#define SRST_DFIMON 158 -#define SRST_TSADC_APB 159 - -/* cru_softrst10_con */ -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTL 164 -#define SRST_VIDEO_NIU 165 -#define SRST_VIDEO_NIU_AHB 167 -#define SRST_DDRMSCH0 170 -#define SRST_PDBUS_AHB 173 -#define SRST_CRYPTO 174 -#define SRST_DDR_NOC 175 - -/* cru_softrst11_con */ -#define SRST_PSPVTM_TOP 176 -#define SRST_PSPVTM_CORE 177 -#define SRST_PSPVTM_GPU 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_PSPVTM_VIDEO 184 -#define SRST_PSPVTM_VIO 185 -#define SRST_SIMC 186 -#define SRST_PSPVTM_PERI 187 - -/* cru_softrst12_con */ -#define SRST_WIFI_MAC_CORE 192 -#define SRST_WIFI_MAC_WT 193 -#define SRST_WIFI_MPIF 194 -#define SRST_WIFI_EXT 195 -#define SRST_WIFI_AHB 196 -#define SRST_WIFI_DSP 197 -#define SRST_BT_FAST_AHB 198 -#define SRST_BT_SLOW_AHB 199 -#define SRST_BT_SLOW_APB 200 -#define SRST_BT_MODEM 201 -#define SRST_BT_MCU 202 -#define SRST_BT_DM 203 -#define SRST_WIFI_LP 204 -#define SRST_BT_LP 205 -#define SRST_BT_MCU_SYS 206 -#define SRST_WIFI_DSP_ORSTN 207 - -/* cru_softrst13_con */ -#define SRST_CORE0_WFI 208 -#define SRST_CORE0_PO_WFI 209 -#define SRST_CORE_L2 210 -#define SRST_PD_CORE_NIU 212 -#define SRST_PDBUS_STRSYS 213 -#define SRST_TRACE 222 - -/* cru_softrst14_con */ -#define SRST_TIMER00 224 -#define SRST_TIMER01 225 -#define SRST_TIMER02 226 -#define SRST_TIMER03 227 -#define SRST_TIMER04 228 -#define SRST_TIMER05 229 -#define SRST_TIMER10 230 -#define SRST_TIMER11 231 -#define SRST_TIMER12 232 -#define SRST_TIMER13 233 -#define SRST_TIMER14 234 -#define SRST_TIMER15 235 -#define SRST_TIMER0_APB 236 -#define SRST_TIMER1_APB 237 - -#endif