diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp-i2s-audio.c
index 4c6ca1756583..8aa581555e42 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp-i2s-audio.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp-i2s-audio.c
@@ -42,6 +42,13 @@ static inline void hdmi_mod(struct dw_hdmi_qp_i2s_audio_data *audio,
 	return audio->mod(hdmi, data, mask, reg);
 }
 
+static inline bool is_dw_hdmi_qp_clk_off(struct dw_hdmi_qp_i2s_audio_data *audio)
+{
+	u32 sta = hdmi_read(audio, CMU_STATUS);
+
+	return (sta & (AUDCLK_OFF | LINKQPCLK_OFF | VIDQPCLK_OFF));
+}
+
 static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
 				    struct hdmi_codec_daifmt *fmt,
 				    struct hdmi_codec_params *hparms)
@@ -50,6 +57,9 @@ static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
 	struct dw_hdmi_qp *hdmi = audio->hdmi;
 	u32 conf0 = 0;
 
+	if (is_dw_hdmi_qp_clk_off(audio))
+		return 0;
+
 	if (fmt->bit_clk_master | fmt->frame_clk_master) {
 		dev_err(dev, "unsupported clock settings\n");
 		return -EINVAL;
@@ -131,6 +141,9 @@ static int dw_hdmi_qp_i2s_audio_startup(struct device *dev, void *data)
 	struct dw_hdmi_qp_i2s_audio_data *audio = data;
 	struct dw_hdmi_qp *hdmi = audio->hdmi;
 
+	if (is_dw_hdmi_qp_clk_off(audio))
+		return 0;
+
 	dw_hdmi_qp_audio_enable(hdmi);
 
 	return 0;
@@ -141,6 +154,9 @@ static void dw_hdmi_qp_i2s_audio_shutdown(struct device *dev, void *data)
 	struct dw_hdmi_qp_i2s_audio_data *audio = data;
 	struct dw_hdmi_qp *hdmi = audio->hdmi;
 
+	if (is_dw_hdmi_qp_clk_off(audio))
+		return;
+
 	dw_hdmi_qp_audio_disable(hdmi);
 }
 
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
index 8a343df716bc..a891c8333e9b 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
@@ -37,6 +37,11 @@
 #define CMU_CONFIG2					0xa8
 #define CMU_CONFIG3					0xac
 #define CMU_STATUS					0xb0
+#define EARC_BPCLK_OFF					BIT(9)
+#define AUDCLK_OFF					BIT(7)
+#define LINKQPCLK_OFF					BIT(5)
+#define VIDQPCLK_OFF					BIT(3)
+#define IPI_CLK_OFF					BIT(1)
 #define CMU_IPI_CLK_FREQ				0xb4
 #define CMU_VIDQPCLK_FREQ				0xb8
 #define CMU_LINKQPCLK_FREQ				0xbc