From aebca4f07f4e01ef35370b5dd03f2098ce70591a Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Sat, 30 Mar 2024 16:40:17 +0800 Subject: [PATCH] drm/rockchip: vop2: filter unsupported mode when can't get correct dclk For rk3576 and rk3588, vop dclk can be from pll or hdmi phy[except hdmi 2.1(dclk bigger than 597M), the HDMI work at FRL mode], when dclk is from pll, dclk_parent is equal to dclk, we need clk_round_rate() for dclk_parent to check whether can support this mode. 1. GPLL/CPLL/VPLL dclk_parent dclk 2. xin24m clk_hdmiphy_pixel0 dclk Signed-off-by: Sandy Huang Change-Id: I4541d41c3fda5b8ff989e19e8dbf686b15e81216 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 593a34b2ad6a..2d72cd21eeea 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -7244,7 +7244,8 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) else if (vop2->version == VOP_VERSION_RK3588) request_clock = request_clock >> 2; } - clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk, + clock = rockchip_drm_dclk_round_rate(vop2->version, + vp->dclk_parent ? vp->dclk_parent : vp->dclk, request_clock * 1000) / 1000; }