diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index a28e933331dd..222467a9dd89 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -901,7 +901,8 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
 	 * remain powered.
 	 */
 	if (rport->port_id == USB2PHY_PORT_OTG &&
-	    of_device_is_compatible(rphy->dev->of_node, "rockchip,rk3588-usb2phy")) {
+	    (of_device_is_compatible(rphy->dev->of_node, "rockchip,rk3588-usb2phy") ||
+	     of_device_is_compatible(rphy->dev->of_node, "rockchip,rk3576-usb2phy"))) {
 		ret = rockchip_usb2phy_reset(rphy);
 		if (ret) {
 			clk_disable_unprepare(rphy->clk480m);
@@ -2875,6 +2876,68 @@ static int rockchip_usb2phy_vbus_det_control(struct rockchip_usb2phy *rphy,
 	return 0;
 }
 
+static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+	unsigned int reg;
+	int ret = 0;
+
+	if (rphy->phy_cfg->reg == 0x0) {
+		/* Read the SIDDQ control register */
+		ret = regmap_read(rphy->grf, 0x0010, &reg);
+		if (ret)
+			return ret;
+
+		if (reg & BIT(13)) {
+			/* Deassert SIDDQ to power on analog block */
+			ret = regmap_write(rphy->grf, 0x0010,
+					   GENMASK(29, 29) | 0x0000);
+			if (ret)
+				return ret;
+
+			/* Do reset after exit IDDQ mode */
+			ret = rockchip_usb2phy_reset(rphy);
+			if (ret)
+				return ret;
+		}
+
+		/* OTG0 HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
+		ret |= regmap_write(rphy->grf, 0x000c,
+				    GENMASK(27, 24) | 0x0900);
+
+		/* OTG0 HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
+		ret |= regmap_write(rphy->grf, 0x0010,
+				    GENMASK(20, 19) | 0x0010);
+	} else if (rphy->phy_cfg->reg == 0x2000) {
+		/* Read the SIDDQ control register */
+		ret = regmap_read(rphy->grf, 0x2010, &reg);
+		if (ret)
+			return ret;
+
+		if (reg & BIT(13)) {
+			/* Deassert SIDDQ to power on analog block */
+			ret = regmap_write(rphy->grf, 0x2010,
+					   GENMASK(29, 29) | 0x0000);
+			if (ret)
+				return ret;
+
+			/* Do reset after exit IDDQ mode */
+			ret = rockchip_usb2phy_reset(rphy);
+			if (ret)
+				return ret;
+		}
+
+		/* OTG1 HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
+		ret |= regmap_write(rphy->grf, 0x200c,
+				    GENMASK(27, 24) | 0x0900);
+
+		/* OTG1 HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
+		ret |= regmap_write(rphy->grf, 0x2010,
+				    GENMASK(20, 19) | 0x0010);
+	}
+
+	return ret;
+}
+
 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
 {
 	unsigned int reg;
@@ -3840,6 +3903,118 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
+	{
+		.reg = 0x0,
+		.num_ports	= 1,
+		.phy_tuning	= rk3576_usb2phy_tuning,
+		.clkout_ctl	= { 0x0008, 0, 0, 1, 0 },
+		.ls_filter_con	= { 0x0020, 19, 0, 0x30100, 0x00020 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
+				.pipe_phystatus	= { 0x0030, 3, 2, 0, 2 },
+				.bvalid_det_en	= { 0x00c0, 1, 1, 0, 1 },
+				.bvalid_det_st	= { 0x00c4, 1, 1, 0, 1 },
+				.bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
+				.bvalid_grf_sel	= { 0x0000, 14, 14, 0, 1 },
+				.bvalid_grf_con	= { 0x0000, 15, 14, 1, 3 },
+				.bvalid_phy_con	= { 0x0010, 1, 0, 2, 3 },
+				.bypass_dm_en	= { 0x0014, 5, 5, 0, 1 },
+				.bypass_sel	= { 0x0014, 6, 6, 0, 1 },
+				.iddig_output	= { 0x0000, 10, 10, 0, 1 },
+				.iddig_en	= { 0x0000, 9, 9, 0, 1 },
+				.idfall_det_en	= { 0x00c0, 4, 4, 0, 1 },
+				.idfall_det_st	= { 0x00c4, 4, 4, 0, 1 },
+				.idfall_det_clr = { 0x00c8, 4, 4, 0, 1 },
+				.idrise_det_en	= { 0x00c0, 3, 3, 0, 1 },
+				.idrise_det_st	= { 0x00c4, 3, 3, 0, 1 },
+				.idrise_det_clr = { 0x00c8, 3, 3, 0, 1 },
+				.ls_det_en	= { 0x00c0, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x00c4, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x00c8, 0, 0, 0, 1 },
+				.disfall_en	= { 0x00c0, 6, 6, 0, 1 },
+				.disfall_st	= { 0x00c4, 6, 6, 0, 1 },
+				.disfall_clr	= { 0x00c8, 6, 6, 0, 1 },
+				.disrise_en	= { 0x00c0, 5, 5, 0, 1 },
+				.disrise_st	= { 0x00c4, 5, 5, 0, 1 },
+				.disrise_clr	= { 0x00c8, 5, 5, 0, 1 },
+				.utmi_avalid	= { 0x0080, 1, 1, 0, 1 },
+				.utmi_bvalid	= { 0x0080, 0, 0, 0, 1 },
+				.utmi_iddig	= { 0x0080, 6, 6, 0, 1 },
+				.utmi_ls	= { 0x0080, 5, 4, 0, 1 },
+			}
+		},
+		.chg_det = {
+			.chg_mode	= { 0x0000, 8, 0, 0, 0x1d7 },
+			.cp_det		= { 0x0080, 8, 8, 0, 1 },
+			.dcp_det	= { 0x0080, 8, 8, 0, 1 },
+			.dp_det		= { 0x0080, 9, 9, 1, 0 },
+			.idm_sink_en	= { 0x0010, 5, 5, 1, 0 },
+			.idp_sink_en	= { 0x0010, 5, 5, 0, 1 },
+			.idp_src_en	= { 0x0010, 14, 14, 0, 1 },
+			.rdm_pdwn_en	= { 0x0010, 14, 14, 0, 1 },
+			.vdm_src_en	= { 0x0010, 7, 6, 0, 3 },
+			.vdp_src_en	= { 0x0010, 7, 6, 0, 3 },
+		},
+	},
+	{
+		.reg = 0x2000,
+		.num_ports	= 1,
+		.phy_tuning	= rk3576_usb2phy_tuning,
+		.clkout_ctl	= { 0x2008, 0, 0, 1, 0 },
+		.ls_filter_con	= { 0x2020, 19, 0, 0x30100, 0x00020 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x2000, 8, 0, 0, 0x1d1 },
+				.pipe_phystatus	= { 0x0038, 3, 2, 0, 2 },
+				.bvalid_det_en	= { 0x20c0, 1, 1, 0, 1 },
+				.bvalid_det_st	= { 0x20c4, 1, 1, 0, 1 },
+				.bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
+				.bvalid_grf_sel	= { 0x2000, 14, 14, 0, 1 },
+				.bvalid_grf_con	= { 0x2000, 15, 14, 1, 3 },
+				.bvalid_phy_con	= { 0x2010, 1, 0, 2, 3 },
+				.bypass_dm_en	= { 0x2014, 5, 5, 0, 1 },
+				.bypass_sel	= { 0x2014, 6, 6, 0, 1 },
+				.iddig_output	= { 0x2000, 10, 10, 0, 1 },
+				.iddig_en	= { 0x2000, 9, 9, 0, 1 },
+				.idfall_det_en	= { 0x20c0, 4, 4, 0, 1 },
+				.idfall_det_st	= { 0x20c4, 4, 4, 0, 1 },
+				.idfall_det_clr = { 0x20c8, 4, 4, 0, 1 },
+				.idrise_det_en	= { 0x20c0, 3, 3, 0, 1 },
+				.idrise_det_st	= { 0x20c4, 3, 3, 0, 1 },
+				.idrise_det_clr = { 0x20c8, 3, 3, 0, 1 },
+				.ls_det_en	= { 0x20c0, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x20c4, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x20c8, 0, 0, 0, 1 },
+				.disfall_en	= { 0x20c0, 6, 6, 0, 1 },
+				.disfall_st	= { 0x20c4, 6, 6, 0, 1 },
+				.disfall_clr	= { 0x20c8, 6, 6, 0, 1 },
+				.disrise_en	= { 0x20c0, 5, 5, 0, 1 },
+				.disrise_st	= { 0x20c4, 5, 5, 0, 1 },
+				.disrise_clr	= { 0x20c8, 5, 5, 0, 1 },
+				.utmi_avalid	= { 0x2080, 1, 1, 0, 1 },
+				.utmi_bvalid	= { 0x2080, 0, 0, 0, 1 },
+				.utmi_iddig	= { 0x2080, 6, 6, 0, 1 },
+				.utmi_ls	= { 0x2080, 5, 4, 0, 1 },
+			}
+		},
+		.chg_det = {
+			.chg_mode	= { 0x2000, 8, 0, 0, 0x1d7 },
+			.cp_det		= { 0x2080, 8, 8, 0, 1 },
+			.dcp_det	= { 0x2080, 8, 8, 0, 1 },
+			.dp_det		= { 0x2080, 9, 9, 1, 0 },
+			.idm_sink_en	= { 0x2010, 5, 5, 1, 0 },
+			.idp_sink_en	= { 0x2010, 5, 5, 0, 1 },
+			.idp_src_en	= { 0x2010, 14, 14, 0, 1 },
+			.rdm_pdwn_en	= { 0x2010, 14, 14, 0, 1 },
+			.vdm_src_en	= { 0x2010, 7, 6, 0, 3 },
+			.vdp_src_en	= { 0x2010, 7, 6, 0, 3 },
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
 	{
 		.reg = 0x0000,
@@ -4121,6 +4296,9 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
 #ifdef CONFIG_CPU_RK3568
 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
 #endif
+#ifdef CONFIG_CPU_RK3576
+	{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
+#endif
 #ifdef CONFIG_CPU_RK3588
 	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
 #endif