From 9d31e80fc16f6982e9fad4c8f600d7edda935256 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Mon, 15 Jul 2024 10:25:21 +0800 Subject: [PATCH 001/191] arm64: dts: rockchip: rk3576-vehicle-evb: fix io conflict for SAI1 The SDI1/2/3 and SDO1/2/3 for SAI1 on RK3576 is iomux functions. Change-Id: I2292e4c3b5c75044e343d19c3557724591365836 Signed-off-by: Jianqun Xu --- arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi index 5175f329bbc1..e75c10fdad11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi @@ -388,12 +388,9 @@ &sai1m0_sclk &sai1m0_sdi0 &sai1m0_sdi1 - &sai1m0_sdi2 - &sai1m0_sdi3 &sai1m0_sdo0 &sai1m0_sdo1 - &sai1m0_sdo2 - &sai1m0_sdo3>; + &sai1m0_sdo2>; }; &sdmmc { From 05422d88379fb97652311b2df5f223024c932681 Mon Sep 17 00:00:00 2001 From: Weixin Zhou Date: Sat, 13 Jul 2024 10:24:15 +0800 Subject: [PATCH 002/191] input: sensors: hall: mh248: clean hall wakeup flag when the kernel suspend abort with is_hall_wakeup true, mh248 resume will use wrong state of is_hall_wakeup to send powerkey event to wakeup screen. Signed-off-by: Weixin Zhou Change-Id: Ifc8d83f49329631e9088fee9111b295c77e05a8a --- drivers/input/sensors/hall/mh248.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/sensors/hall/mh248.c b/drivers/input/sensors/hall/mh248.c index bed35c4a8a11..2a4586dec37e 100644 --- a/drivers/input/sensors/hall/mh248.c +++ b/drivers/input/sensors/hall/mh248.c @@ -275,6 +275,7 @@ static int mh248_resume(struct device *dev) if (mem_sleep_current == PM_SUSPEND_MEM_ULTRA) { if (g_mh248->is_hall_wakeup) { + g_mh248->is_hall_wakeup = 0; gpio_value = gpio_get_value(g_mh248->gpio_pin); if ((gpio_value == g_mh248->active_value) && (g_mh248->is_suspend == 1)) { From f5566f8c7d979d47ef0584034653b28c54bd09d9 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 21 Jun 2024 16:19:09 +0800 Subject: [PATCH 003/191] spi: rockchip-sfc: Add rockchip,fspi compatible Change-Id: I0ccccf4061465836837cfde78bf7e70d2da78ac6 Signed-off-by: Jon Lin --- drivers/spi/spi-rockchip-sfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 0dc25bd9a685..48e89763fcb5 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -1125,6 +1125,7 @@ static const struct dev_pm_ops rockchip_sfc_pm_ops = { }; static const struct of_device_id rockchip_sfc_dt_ids[] = { + { .compatible = "rockchip,fspi"}, { .compatible = "rockchip,sfc"}, { /* sentinel */ } }; From c333c5b65be8dc285eaf7c1b77535be530eeb5cc Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 21 Jun 2024 17:31:16 +0800 Subject: [PATCH 004/191] dt-bindings: spi: rockchip-sfc: Add rockchip,fspi compatible Change-Id: I61d4919ed3813579dfc3a6caac7ffdf64aa96098 Signed-off-by: Jon Lin --- Documentation/devicetree/bindings/spi/rockchip-sfc.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml index 7ab581a7a127..0b394d83771f 100644 --- a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml @@ -15,11 +15,15 @@ allOf: properties: compatible: - const: rockchip,sfc + enum: + - rockchip,fspi + - rockchip,sfc + description: The rockchip sfc controller is a standalone IP with version register, and the driver can handle all the feature difference inside the IP depending on the version register. + The rockchip flexible spi controller is the next generation IP of sfc. reg: maxItems: 1 From 3576d58da0ea63b141581f835f7a3146615678be Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 21 Jun 2024 18:39:38 +0800 Subject: [PATCH 005/191] spi: rockchip-sfc: Support sclk_x2_bypass Change-Id: Ic5e19484afc9f98063e73d0da2bbf9f3cb595ea8 Signed-off-by: Jon Lin --- drivers/spi/spi-rockchip-sfc.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 48e89763fcb5..67b4e486dacf 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -123,6 +123,10 @@ #define SFC_VER_6 0x6 #define SFC_VER_8 0x8 +/* Ext ctrl */ +#define SFC_EXT_CTRL 0x34 +#define SFC_SCLK_X2_BYPASS BIT(24) + /* Delay line controller resiter */ #define SFC_DLL_CTRL0 0x3C #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) @@ -205,6 +209,7 @@ struct rockchip_sfc { dma_addr_t dma_buffer; struct completion cp; bool use_dma; + bool sclk_x2_bypass; u32 max_iosize; u32 dll_cells[SFC_MAX_CHIPSELECT_NUM]; u16 version; @@ -273,18 +278,18 @@ static void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells, u8 static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long speed) { - if (sfc->version >= SFC_VER_8) - return clk_set_rate(sfc->clk, speed * 2); - else + if (sfc->version < SFC_VER_8 || sfc->sclk_x2_bypass) return clk_set_rate(sfc->clk, speed); + else + return clk_set_rate(sfc->clk, speed * 2); } static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc) { - if (sfc->version >= SFC_VER_8) - return clk_get_rate(sfc->clk) / 2; - else + if (sfc->version < SFC_VER_8 || sfc->sclk_x2_bypass) return clk_get_rate(sfc->clk); + else + return clk_get_rate(sfc->clk) / 2; } static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) @@ -309,11 +314,18 @@ static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) static int rockchip_sfc_init(struct rockchip_sfc *sfc) { + u32 reg; + writel(0, sfc->regbase + SFC_CTRL); writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF); if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); + if (rockchip_sfc_get_version(sfc) >= SFC_VER_8 && sfc->sclk_x2_bypass) { + reg = readl(sfc->regbase + SFC_EXT_CTRL); + reg |= SFC_SCLK_X2_BYPASS; + writel(reg, sfc->regbase + SFC_EXT_CTRL); + } return 0; } @@ -937,6 +949,8 @@ static int rockchip_sfc_probe(struct platform_device *pdev) sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, "rockchip,sfc-no-dma"); + sfc->sclk_x2_bypass = of_property_read_bool(sfc->dev->of_node, + "rockchip,sclk-x2-bypass"); ret = rockchip_sfc_get_gpio_descs(master, sfc); if (ret) { From e815077db871db746508343649cabdec927526d2 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 21 Jun 2024 18:43:02 +0800 Subject: [PATCH 006/191] dt-bindings: spi: rockchip-sfc: Add rockchip,sclk-x2-bypass property Change-Id: Ide075d15a32ad2e29bdfbd9c21c56a6853fdccb8 Signed-off-by: Jon Lin --- Documentation/devicetree/bindings/spi/rockchip-sfc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml index 0b394d83771f..7f13e3d3946f 100644 --- a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml @@ -48,6 +48,12 @@ properties: description: Disable DMA and utilize FIFO mode only type: boolean + rockchip,sclk-x2-bypass: + description: + Turn off the internal 2 frequency division logic of the controller clock, + and the interface clock is 1:1 with the controller working clock. + type: boolean + patternProperties: "^flash@[0-3]$": type: object From 29f9d3fccbcc487470ccb1679c95cf2c36c02548 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sat, 22 Jun 2024 18:23:34 +0800 Subject: [PATCH 007/191] spi: spi-rockchip-sfc: Support SFC_VER_9 Change-Id: I44b99cae8bbe1d23a48a65b5435456a070e76fca Signed-off-by: Jon Lin --- drivers/spi/spi-rockchip-sfc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 67b4e486dacf..1807245f9711 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -122,6 +122,7 @@ #define SFC_VER_5 0x5 #define SFC_VER_6 0x6 #define SFC_VER_8 0x8 +#define SFC_VER_9 0x9 /* Ext ctrl */ #define SFC_EXT_CTRL 0x34 @@ -999,6 +1000,8 @@ static int rockchip_sfc_probe(struct platform_device *pdev) goto err_irq; sfc->version = rockchip_sfc_get_version(sfc); + if (sfc->version == SFC_VER_9) + sfc->version = SFC_VER_6; sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; From 91f060aa31c817882aef21b079e1403c6189705b Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 8 Nov 2023 09:07:01 -0600 Subject: [PATCH 008/191] UPSTREAM: mtd: spinand: gigadevice: Fix the get ecc status issue Some GigaDevice ecc_get_status functions use on-stack buffer for spi_mem_op causes spi_mem_check_op failing, fix the issue by using spinand scratchbuf. Fixes: c40c7a990a46 ("mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG") Change-Id: I061911754ab4a3d69bfa2ebbb17af8f14027e5cc Signed-off-by: Han Xu Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20231108150701.593912-1-han.xu@nxp.com (cherry picked from commit 59950610c0c00c7a06d8a75d2ee5d73dba4274cf) Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/gigadevice.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index e8601e8d7d7a..9bfd08a0b4a8 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -210,7 +210,7 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, { u8 status2; struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, - &status2); + spinand->scratchbuf); int ret; switch (status & STATUS_ECC_MASK) { @@ -231,6 +231,7 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, * report the maximum of 4 in this case */ /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */ + status2 = *(spinand->scratchbuf); return ((status & STATUS_ECC_MASK) >> 2) | ((status2 & STATUS_ECC_MASK) >> 4); @@ -252,7 +253,7 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, { u8 status2; struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, - &status2); + spinand->scratchbuf); int ret; switch (status & STATUS_ECC_MASK) { @@ -272,6 +273,7 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, * 1 ... 4 bits are flipped (and corrected) */ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ + status2 = *(spinand->scratchbuf); return ((status2 & STATUS_ECC_MASK) >> 4) + 1; case STATUS_ECC_UNCOR_ERROR: From abe99ba212b4a01d823e061bf83aaa0eeb2f6493 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 28 Jun 2024 18:58:57 +0800 Subject: [PATCH 009/191] drm/rockchip: rgb: fix the log in rockchip_rgb_encoder_mode_valid() The logs about max clock check may be too frequent, so replace DRM_DEV_ERROR() with DRM_DEBUG_DRIVER(). Change-Id: Ia5e4ad4a7dc00863e99d9b6cb92f3a812c1171e9 Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index f93511282777..d66d415bf746 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -382,7 +382,6 @@ rockchip_rgb_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) { struct rockchip_rgb *rgb = encoder_to_rgb(encoder); - struct device *dev = rgb->dev; struct drm_display_info *info = &rgb->connector.display_info; u32 request_clock = mode->clock; u32 max_clock = rgb->max_dclk_rate; @@ -401,8 +400,8 @@ rockchip_rgb_encoder_mode_valid(struct drm_encoder *encoder, (rgb->mcu_pix_total + 1); if (max_clock != 0 && request_clock > max_clock) { - DRM_DEV_ERROR(dev, "mode [%dx%d] clock %d is higher than max_clock %d\n", - mode->hdisplay, mode->vdisplay, request_clock, max_clock); + DRM_DEBUG_DRIVER("mode [%dx%d] clock %d is higher than max_clock %d\n", + mode->hdisplay, mode->vdisplay, request_clock, max_clock); return MODE_CLOCK_HIGH; } From 09f85f2be6d4a00e5ddc400711e8e47d3d752f68 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 28 Jun 2024 20:54:42 +0800 Subject: [PATCH 010/191] drm/rockchip: rgb: clear output_if of rockchip_crtc_state if crtc active change Clear output_if of rockchip_crtc_state in rockchip_rgb_encoder_disable() only if active_changed flag of drm_crtc_state is true, otherwise the output_if related checks may be affected in .atomic_enable() of crtc. Change-Id: Id15873feebd420a77c8949ea6601b9f33c18188c Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index d66d415bf746..78f7bc1f6d74 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -263,7 +263,9 @@ static void rockchip_rgb_encoder_disable(struct drm_encoder *encoder) rgb->funcs->disable(rgb); pinctrl_pm_select_sleep_state(rgb->dev); - s->output_if &= ~(VOP_OUTPUT_IF_RGB | VOP_OUTPUT_IF_BT656 | VOP_OUTPUT_IF_BT1120); + + if (crtc->state->active_changed) + s->output_if &= ~(VOP_OUTPUT_IF_RGB | VOP_OUTPUT_IF_BT656 | VOP_OUTPUT_IF_BT1120); } static int From d8983a420310f00f60cc136866b0cce74ae9995c Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 3 Jul 2024 19:50:40 +0800 Subject: [PATCH 011/191] soc: rockchip: debug: fix compile error on arm Change-Id: Ie00fddf20e0fff5e5d3bb6e96e9c3b6040d24165 Signed-off-by: Huibin Hong --- drivers/soc/rockchip/rockchip_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/rockchip/rockchip_debug.c b/drivers/soc/rockchip/rockchip_debug.c index 417781d3f8b0..f468183abf43 100644 --- a/drivers/soc/rockchip/rockchip_debug.c +++ b/drivers/soc/rockchip/rockchip_debug.c @@ -551,7 +551,7 @@ static int rockchip_hardlock_notify(struct notifier_block *nb, else pmpcsr &= 0x0fffffffffffffff; /* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */ - pc = (void *)(pmpcsr & ~1); + pc = (void *)(uintptr_t)(pmpcsr & ~1); } rockchip_debug_serror_enable(); From 9e76349ea21b39ead98c1f386d691929cc25506b Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 19 Feb 2024 16:41:23 +0800 Subject: [PATCH 012/191] drm/bridge: sii902x: enable CLK_RATIO_2X for interlace modes According to the datasheet, CLK_RATIO_2X should be enabled for interlace modes otherwise the 720x480i60/720x576i60 modes may be mistaken for 360x480p60/360x576p60. Change-Id: I7efa084b7d3a05bdafd0dc17264784db178d05c6 Signed-off-by: Damon Ding --- drivers/gpu/drm/bridge/sii902x.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c index d3fbbeff7ed9..3cb850db9e99 100644 --- a/drivers/gpu/drm/bridge/sii902x.c +++ b/drivers/gpu/drm/bridge/sii902x.c @@ -40,6 +40,7 @@ #define SII902X_TPI_AVI_PIXEL_REP_4X 3 #define SII902X_TPI_AVI_PIXEL_REP_2X 1 #define SII902X_TPI_AVI_PIXEL_REP_NONE 0 +#define SII902X_TPI_CLK_RATIO_MASK GENMASK(7, 6) #define SII902X_TPI_CLK_RATIO_HALF (0 << 6) #define SII902X_TPI_CLK_RATIO_1X (1 << 6) #define SII902X_TPI_CLK_RATIO_2X (2 << 6) @@ -550,6 +551,7 @@ static void sii902x_bridge_mode_set(struct drm_bridge *bridge, u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; struct hdmi_avi_infoframe frame; u16 pixel_clock_10kHz = adj->clock / 10; + u8 ratio; int ret, vrefresh; if (sii902x->loader_protect) { @@ -570,8 +572,7 @@ static void sii902x_bridge_mode_set(struct drm_bridge *bridge, buf[5] = adj->crtc_htotal >> 8; buf[6] = adj->crtc_vtotal; buf[7] = adj->crtc_vtotal >> 8; - buf[8] = SII902X_TPI_CLK_RATIO_1X | SII902X_TPI_AVI_PIXEL_REP_NONE | - SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT; + buf[8] = SII902X_TPI_AVI_PIXEL_REP_NONE | SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT; switch (sii902x->bus_format) { case MEDIA_BUS_FMT_YUYV8_1X16: case MEDIA_BUS_FMT_YVYU8_1X16: @@ -620,6 +621,13 @@ static void sii902x_bridge_mode_set(struct drm_bridge *bridge, if (ret) goto out; + if (sii902x->mode.flags & DRM_MODE_FLAG_INTERLACE) + ratio = SII902X_TPI_CLK_RATIO_2X; + else + ratio = SII902X_TPI_CLK_RATIO_1X; + regmap_update_bits(sii902x->regmap, SII902X_TPI_PIXEL_REPETITION, + SII902X_TPI_CLK_RATIO_MASK, ratio); + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, &sii902x->connector, adj); if (ret < 0) { From 86d14071cc152da6a6274c3ea60103e4f4f13413 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 25 Jun 2024 15:24:31 +0800 Subject: [PATCH 013/191] pwm: rockchip: read more regs for pwm v4 in rockchip_pwm_debugfs_show() Change-Id: Ied865eee371e08b0b5895482f49d1da777828ac3 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index d89dce9db1d8..bee407572e06 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -1842,7 +1842,7 @@ static int rockchip_pwm_debugfs_show(struct seq_file *s, void *data) if (pc->main_version >= 4) { regs_start = (u32)pc->res->start; - for (i = 0; i < 0x80; i += 4) { + for (i = 0; i < 0x90; i += 4) { seq_printf(s, "%08x: %08x %08x %08x %08x\n", regs_start + i * 4, readl_relaxed(pc->base + (4 * i)), readl_relaxed(pc->base + (4 * (i + 1))), From 7ba66dbbff8902080844f253b4b30554d5e36592 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 25 Jun 2024 15:03:32 +0800 Subject: [PATCH 014/191] pwm: rockchip: make sure the dividend is u64 in frequency calculation Change-Id: I207ceb42ab31d45c9bf2b72a54e94003ee508cf5 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index bee407572e06..26dd79a86a00 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -1224,7 +1224,7 @@ static int rockchip_pwm_get_freq_meter_result_v4(struct pwm_chip *chip, struct p if (pc->freq_res_valid) { freq_res = readl_relaxed(pc->base + FREQ_RESULT_VALUE); freq_timer = readl_relaxed(pc->base + FREQ_TIMER_VALUE); - *freq_hz = DIV_ROUND_CLOSEST_ULL(pc->clk_rate * freq_res, freq_timer); + *freq_hz = DIV_ROUND_CLOSEST_ULL((u64)pc->clk_rate * freq_res, freq_timer); if (!*freq_hz) return -EINVAL; @@ -1765,7 +1765,7 @@ static int rockchip_pwm_get_biphasic_result_v4(struct pwm_chip *chip, struct pwm if (pc->biphasic_config->mode == PWM_BIPHASIC_COUNTER_MODE0_FREQ) { val = *biphasic_res; biphasic_timer = readl_relaxed(pc->base + BIPHASIC_TIMER_VALUE); - *biphasic_res = DIV_ROUND_CLOSEST_ULL(pc->clk_rate * val, + *biphasic_res = DIV_ROUND_CLOSEST_ULL((u64)pc->clk_rate * val, biphasic_timer); } From 1479b8950e3b38e8051a1810f46e6ea5359a59ab Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 1 Jul 2024 16:42:34 +0800 Subject: [PATCH 015/191] pwm: rockchip: not to switch pclk dynamically in count mode According to IC design, it is not recommended to enable/disable pclk in counter mode, because the pclk is used to sync counter result. Change-Id: Ibb44082ae1091d38a51f0d1f0c1879769109bc86 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 26dd79a86a00..5d585dc5ce80 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -1084,9 +1084,11 @@ int rockchip_pwm_set_counter(struct pwm_device *pwm, return -EBUSY; } - ret = clk_enable(pc->pclk); - if (ret) - return ret; + if (enable) { + ret = clk_enable(pc->pclk); + if (ret) + return ret; + } ret = pinctrl_select_state(pc->pinctrl, pc->active_state); if (ret) { @@ -1101,8 +1103,14 @@ int rockchip_pwm_set_counter(struct pwm_device *pwm, goto err_disable_pclk; } + if (!enable) + clk_disable(pc->pclk); + + return ret; + err_disable_pclk: - clk_disable(pc->pclk); + if (enable) + clk_disable(pc->pclk); return ret; } @@ -1146,20 +1154,13 @@ int rockchip_pwm_get_counter_result(struct pwm_device *pwm, return -EINVAL; } - ret = clk_enable(pc->pclk); - if (ret) - return ret; - ret = pc->data->funcs.get_counter_result(chip, pwm, counter_res, is_clear); if (ret) { dev_err(chip->dev, "Failed to get counter result for PWM%d\n", pc->channel_id); - goto err_disable_pclk; + return ret; } -err_disable_pclk: - clk_disable(pc->pclk); - return ret; } EXPORT_SYMBOL_GPL(rockchip_pwm_get_counter_result); From e8d401ee32a6b1a8dcd877879448c9750b93864b Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 1 Jul 2024 15:25:39 +0800 Subject: [PATCH 016/191] pwm: rockchip-test: get counter result before disabled in pwm test demo The counter result read after disabled may be inaccurate, because the arbitration has been removed. Change-Id: Id91069721ef5767d81bb8bced0ae429840711ad4 Signed-off-by: Damon Ding --- drivers/pwm/pwm-rockchip-test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-rockchip-test.c b/drivers/pwm/pwm-rockchip-test.c index ca8dc514664e..59294260298d 100644 --- a/drivers/pwm/pwm-rockchip-test.c +++ b/drivers/pwm/pwm-rockchip-test.c @@ -490,16 +490,16 @@ static ssize_t pwm_rockchip_test_write(struct file *file, const char __user *buf msleep(timeout_ms); - ret = rockchip_pwm_set_counter(pdev, 0, false); + ret = rockchip_pwm_get_counter_result(pdev, &counter_res, true); if (ret) { - pr_err("failed to disable %s mode for pwm%d_%d\n", + pr_err("failed to get %s mode result for pwm%d_%d\n", cmd, controller_id, channel_id); return -EINVAL; } - ret = rockchip_pwm_get_counter_result(pdev, &counter_res, true); + ret = rockchip_pwm_set_counter(pdev, 0, false); if (ret) { - pr_err("failed to get %s mode result for pwm%d_%d\n", + pr_err("failed to disable %s mode for pwm%d_%d\n", cmd, controller_id, channel_id); return -EINVAL; } From e000b868adbb50f342619d05f23b6c1657e4f758 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Fri, 5 Jul 2024 18:06:38 +0800 Subject: [PATCH 017/191] soc: rockchip: fiq debugger: alloc memory for fifo and tty_fifo save about 130944 bytes image size. Change-Id: Ie6683f01d6b0189018961236a4dce44e0c51a277 Signed-off-by: Huibin Hong --- .../soc/rockchip/fiq_debugger/rk_fiq_debugger.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c b/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c index 8902c5153ce0..2e43bdb01209 100644 --- a/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c +++ b/drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c @@ -232,8 +232,8 @@ static void debug_flush(struct platform_device *pdev) #ifdef CONFIG_RK_CONSOLE_THREAD #define FIFO_SIZE SZ_64K #define TTY_FIFO_SIZE SZ_64K -static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE); -static DEFINE_KFIFO(tty_fifo, unsigned char, TTY_FIFO_SIZE); +static struct kfifo fifo; +static struct kfifo tty_fifo; static bool console_thread_stop; /* write on console_write */ static bool console_thread_running; /* write on console_thread */ static unsigned int console_dropped_messages; @@ -1110,7 +1110,17 @@ static int __init rk_fiqdbg_probe(struct platform_device *pdev) pr_err("fiq-debugger get clock fail\n"); return -EINVAL; } +#ifdef CONFIG_RK_CONSOLE_THREAD + if (kfifo_alloc(&fifo, FIFO_SIZE, GFP_KERNEL)) { + pr_err("fiq-debugger alloc fifo fail\n"); + return -ENOMEM; + } + if (kfifo_alloc(&tty_fifo, TTY_FIFO_SIZE, GFP_KERNEL)) { + pr_err("fiq-debugger alloc tty_fifo fail\n"); + return -ENOMEM; + } +#endif clk_prepare_enable(clk); clk_prepare_enable(pclk); From 3b8c21b8822af83dc07154afd938c61d025d5b1c Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 9 Jul 2024 15:28:49 +0800 Subject: [PATCH 018/191] net: can: rockchip: rk3576: fix the rx_fifo_depth Change-Id: I571a8abe5017354f6a6b041f5ae5b9912ce8b4db Signed-off-by: Elaine Zhang --- drivers/net/can/rockchip/rk3576_canfd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/rockchip/rk3576_canfd.c b/drivers/net/can/rockchip/rk3576_canfd.c index eab5b850a7d6..52697b70703f 100644 --- a/drivers/net/can/rockchip/rk3576_canfd.c +++ b/drivers/net/can/rockchip/rk3576_canfd.c @@ -830,7 +830,7 @@ static int rk3576_canfd_rx_poll(struct napi_struct *napi, int quota) while (work_done < rcan->quota) work_done += rk3576_canfd_rx(ndev, work_done); - if (work_done < rcan->rx_fifo_depth) { + if (work_done <= rcan->rx_fifo_depth) { napi_complete_done(napi, work_done); rk3576_canfd_write(rcan, CANFD_INT_MASK, INT_ENABLE); } @@ -846,7 +846,7 @@ static int rk3576_canfd_rx_poll(struct napi_struct *napi, int quota) while (work_done < quota) work_done += rk3576_canfd_rx(ndev, CANFD_RXFRD); - if (work_done < rcan->rx_fifo_depth) { + if (work_done <= rcan->rx_fifo_depth) { napi_complete_done(napi, work_done); rk3576_canfd_write(rcan, CANFD_INT_MASK, INT_ENABLE); } From 24baa731372f42b5881aaa4387c6fee94c7e4999 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 28 Jun 2024 18:52:18 +0800 Subject: [PATCH 019/191] ASoC: rockchip: multicodecs: Depends on INPUT and EXTCON Signed-off-by: Sugar Zhang Change-Id: I30140add50609cf745c09b5859702376d4f27408 --- sound/soc/rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig index 5d4cf45426eb..ed8de4bc8624 100644 --- a/sound/soc/rockchip/Kconfig +++ b/sound/soc/rockchip/Kconfig @@ -139,7 +139,7 @@ config SND_SOC_ROCKCHIP_MAX98090 config SND_SOC_ROCKCHIP_MULTICODECS tristate "ASoC support for Rockchip multicodecs" - depends on SND_SOC_ROCKCHIP && HAVE_CLK + depends on SND_SOC_ROCKCHIP && HAVE_CLK && INPUT && EXTCON help Say Y or M here if you want to add support for SoC audio on Rockchip boards using multicodecs, such as RK3308 boards. From 934e65c34aca21f4dc841ada16a4888799bb91f5 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Sat, 29 Jun 2024 15:19:53 +0800 Subject: [PATCH 020/191] ASoC: es8323: Remove non-existent register 0x35 ES8323 0-0011: ASoC: error at soc_component_write_no_lock on ES8323.0-0011 for register: [0x00000035] -5 Signed-off-by: Sugar Zhang Change-Id: I798eaa00c3c95a85d18d04d55503c9acb40c5396 --- sound/soc/codecs/es8323.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/codecs/es8323.c b/sound/soc/codecs/es8323.c index bf35eaec413c..87adeaac233a 100644 --- a/sound/soc/codecs/es8323.c +++ b/sound/soc/codecs/es8323.c @@ -808,7 +808,6 @@ static int es8323_probe(struct snd_soc_component *component) snd_soc_component_write(component, 0x1B, 0x00); snd_soc_component_write(component, 0x27, 0xB8); snd_soc_component_write(component, 0x2A, 0xB8); - snd_soc_component_write(component, 0x35, 0xA0); usleep_range(18000, 20000); snd_soc_component_write(component, 0x2E, 0x1E); snd_soc_component_write(component, 0x2F, 0x1E); From 94152e98c114da1f9add52197b2a9899c6e4a249 Mon Sep 17 00:00:00 2001 From: David Wu Date: Sat, 29 Jun 2024 15:16:43 +0800 Subject: [PATCH 021/191] net: phy: motorcomm: Add YT8522 phy support Change-Id: I29abc85c505df5d644b1a0ec0db64101e5f1631d Signed-off-by: David Wu --- drivers/net/phy/motorcomm.c | 139 +++++++++++++++++++++++++++++++++++- 1 file changed, 138 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index a618df511257..983c6b52d103 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -15,6 +15,7 @@ #define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8512 0x00000118 #define PHY_ID_YT8512B 0x00000128 +#define PHY_ID_YT8522 0x4f51e928 #define PHY_ID_YT8531S 0x4f51e91a #define PHY_ID_YT8531 0x4f51e91b @@ -43,7 +44,7 @@ struct yt8011_priv { #define REG_DEBUG_ADDR_OFFSET 0x1e #define REG_DEBUG_DATA 0x1f #define REG_MII_MMD_CTRL 0x0D /* MMD access control register */ -#define REG_MII_MMD_DATA 0x0E /* MMD access data register */ +#define REG_MII_MMD_DATA 0x0E /* MMD access data register */ #define YT8511_PAGE_SELECT 0x1e #define YT8511_PAGE 0x1f @@ -99,6 +100,22 @@ struct yt8011_priv { #define YT8512_DUPLEX_BIT 13 #define YT8512_EN_SLEEP_SW_BIT 15 +#define YT8522_TX_CLK_DELAY 0x4210 +#define YT8522_ANAGLOG_IF_CTRL 0x4008 +#define YT8522_DAC_CTRL 0x2057 +#define YT8522_INTERPOLATOR_FILTER_1 0x14 +#define YT8522_INTERPOLATOR_FILTER_2 0x15 +#define YT8522_EXTENDED_COMBO_CTRL_1 0x4000 + +#define YTXXXX_SPEED_MODE 0xc000 +#define YTXXXX_DUPLEX 0x2000 +#define YTXXXX_SPEED_MODE_BIT 14 +#define YTXXXX_DUPLEX_BIT 13 +#define YTXXXX_AUTO_NEGOTIATION_BIT 12 +#define YTXXXX_ASYMMETRIC_PAUSE_BIT 11 +#define YTXXXX_PAUSE_BIT 10 +#define YTXXXX_LINK_STATUS_BIT 10 + /* if system depends on ethernet packet to restore from sleep, * please define this macro to 1 otherwise, define it to 0. */ @@ -114,6 +131,11 @@ struct yt8011_priv { #define SYS_WAKEUP_BASED_ON_ETH_PKT 1 #endif +struct yt8xxx_priv { + u8 polling_mode; + u8 chip_mode; +}; + /* for YT8531 package A xtal init config */ #define YTPHY8531A_XTAL_INIT 0 @@ -913,6 +935,109 @@ static int yt8521_resume(struct phy_device *phydev) return 0; } +static int yt8522_read_status(struct phy_device *phydev) +{ + int speed, speed_mode, duplex, val; + + genphy_read_status(phydev); + val = phy_read(phydev, REG_PHY_SPEC_STATUS); + if (val < 0) + return val; + + /* link up */ + if ((val & BIT(10)) >> YTXXXX_LINK_STATUS_BIT) { + duplex = (val & BIT(13)) >> YTXXXX_DUPLEX_BIT; + speed_mode = (val & (BIT(15) | BIT(14))) >> YTXXXX_SPEED_MODE_BIT; + switch (speed_mode) { + case 0: + speed = SPEED_10; + break; + case 1: + speed = SPEED_100; + break; + case 2: + case 3: + default: + speed = SPEED_UNKNOWN; + break; + } + + phydev->link = 1; + phydev->speed = speed; + phydev->duplex = duplex; + + return 0; + } + + phydev->link = 0; + + return 0; +} + +static int yt8522_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct yt8xxx_priv *priv; + int chip_config; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + chip_config = ytphy_read_ext(phydev, YT8522_EXTENDED_COMBO_CTRL_1); + + priv->chip_mode = ((chip_config & BIT(3)) >> 3); + + return 0; +} + +static int yt8522_config_init(struct phy_device *phydev) +{ + struct yt8xxx_priv *priv = phydev->priv; + int ret; + int val; + + /* UTP */ + if (!priv->chip_mode) { + val = ytphy_write_ext(phydev, YT8522_TX_CLK_DELAY, 0); + if (val < 0) + return val; + + val = ytphy_write_ext(phydev, YT8522_ANAGLOG_IF_CTRL, 0xbf2a); + if (val < 0) + return val; + + val = ytphy_write_ext(phydev, YT8522_DAC_CTRL, 0x297f); + if (val < 0) + return val; + + val = ytphy_write_ext(phydev, YT8522_INTERPOLATOR_FILTER_1, 0x1FE); + if (val < 0) + return val; + + val = ytphy_write_ext(phydev, YT8522_INTERPOLATOR_FILTER_2, 0x1FE); + if (val < 0) + return val; + + /* disable auto sleep */ + val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1); + if (val < 0) + return val; + + val &= (~BIT(YT8512_EN_SLEEP_SW_BIT)); + + ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val); + if (ret < 0) + return ret; + + ytphy_soft_reset(phydev); + } + + return 0; +} + static int yt8531_rxclk_duty_init(struct phy_device *phydev) { unsigned int value = 0x9696; @@ -1045,6 +1170,17 @@ static struct phy_driver motorcomm_phy_drvs[] = { .suspend = genphy_suspend, .resume = genphy_resume, }, { + PHY_ID_MATCH_EXACT(PHY_ID_YT8522), + .name = "YT8522 100M Ethernet", + .features = PHY_BASIC_FEATURES, + .probe = yt8522_probe, + .soft_reset = ytphy_soft_reset, + .config_aneg = genphy_config_aneg, + .config_init = yt8522_config_init, + .read_status = yt8522_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { /* same as 8521 */ PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), .name = "YT8531S Gigabit Ethernet", @@ -1084,6 +1220,7 @@ static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, { PHY_ID_MATCH_EXACT(PHY_ID_YT8512) }, { PHY_ID_MATCH_EXACT(PHY_ID_YT8512B) }, + { PHY_ID_MATCH_EXACT(PHY_ID_YT8522) }, { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, { /* sentinal */ } From ff726840516b91ac1b03d655ae38c44566057079 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 2 Jul 2024 21:17:14 +0800 Subject: [PATCH 022/191] ASoC: generic-dmaengine-pcm: Add support for dma chan request dynamically Change-Id: I187b4292c75ed1195bded805e58c8346f9e4074c Signed-off-by: Sugar Zhang --- sound/soc/Kconfig | 4 ++++ sound/soc/soc-generic-dmaengine-pcm.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 848fbae26c3b..c760b72a3bfb 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -30,6 +30,10 @@ config SND_SOC_GENERIC_DMAENGINE_PCM bool select SND_DMAENGINE_PCM +config SND_SOC_DYNAMIC_DMA_CHAN + bool "Request dma chan dynamically" + depends on SND_SOC_GENERIC_DMAENGINE_PCM + config SND_SOC_COMPRESS bool select SND_COMPRESS_OFFLOAD diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c index 3b99f619e37e..38866b98fae4 100644 --- a/sound/soc/soc-generic-dmaengine-pcm.c +++ b/sound/soc/soc-generic-dmaengine-pcm.c @@ -156,12 +156,23 @@ static int dmaengine_pcm_open(struct snd_soc_component *component, if (ret) return ret; + if (IS_ENABLED(CONFIG_SND_SOC_DYNAMIC_DMA_CHAN)) { + chan = dma_request_chan(component->dev, substream->stream ? "rx" : "tx"); + if (IS_ERR(chan)) { + dev_err(component->dev, "No DMA channel available\n"); + return -ENXIO; + } + } + return snd_dmaengine_pcm_open(substream, chan); } static int dmaengine_pcm_close(struct snd_soc_component *component, struct snd_pcm_substream *substream) { + if (IS_ENABLED(CONFIG_SND_SOC_DYNAMIC_DMA_CHAN)) + return snd_dmaengine_pcm_close_release_chan(substream); + return snd_dmaengine_pcm_close(substream); } @@ -458,6 +469,9 @@ int snd_dmaengine_pcm_register(struct device *dev, if (ret) goto err_free_dma; + if (IS_ENABLED(CONFIG_SND_SOC_DYNAMIC_DMA_CHAN)) + dmaengine_pcm_release_chan(pcm); + return 0; err_free_dma: From 71ea8ca8350a68f18bca9680fc85fb4b45ce2e0f Mon Sep 17 00:00:00 2001 From: Wang Panzhenzhuan Date: Thu, 11 Jul 2024 19:43:13 +0800 Subject: [PATCH 023/191] media: i2c: gc05a2: add set flip & mirror support note: gc05a2 flip & mirror use the same register; but write value to the register not valid immediately, so need record it in variable, to avoid being covered. Signed-off-by: Wang Panzhenzhuan Change-Id: Ice9c9fcefdbf9fa56a83f9b049e434cfe1c23bba --- drivers/media/i2c/gc05a2.c | 84 +++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 46 deletions(-) diff --git a/drivers/media/i2c/gc05a2.c b/drivers/media/i2c/gc05a2.c index 233063592e03..bb4f7ab6ccc5 100644 --- a/drivers/media/i2c/gc05a2.c +++ b/drivers/media/i2c/gc05a2.c @@ -8,6 +8,7 @@ * V0.0X01.0X01 update sensor driver. * 1. adjust power sequence to suit spec. * 2. fix bayer pattern to suit setting. + * V0.0X01.0X02 add mirror & flip support. */ #include @@ -81,6 +82,10 @@ #define GC05A2_REG_VTS_H 0x0340 #define GC05A2_REG_VTS_L 0x0341 +#define GC05A2_FLIP_MIRROR_REG 0x0101 +#define MIRROR_BIT_MASK BIT(0) +#define FLIP_BIT_MASK BIT(1) + #define REG_NULL 0xFFFF #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" @@ -139,6 +144,9 @@ struct gc05a2 { struct v4l2_ctrl *hblank; struct v4l2_ctrl *vblank; struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + u8 flip_mirror; struct mutex mutex; bool streaming; unsigned int lane_num; @@ -157,49 +165,6 @@ struct gc05a2 { #define to_gc05a2(sd) container_of(sd, struct gc05a2, subdev) -#undef GC05A2_MIRROR_NORMAL -#undef GC05A2_MIRROR_H -#undef GC05A2_MIRROR_V -#undef GC05A2_MIRROR_HV - -/* SENSOR MIRROR FLIP INFO */ -#define GC05A2_MIRROR_NORMAL 0 -#define GC05A2_MIRROR_H 1 -#define GC05A2_MIRROR_V 0 -#define GC05A2_MIRROR_HV 0 - -#if GC05A2_MIRROR_NORMAL - #define GC05A2_MIRROR 0x00 - #define FULL_STARTY 0x06 - #define FULL_STARTX 0x08 - #define BINNING_STARTY 0x03 - #define BINNING_STARTX 0x03 -#elif GC05A2_MIRROR_H - #define GC05A2_MIRROR 0x01 - #define FULL_STARTY 0x06 - #define FULL_STARTX 0x09 - #define BINNING_STARTY 0x03 - #define BINNING_STARTX 0x04 -#elif GC05A2_MIRROR_V - #define GC05A2_MIRROR 0x02 - #define FULL_STARTY 0x07 - #define FULL_STARTX 0x08 - #define BINNING_STARTY 0x04 - #define BINNING_STARTX 0x03 -#elif GC05A2_MIRROR_HV - #define GC05A2_MIRROR 0x03 - #define FULL_STARTY 0x07 - #define FULL_STARTX 0x09 - #define BINNING_STARTY 0x04 - #define BINNING_STARTX 0x04 -#else - #define GC05A2_MIRROR 0x00 - #define FULL_STARTY 0x06 - #define FULL_STARTX 0x08 - #define BINNING_STARTY 0x03 - #define BINNING_STARTX 0x03 -#endif - /* * Xclk 24Mhz */ @@ -1136,6 +1101,7 @@ static int gc05a2_s_power(struct v4l2_subdev *sd, int on) goto unlock_and_return; } + gc05a2->flip_mirror = 0; ret = gc05a2_write_array(gc05a2->client, gc05a2->cur_mode->global_reg_list); if (ret) { v4l2_err(sd, "could not set init registers\n"); @@ -1421,15 +1387,15 @@ static int gc05a2_set_ctrl(struct v4l2_ctrl *ctrl) switch (ctrl->id) { case V4L2_CID_EXPOSURE: /* 4 least significant bits of expsoure are fractional part */ - dev_info(&client->dev, "set exposure value 0x%x\n", ctrl->val); + dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val); ret = gc05a2_set_exposure_reg(gc05a2, ctrl->val); break; case V4L2_CID_ANALOGUE_GAIN: - dev_info(&client->dev, "set analog gain value 0x%x\n", ctrl->val); + dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val); ret = gc05a2_set_gain_reg(gc05a2, ctrl->val); break; case V4L2_CID_VBLANK: - dev_info(&client->dev, "set vb value 0x%x\n", ctrl->val); + dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val); ret = gc05a2_write_reg(gc05a2->client, GC05A2_REG_VTS_H, (ctrl->val + gc05a2->cur_mode->height) @@ -1439,6 +1405,27 @@ static int gc05a2_set_ctrl(struct v4l2_ctrl *ctrl) (ctrl->val + gc05a2->cur_mode->height) & 0xff); break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "set mirror value 0x%x\n", ctrl->val); + + if (ctrl->val) + gc05a2->flip_mirror |= MIRROR_BIT_MASK; + else + gc05a2->flip_mirror &= ~MIRROR_BIT_MASK; + + ret |= gc05a2_write_reg(gc05a2->client, GC05A2_FLIP_MIRROR_REG, + gc05a2->flip_mirror); + break; + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "set flip value 0x%x\n", ctrl->val); + if (ctrl->val) + gc05a2->flip_mirror |= FLIP_BIT_MASK; + else + gc05a2->flip_mirror &= ~FLIP_BIT_MASK; + + ret |= gc05a2_write_reg(gc05a2->client, GC05A2_FLIP_MIRROR_REG, + gc05a2->flip_mirror); + break; default: dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", __func__, ctrl->id, ctrl->val); @@ -1501,6 +1488,11 @@ static int gc05a2_initialize_controls(struct gc05a2 *gc05a2) V4L2_CID_ANALOGUE_GAIN, GC05A2_AGAIN_MIN, GC05A2_AGAIN_MAX, GC05A2_AGAIN_STEP, GC05A2_AGAIN_DEFAULT); + gc05a2->h_flip = v4l2_ctrl_new_std(handler, &gc05a2_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + + gc05a2->v_flip = v4l2_ctrl_new_std(handler, &gc05a2_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); if (handler->error) { ret = handler->error; From a21414874a58adcab03b768babe7dc45612cab01 Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Tue, 16 Jul 2024 11:46:58 +0800 Subject: [PATCH 024/191] arm64: dts: rockchip: rk3576-tablet: add sleep property for es8388 pa control fix es8388 pop issue Signed-off-by: Binyuan Lan Change-Id: I789da309197061e67bc9690654b76ad6fc043cf2 --- arch/arm64/boot/dts/rockchip/rk3576-tablet-v10.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-tablet-v10.dts index eed648ef4430..c75eb2e8bae5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-tablet-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-tablet-v10.dts @@ -141,6 +141,8 @@ poll-interval = <100>; spk-con-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; hp-con-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,pre-power-on-delay-ms = <30>; + rockchip,post-power-down-delay-ms = <40>; rockchip,format = "i2s"; rockchip,mclk-fs = <256>; rockchip,cpu = <&sai1>; From 6e99cb3d8487863f6d85e33d9ef98a688604a9bb Mon Sep 17 00:00:00 2001 From: "damon.ding" Date: Fri, 21 Jun 2024 16:05:52 +0800 Subject: [PATCH 025/191] phy/rockchip: samsung-hdptx: modify pe/vs/pll configs for R216/R243/R324/R432 According to the SI report, modify pe/vs configs of new link rate R216/R243/R324/R432, which are configured to nearby RBR/HBR/HBR2 configs in the past. In addition, modify the pll configs to pass SSC test. Change-Id: Ic10ea8289f47cfc93bd2c08231b76c68a6e4b4d2 Signed-off-by: damon.ding --- .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 127 +++++++++++++++++- 1 file changed, 122 insertions(+), 5 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 98890994e7ca..036e8ac657a5 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -459,12 +459,96 @@ static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { } }; +static struct tx_drv_ctrl tx_drv_ctrl_r216_r243[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x0, 0x1, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x1, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x1, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x3, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x3, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x1, 0x1, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x1, 0x2, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x3, 0x2, 0x2, 0x2, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + } +}; + +static struct tx_drv_ctrl tx_drv_ctrl_r324[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x2, 0x4, 0x5, 0x5, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x4, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x2, 0x3, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x4, 0x5, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x3, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + } +}; + +static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x1, 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x2, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x2, 0x4, 0x6, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x4, 0x6, 0x6, 0x6, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x3, 0x4, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x5, 0x6, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x2, 0x2, 0x4, 0x4, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x4, 0x4, 0x4, 0x4, 0x0, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x5, 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + } +}; + /* pll configurations for link rate R216/R243/R324/R432 */ -static struct tx_pll_ctrl tx_pll_ctrl_extra[4] = { - { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0f, 0x18 }, /* R216 */ - { 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x20, 0x0b }, /* R243 */ - { 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0e, 0x1a }, /* R324 */ - { 0x5a, 0x00, 0x32, 0x00, 0x00, 0x00, 0x01, 0x01, 0x0f, 0x18 }, /* R432 */ +static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = { + { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */ + { 0x65, 0x01, 0x60, 0x00, 0x10, 0x01, 0x13, 0x18, 0x1c, 0x0d }, /* R243 */ + { 0x87, 0x01, 0x21, 0x00, 0x00, 0x02, 0x03, 0x08, 0x0d, 0x1c }, /* R324 */ + { 0x5a, 0x00, 0x32, 0x00, 0x00, 0x01, 0x01, 0x01, 0x0e, 0x1a }, /* R432 */ }; static int rockchip_hdptx_phy_parse_training_table(struct device *dev) @@ -580,6 +664,17 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, break; case 2160: case 2430: + ctrl = &tx_drv_ctrl_r216_r243[dp->voltage[lane]][dp->pre[lane]]; + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), + LN_TX_SER_40BIT_EN_HBR, + FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), + LN_TX_JEQ_EVEN_CTRL_HBR, + FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, ctrl->tx_jeq_even_ctrl)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), + LN_TX_JEQ_ODD_CTRL_HBR, + FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl)); + break; case 2700: ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), @@ -593,7 +688,29 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl)); break; case 3240: + ctrl = &tx_drv_ctrl_r324[dp->voltage[lane]][dp->pre[lane]]; + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), + LN_TX_SER_40BIT_EN_HBR2, + FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), + LN_TX_JEQ_EVEN_CTRL_HBR2, + FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), + LN_TX_JEQ_ODD_CTRL_HBR2, + FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl)); + break; case 4320: + ctrl = &tx_drv_ctrl_r432[dp->voltage[lane]][dp->pre[lane]]; + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), + LN_TX_SER_40BIT_EN_HBR2, + FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), + LN_TX_JEQ_EVEN_CTRL_HBR2, + FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, ctrl->tx_jeq_even_ctrl)); + regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), + LN_TX_JEQ_ODD_CTRL_HBR2, + FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, ctrl->tx_jeq_odd_ctrl)); + break; case 5400: default: ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; From 764ff0a4cb2ecf027990d96a30df9bcb78b85f72 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 15 Jul 2024 15:26:51 +0800 Subject: [PATCH 026/191] drm/rockchip: vop2: get power_ctrl default value and backup to regsbak Read default register value and backup to regsbak must after pd power on, so we can get correctly value, but the pd power on action depend on regsbak, so we add extra regsbak for power_ctrl. Fixes: 6282856b6707 ("drm/rockchip: vop2: move power up plane pd before read regsbak") Signed-off-by: Sandy Huang Change-Id: I465b0ec76d4e1233c40e79528ee42b5c5c2fb727 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 353fdd521f61..dfd6fcf9fa5b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4293,7 +4293,13 @@ static void vop2_initial(struct drm_crtc *crtc) */ if (vop2->version == VOP_VERSION_RK3588) { struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART); + u32 pd_offset = esmart_pd->data->regs->pd.offset; + /* + * Get power_ctrl default value and backup to regsbak, + * so we can config pd register correctly as expected. + */ + vop2->regsbak[pd_offset >> 2] = vop2_readl(vop2, pd_offset); if (vop2_power_domain_status(esmart_pd)) esmart_pd->on = true; else @@ -4302,10 +4308,14 @@ static void vop2_initial(struct drm_crtc *crtc) struct vop2_power_domain *pd, *n; list_for_each_entry_safe_reverse(pd, n, &vop2->pd_list_head, list) { - if (vop2_power_domain_status(pd)) + if (vop2_power_domain_status(pd)) { pd->on = true; - else + } else { + u32 pd_offset = pd->data->regs->pd.offset; + + vop2->regsbak[pd_offset >> 2] = vop2_readl(vop2, pd_offset); vop2_power_domain_on(pd); + } } } From 40487a94b232866dcce25b44f1ffc01ce0a11698 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 15 Jul 2024 15:37:08 +0800 Subject: [PATCH 027/191] drm/rockchip: vop2: to access dsc register must after enable dsc pd and release reset Signed-off-by: Sandy Huang Change-Id: I80d18b8f0b4dadc62c8304b5b62186691a684dd9 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index dfd6fcf9fa5b..d42fbe92a93c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4428,7 +4428,9 @@ static void vop2_initial(struct drm_crtc *crtc) if (!dsc->pd) continue; - if (!vop2_power_domain_status(dsc->pd)) + /* To access dsc register must after enable dsc pd and release reset */ + if (!vop2_power_domain_status(dsc->pd) || + !VOP_MODULE_GET(vop2, dsc, rst_deassert)) continue; dsc->enabled = VOP_MODULE_GET(vop2, dsc, dsc_en); From d126fcad4a5d939a90f4779ad73f10228cce6a31 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Mon, 15 Jul 2024 15:44:54 +0800 Subject: [PATCH 028/191] drm/rockchip: vop2: move rk3588 pd control together This is a merge error at following commit: commit 32062f68cc72 ("drm/rockchip: vop2: update dsc pd status when show logo with dsc") Signed-off-by: Sandy Huang Change-Id: I603abd28fb9e1ccdbb06fa1e25c3a64b35b8d293 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 64 +++++++++----------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index d42fbe92a93c..3b34c70a095e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -4304,6 +4304,33 @@ static void vop2_initial(struct drm_crtc *crtc) esmart_pd->on = true; else vop2_power_domain_on(esmart_pd); + + if (vop2->data->nr_dscs) { + struct vop2_dsc *dsc; + int i = 0; + + for (i = 0; i < vop2->data->nr_dscs; i++) { + dsc = &vop2->dscs[i]; + + if (!dsc->pd) + continue; + + /* To access dsc register must after enable dsc pd and release reset */ + if (!vop2_power_domain_status(dsc->pd) || + !VOP_MODULE_GET(vop2, dsc, rst_deassert)) + continue; + + dsc->enabled = VOP_MODULE_GET(vop2, dsc, dsc_en); + + if (dsc->enabled) { + dsc->attach_vp_id = VOP_MODULE_GET(vop2, dsc, + dsc_port_sel); + dsc->pd->vp_mask = BIT(dsc->attach_vp_id); + dsc->pd->on = true; + dsc->pd->ref_count++; + } + } + } } else { struct vop2_power_domain *pd, *n; @@ -4408,43 +4435,6 @@ static void vop2_initial(struct drm_crtc *crtc) * immediately. */ VOP_CTRL_SET(vop2, if_ctrl_cfg_done_imd, 1); - - /* Close dynamic turn on/off rk3588 PD_ESMART and keep esmart pd on when enable */ - if (vop2->version == VOP_VERSION_RK3588) { - struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART); - - if (vop2_power_domain_status(esmart_pd)) - esmart_pd->on = true; - else - vop2_power_domain_on(esmart_pd); - - if (vop2->data->nr_dscs) { - struct vop2_dsc *dsc; - int i = 0; - - for (i = 0; i < vop2->data->nr_dscs; i++) { - dsc = &vop2->dscs[i]; - - if (!dsc->pd) - continue; - - /* To access dsc register must after enable dsc pd and release reset */ - if (!vop2_power_domain_status(dsc->pd) || - !VOP_MODULE_GET(vop2, dsc, rst_deassert)) - continue; - - dsc->enabled = VOP_MODULE_GET(vop2, dsc, dsc_en); - - if (dsc->enabled) { - dsc->attach_vp_id = VOP_MODULE_GET(vop2, dsc, - dsc_port_sel); - dsc->pd->vp_mask = BIT(dsc->attach_vp_id); - dsc->pd->on = true; - dsc->pd->ref_count++; - } - } - } - } vop2_layer_map_initial(vop2, current_vp_id); vop2_axi_irqs_enable(vop2); vop2->is_enabled = true; From aa2994fbdb364a50cae8fb062fec63bb0a84cc95 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Tue, 16 Jul 2024 11:38:04 +0800 Subject: [PATCH 029/191] video: rockchip: rga3: fix YUV-10bit offset calculation error Signed-off-by: Yu Qiaowei Change-Id: I2a3719e396a129a8d805bd87f5b39365dbc34922 --- drivers/video/rockchip/rga3/rga2_reg_info.c | 25 ++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index d5302e91c756..531401e45054 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -252,9 +252,11 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) u8 src0_cbcr_swp = 0; u8 pixel_width = 1; u8 plane_width = 0; + u8 pixel_depth = 8; u32 stride = 0; u32 uv_stride = 0; u32 mask_stride = 0; + u32 byte_stride = 0; u32 ydiv = 1, xdiv = 2; u8 yuv10 = 0; @@ -562,6 +564,7 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) case RGA_FORMAT_YCbCr_420_SP_10B: src0_format = 0xa; plane_width = 2; + pixel_depth = 10; xdiv = 2; ydiv = 2; yuv10 = 1; @@ -569,6 +572,7 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) case RGA_FORMAT_YCrCb_420_SP_10B: src0_format = 0xa; plane_width = 2; + pixel_depth = 10; xdiv = 2; ydiv = 2; src0_cbcr_swp = 1; @@ -577,6 +581,7 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) case RGA_FORMAT_YCbCr_422_SP_10B: src0_format = 0x8; plane_width = 2; + pixel_depth = 10; xdiv = 2; ydiv = 1; yuv10 = 1; @@ -584,6 +589,7 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) case RGA_FORMAT_YCrCb_422_SP_10B: src0_format = 0x8; plane_width = 2; + pixel_depth = 10; xdiv = 2; ydiv = 1; src0_cbcr_swp = 1; @@ -615,12 +621,25 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg) switch (msg->src.rd_mode) { case RGA_RASTER_MODE: - stride = ALIGN(msg->src.vir_w * pixel_width, 4); + if (msg->src.format == RGA_FORMAT_YCbCr_420_SP_10B || + msg->src.format == RGA_FORMAT_YCrCb_420_SP_10B || + msg->src.format == RGA_FORMAT_YCbCr_422_SP_10B || + msg->src.format == RGA_FORMAT_YCrCb_422_SP_10B) + /* + * Legacy: implicit semantics exist here, 10bit format + * width_stride equals byte_stride. + */ + byte_stride = msg->src.vir_w; + else + byte_stride = msg->src.vir_w * pixel_width * pixel_depth / 8; + + stride = ALIGN(byte_stride, 4); uv_stride = ALIGN(msg->src.vir_w / xdiv * plane_width, 4); - yrgb_offset = msg->src.y_offset * stride + msg->src.x_offset * pixel_width; + yrgb_offset = msg->src.y_offset * stride + + msg->src.x_offset * pixel_width * pixel_depth / 8; uv_offset = (msg->src.y_offset / ydiv) * uv_stride + - (msg->src.x_offset / xdiv * plane_width); + (msg->src.x_offset / xdiv * plane_width * pixel_depth / 8); v_offset = uv_offset; break; From faf338e81ae661b307fe9db12770ffa89baa6285 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 16 Jul 2024 16:46:39 +0800 Subject: [PATCH 030/191] drm/rockchip: dw-dp: force-hpd get the connect status as connected For force-hpd, It should be regard as always connected, so it don't read the register to get the connect status. Change-Id: I7082bb1ae56a640a43a800b9a934da7700e76de5 Signed-off-by: Zhang Yubing --- drivers/gpu/drm/rockchip/dw-dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c index 79e2a3e8a697..d26c01ce8771 100644 --- a/drivers/gpu/drm/rockchip/dw-dp.c +++ b/drivers/gpu/drm/rockchip/dw-dp.c @@ -1142,6 +1142,9 @@ static bool dw_dp_detect_no_power(struct dw_dp *dp) if (dp->usbdp_hpd) return dp->hotplug.status; + if (dp->force_hpd) + return true; + ret = regmap_read_poll_timeout(dp->regmap, DPTX_HPD_STATUS, value, FIELD_GET(HPD_STATE, value) != SOURCE_STATE_UNPLUG, 100, 3000); From 5b8d7ddc4d6ba4f4ac607f25cc93d32c1bf02d5b Mon Sep 17 00:00:00 2001 From: Xu Xuehui Date: Wed, 3 Jul 2024 10:40:54 +0800 Subject: [PATCH 031/191] Revert "rtc: s35390a: set 32K register when resume" This reverts commit 7f151d91707581164ebdb053d520d67307ff2437. Signed-off-by: Xu Xuehui Change-Id: I4839139c400d73bcb1ecbed87604e7838bdd8173 --- drivers/rtc/rtc-s35390a.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/rtc/rtc-s35390a.c b/drivers/rtc/rtc-s35390a.c index 6949afcb62f5..a3bc2003852d 100644 --- a/drivers/rtc/rtc-s35390a.c +++ b/drivers/rtc/rtc-s35390a.c @@ -460,22 +460,6 @@ static int s35390a_rtc_ioctl(struct device *dev, unsigned int cmd, return 0; } -#ifdef CONFIG_PM_SLEEP -static int s35390a_resume(struct device *dev) -{ - struct i2c_client *client = to_i2c_client(dev); - struct s35390a *s35390a = i2c_get_clientdata(client); - char buf; - - buf = S35390A_INT2_MODE_32K; - s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &buf, sizeof(buf)); - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(s35390a_pm_ops, NULL, s35390a_resume); - static const struct rtc_class_ops s35390a_rtc_ops = { .read_time = s35390a_rtc_read_time, .set_time = s35390a_rtc_set_time, @@ -571,7 +555,6 @@ static int s35390a_probe(struct i2c_client *client) static struct i2c_driver s35390a_driver = { .driver = { .name = "rtc-s35390a", - .pm = &s35390a_pm_ops, .of_match_table = of_match_ptr(s35390a_of_match), }, .probe_new = s35390a_probe, From 74ec6378c5cca450b899d3cfd30fcec19a08d6fc Mon Sep 17 00:00:00 2001 From: Xu Xuehui Date: Wed, 3 Jul 2024 10:40:54 +0800 Subject: [PATCH 032/191] rtc: s35390a: Correct RTC alarm behavior to maintain 32KHz output When setting an RTC alarm, the S35390A_CMD_STATUS2 register will be set again, which unintentionally disables the 32KHz output, this commit adds the necessary configuration to set the S35390A_INT2_MODE_32K, ensuring that the 32KHz output remains enabled at all times. as a result of this change, the previous commit 7f151d91707581164ebdb053d520d67307ff2437 is no longer necessary. Signed-off-by: Xu Xuehui Change-Id: I8607899676bd624e00032eeca1a21a0658f3b71a --- drivers/rtc/rtc-s35390a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-s35390a.c b/drivers/rtc/rtc-s35390a.c index a3bc2003852d..fb0e0c36131c 100644 --- a/drivers/rtc/rtc-s35390a.c +++ b/drivers/rtc/rtc-s35390a.c @@ -344,7 +344,7 @@ static int s35390a_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) return err; if (alm->enabled) - sts = S35390A_INT2_MODE_ALARM; + sts = S35390A_INT2_MODE_ALARM | S35390A_INT2_MODE_32K; else sts = S35390A_INT2_MODE_NOINTR; From ec81e6557ef65ff50c39f83318156a5cc7a65de2 Mon Sep 17 00:00:00 2001 From: Troy Lin Date: Tue, 16 Jul 2024 16:06:24 +0800 Subject: [PATCH 033/191] crypto: rockchip: v2/v3: drop unused struct rk_ahash_expt_ctx Signed-off-by: Troy Lin Change-Id: I5da997756902ba90da3393a085b08e2d903dc180 --- drivers/crypto/rockchip/rk_crypto_v2_ahash.c | 11 +++-------- drivers/crypto/rockchip/rk_crypto_v3_ahash.c | 11 +++-------- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c index 919603ff4768..d9c1f1a46c45 100644 --- a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c @@ -22,11 +22,6 @@ #define RK_POLL_PERIOD_US 100 #define RK_POLL_TIMEOUT_US 50000 -struct rk_ahash_expt_ctx { - struct rk_ahash_ctx ctx; - u8 lastc[RK_DMA_ALIGNMENT]; -}; - static const u32 hash_algo2bc[] = { [HASH_ALGO_MD5] = CRYPTO_MD5, [HASH_ALGO_SHA1] = CRYPTO_SHA1, @@ -187,7 +182,7 @@ static void clean_hash_setting(struct rk_crypto_dev *rk_dev) static int rk_ahash_import(struct ahash_request *req, const void *in) { - struct rk_ahash_expt_ctx state; + struct rk_ahash_ctx state; /* 'in' may not be aligned so memcpy to local variable */ memcpy(&state, in, sizeof(state)); @@ -199,7 +194,7 @@ static int rk_ahash_import(struct ahash_request *req, const void *in) static int rk_ahash_export(struct ahash_request *req, void *out) { - struct rk_ahash_expt_ctx state; + struct rk_ahash_ctx state; /* Don't let anything leak to 'out' */ memset(&state, 0, sizeof(state)); @@ -346,7 +341,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct rk_ahash_rctx)); - algt->alg.hash.halg.statesize = sizeof(struct rk_ahash_expt_ctx); + algt->alg.hash.halg.statesize = sizeof(struct rk_ahash_ctx); return 0; } diff --git a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c index 8838cc625bb4..eb524cfee4e8 100644 --- a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c @@ -21,11 +21,6 @@ #define RK_POLL_PERIOD_US 100 #define RK_POLL_TIMEOUT_US 50000 -struct rk_ahash_expt_ctx { - struct rk_ahash_ctx ctx; - u8 lastc[RK_DMA_ALIGNMENT]; -}; - struct rk_hash_mid_data { u32 valid_flag; u32 hash_ctl; @@ -267,7 +262,7 @@ static void clean_hash_setting(struct rk_crypto_dev *rk_dev) static int rk_ahash_import(struct ahash_request *req, const void *in) { - struct rk_ahash_expt_ctx state; + struct rk_ahash_ctx state; /* 'in' may not be aligned so memcpy to local variable */ memcpy(&state, in, sizeof(state)); @@ -279,7 +274,7 @@ static int rk_ahash_import(struct ahash_request *req, const void *in) static int rk_ahash_export(struct ahash_request *req, void *out) { - struct rk_ahash_expt_ctx state; + struct rk_ahash_ctx state; /* Don't let anything leak to 'out' */ memset(&state, 0, sizeof(state)); @@ -441,7 +436,7 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct rk_ahash_rctx)); - algt->alg.hash.halg.statesize = sizeof(struct rk_ahash_expt_ctx); + algt->alg.hash.halg.statesize = sizeof(struct rk_ahash_ctx); return 0; } From b21ab65f3af57868a593be97d1ad70a8cdba4e6a Mon Sep 17 00:00:00 2001 From: Troy Lin Date: Tue, 16 Jul 2024 16:09:24 +0800 Subject: [PATCH 034/191] crypto: rockchip: Configure reserve block size based on CRYPTO version CRYPTO_V2 : rk_hash_reserve_block = 128 CRYPTO_V3/V4 : rk_hash_reserve_block = 64 Signed-off-by: Troy Lin Change-Id: I2a22d6084cb0f111f54c73939180fa7bbed29ef0 --- drivers/crypto/rockchip/rk_crypto_ahash_utils.c | 14 ++++++++------ drivers/crypto/rockchip/rk_crypto_ahash_utils.h | 2 ++ drivers/crypto/rockchip/rk_crypto_core.h | 5 +++-- drivers/crypto/rockchip/rk_crypto_v2_ahash.c | 8 +++++--- drivers/crypto/rockchip/rk_crypto_v3_ahash.c | 8 +++++--- 5 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/crypto/rockchip/rk_crypto_ahash_utils.c b/drivers/crypto/rockchip/rk_crypto_ahash_utils.c index 495c55485f14..29873554c05c 100644 --- a/drivers/crypto/rockchip/rk_crypto_ahash_utils.c +++ b/drivers/crypto/rockchip/rk_crypto_ahash_utils.c @@ -11,6 +11,8 @@ #include "rk_crypto_core.h" #include "rk_crypto_ahash_utils.h" +uint32_t rk_hash_reserve_block = RK_HASH_RESERVE_BLOCK; + static const char * const hash_algo2name[] = { [HASH_ALGO_MD5] = "md5", [HASH_ALGO_SHA1] = "sha1", @@ -35,7 +37,7 @@ static void rk_ahash_ctx_clear(struct rk_ahash_ctx *ctx) { rk_alg_ctx_clear(&ctx->algs_ctx); - memset(ctx->hash_tmp, 0x00, RK_DMA_ALIGNMENT); + memset(ctx->hash_tmp, 0x00, RK_HASH_RESERVE_BLOCK); memset(ctx->lastc, 0x00, sizeof(ctx->lastc)); ctx->hash_tmp_len = 0; @@ -81,13 +83,13 @@ static u32 rk_calc_lastc_new_len(u32 nbytes, u32 old_len) { u32 total_len = nbytes + old_len; - if (total_len <= RK_DMA_ALIGNMENT) + if (total_len <= rk_hash_reserve_block) return nbytes; - if (total_len % RK_DMA_ALIGNMENT) - return total_len % RK_DMA_ALIGNMENT; + if (total_len % rk_hash_reserve_block) + return total_len % rk_hash_reserve_block; - return RK_DMA_ALIGNMENT; + return rk_hash_reserve_block; } static int rk_ahash_fallback_digest(const char *alg_name, bool is_hmac, @@ -326,7 +328,7 @@ int rk_ahash_start(struct rk_crypto_dev *rk_dev) nbytes = ctx->hash_tmp_len + req->nbytes - ctx->lastc_len; /* not enough data */ - if (nbytes < RK_DMA_ALIGNMENT) { + if (nbytes < rk_hash_reserve_block) { CRYPTO_TRACE("nbytes = %u, not enough data", nbytes); memcpy(ctx->hash_tmp + ctx->hash_tmp_len, ctx->lastc, ctx->lastc_len); diff --git a/drivers/crypto/rockchip/rk_crypto_ahash_utils.h b/drivers/crypto/rockchip/rk_crypto_ahash_utils.h index 46afd98a0252..6110bd97bc43 100644 --- a/drivers/crypto/rockchip/rk_crypto_ahash_utils.h +++ b/drivers/crypto/rockchip/rk_crypto_ahash_utils.h @@ -10,6 +10,8 @@ #include "rk_crypto_core.h" #include "rk_crypto_utils.h" +extern uint32_t rk_hash_reserve_block; + struct rk_alg_ctx *rk_ahash_alg_ctx(struct rk_crypto_dev *rk_dev); struct rk_crypto_algt *rk_ahash_get_algt(struct crypto_ahash *tfm); diff --git a/drivers/crypto/rockchip/rk_crypto_core.h b/drivers/crypto/rockchip/rk_crypto_core.h index aba37a9cc1b0..a793cf87457d 100644 --- a/drivers/crypto/rockchip/rk_crypto_core.h +++ b/drivers/crypto/rockchip/rk_crypto_core.h @@ -42,7 +42,8 @@ #define RK_BUFFER_ORDER 3 #define RK_BUFFER_SIZE (PAGE_SIZE << RK_BUFFER_ORDER) -#define RK_DMA_ALIGNMENT 128 +#define RK_HASH_RESERVE_BLOCK 128 + #define sha384_state sha512_state #define sha224_state sha256_state @@ -175,7 +176,7 @@ struct rk_ahash_ctx { bool hash_tmp_mapped; u32 calc_cnt; - u8 lastc[RK_DMA_ALIGNMENT]; + u8 lastc[RK_HASH_RESERVE_BLOCK]; u32 lastc_len; void *priv; diff --git a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c index d9c1f1a46c45..b189fcb30bbf 100644 --- a/drivers/crypto/rockchip/rk_crypto_v2_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v2_ahash.c @@ -220,9 +220,9 @@ static int rk_ahash_dma_start(struct rk_crypto_dev *rk_dev, uint32_t flag) CRYPTO_TRACE("ctx->calc_cnt = %u, count %u Byte, is_final = %d", ctx->calc_cnt, alg_ctx->count, is_final); - if (alg_ctx->count % RK_DMA_ALIGNMENT && !is_final) { + if (alg_ctx->count % rk_hash_reserve_block && !is_final) { dev_err(rk_dev->dev, "count = %u is not aligned with [%u]\n", - alg_ctx->count, RK_DMA_ALIGNMENT); + alg_ctx->count, rk_hash_reserve_block); return -EINVAL; } @@ -313,12 +313,14 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) CRYPTO_TRACE(); + rk_hash_reserve_block = RK_HASH_RESERVE_BLOCK; + memset(ctx, 0x00, sizeof(*ctx)); if (!rk_dev->request_crypto) return -EFAULT; - alg_ctx->align_size = RK_DMA_ALIGNMENT; + alg_ctx->align_size = 64; alg_ctx->ops.start = rk_ahash_start; alg_ctx->ops.update = rk_ahash_crypto_rx; diff --git a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c index eb524cfee4e8..1a49e989f915 100644 --- a/drivers/crypto/rockchip/rk_crypto_v3_ahash.c +++ b/drivers/crypto/rockchip/rk_crypto_v3_ahash.c @@ -300,9 +300,9 @@ static int rk_ahash_dma_start(struct rk_crypto_dev *rk_dev, uint32_t flag) CRYPTO_TRACE("ctx->calc_cnt = %u, count %u Byte, is_final = %d", ctx->calc_cnt, alg_ctx->count, is_final); - if (alg_ctx->count % RK_DMA_ALIGNMENT && !is_final) { + if (alg_ctx->count % rk_hash_reserve_block && !is_final) { dev_err(rk_dev->dev, "count = %u is not aligned with [%u]\n", - alg_ctx->count, RK_DMA_ALIGNMENT); + alg_ctx->count, rk_hash_reserve_block); return -EINVAL; } @@ -400,12 +400,14 @@ static int rk_cra_hash_init(struct crypto_tfm *tfm) CRYPTO_TRACE(); + rk_hash_reserve_block = 64; + memset(ctx, 0x00, sizeof(*ctx)); if (!rk_dev->request_crypto) return -EFAULT; - alg_ctx->align_size = RK_DMA_ALIGNMENT; + alg_ctx->align_size = 64; alg_ctx->ops.start = rk_ahash_start; alg_ctx->ops.update = rk_ahash_crypto_rx; From 27568f17569f21f5b1dcbfcf127d9d7ae37bd3f2 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 12 Jul 2024 09:12:21 +0800 Subject: [PATCH 035/191] media: rockchip: vicap fixes scale intr error Signed-off-by: Zefa Chen Change-Id: Icd8f6dae6563c6ee7082e4ff158403faf80a37a0 --- drivers/media/platform/rockchip/cif/capture.c | 1 - drivers/media/platform/rockchip/cif/hw.c | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index d853c40c915b..7fd7a509c94b 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -12039,7 +12039,6 @@ unsigned int rkcif_irq_global(struct rkcif_device *cif_dev) intstat_glb); return 0; } - rkcif_irq_handle_scale(cif_dev, intstat_glb); return intstat_glb; } diff --git a/drivers/media/platform/rockchip/cif/hw.c b/drivers/media/platform/rockchip/cif/hw.c index b617a2a346fb..5b895e0d197b 100644 --- a/drivers/media/platform/rockchip/cif/hw.c +++ b/drivers/media/platform/rockchip/cif/hw.c @@ -1301,8 +1301,10 @@ static irqreturn_t rkcif_irq_handler(int irq, void *ctx) cif_hw->cif_dev[i]->err_state = 0; schedule_work(&cif_hw->cif_dev[i]->err_state_work.work); } - if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb) + if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb) { rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb); + rkcif_irq_handle_scale(cif_hw->cif_dev[i], intstat_glb); + } } } irq_stop = ktime_get_ns(); From 14a361a75bbfe196c1fcd57dae6bdf02d87a9a32 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 16 Jul 2024 10:41:23 +0800 Subject: [PATCH 036/191] media: rockchip: vicap fixes error of clean intr mask when stop stream Signed-off-by: Zefa Chen Change-Id: I5678f52e8a527b38eaa96ad4ae35e94addee525d --- drivers/media/platform/rockchip/cif/capture.c | 28 +++++++++++++------ 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c index 7fd7a509c94b..68a4f21164a5 100644 --- a/drivers/media/platform/rockchip/cif/capture.c +++ b/drivers/media/platform/rockchip/cif/capture.c @@ -4661,15 +4661,27 @@ static void rkcif_stream_stop(struct rkcif_stream *stream) rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val); } - rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, - CSI_START_INTSTAT(id) | - CSI_DMA_END_INTSTAT(id) | - CSI_LINE_INTSTAT(id)); + val = CSI_DMA_END_INTSTAT(id); + if (cif_dev->chip_id >= CHIP_RK3576_CIF) + val |= CSI_START_INTSTAT_RK3576(id); + else + val |= CSI_START_INTSTAT(id); + if (cif_dev->chip_id >= CHIP_RK3588_CIF) + val |= CSI_LINE_INTSTAT_V1(id); + else + val |= CSI_LINE_INTSTAT(id); + rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, val); - rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN, - ~(CSI_START_INTEN(id) | - CSI_DMA_END_INTEN(id) | - CSI_LINE_INTEN(id))); + val = CSI_DMA_END_INTEN(id); + if (cif_dev->chip_id >= CHIP_RK3576_CIF) + val |= CSI_START_INTEN_RK3576(id); + else + val |= CSI_START_INTEN(id); + if (cif_dev->chip_id >= CHIP_RK3588_CIF) + val |= CSI_LINE_INTEN_RK3588(id); + else + val |= CSI_LINE_INTEN(id); + rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN, ~val); if (stream->cifdev->chip_id < CHIP_RK3588_CIF) { rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN, From f056cfd8cd2380bec2a42b7658f9d39c130135db Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Fri, 12 Jul 2024 16:33:24 +0800 Subject: [PATCH 037/191] firmware: rockchip_sip: support access mem_os_reg Signed-off-by: XiaoDong Huang Change-Id: Ic28ea22e37a03dcc4e930320ac59992affd5e765 --- drivers/firmware/rockchip_sip.c | 16 ++++++++++++++++ include/linux/rockchip/rockchip_sip.h | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/firmware/rockchip_sip.c b/drivers/firmware/rockchip_sip.c index e483899d79fe..593e2f693464 100644 --- a/drivers/firmware/rockchip_sip.c +++ b/drivers/firmware/rockchip_sip.c @@ -264,6 +264,22 @@ struct arm_smccc_res sip_smc_lastlog_request(void) } EXPORT_SYMBOL_GPL(sip_smc_lastlog_request); +int sip_smc_access_mem_os_reg(u32 func, u32 id, u32 *val) +{ + struct arm_smccc_res res; + + if (val == NULL) + return SIP_RET_INVALID_PARAMS; + + res = __invoke_sip_fn_smc(SIP_ACCESS_MEM_OS_REG, func, id, *val); + + if (func == RK_MEM_OS_REG_READ) + *val = res.a1; + + return res.a0; +} +EXPORT_SYMBOL_GPL(sip_smc_access_mem_os_reg); + int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3) { struct arm_smccc_res res; diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h index 70b1493ef697..20b91a1dfa34 100644 --- a/include/linux/rockchip/rockchip_sip.h +++ b/include/linux/rockchip/rockchip_sip.h @@ -33,6 +33,7 @@ #define PSCI_SIP_VPU_RESET 0x8200000c #define SIP_BUS_CFG 0x8200000d #define SIP_LAST_LOG 0x8200000e +#define SIP_ACCESS_MEM_OS_REG 0x8200000f #define SIP_SCMI_AGENT0 0x82000010 #define SIP_SCMI_AGENT1 0x82000011 #define SIP_SCMI_AGENT2 0x82000012 @@ -120,6 +121,12 @@ /* wakeup state */ #define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf +/* SIP_ACCESS_MEM_OS_REG child configs */ +enum { + RK_MEM_OS_REG_READ = 0, + RK_MEM_OS_REG_WRITE, +}; + /* SIP_MCU_CFG child configs, MCU ID */ enum { RK_BUS_MCU, @@ -262,6 +269,7 @@ int sip_smc_secure_reg_write(u32 addr_phy, u32 val); u32 sip_smc_secure_reg_read(u32 addr_phy); struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2); struct dram_addrmap_info *sip_smc_get_dram_map(void); +int sip_smc_access_mem_os_reg(u32 func, u32 id, u32 *val); int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3); struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1); struct arm_smccc_res sip_smc_get_pvtpll_info(u32 sub_func_id, u32 arg1); @@ -360,6 +368,13 @@ static inline struct dram_addrmap_info *sip_smc_get_dram_map(void) return NULL; } +static inline int sip_smc_access_mem_os_reg(u32 func, + u32 id, + u32 *val) +{ + return 0; +} + static inline int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, From d7d83d87f94f4534e17f2cf25629469b54a591a5 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 16 Jul 2024 16:22:09 +0800 Subject: [PATCH 038/191] drm/bridge: Kconfig: DRM_SII0902X select HDMI if ROCKCHIP_MINI_KERNEL Fixes: 7c7517b5c113 ("drm: Kconfig: CONFIG_DRM select CONFIG_HDMI if !ROCKCHIP_MINI_KERNEL") Change-Id: I3146435048c242c053697e183fd4e3cf87d3592d Signed-off-by: Damon Ding --- drivers/gpu/drm/bridge/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index db0a262000ba..23c3bd7d99df 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -306,6 +306,7 @@ config DRM_SII902X select I2C_MUX select SND_SOC_HDMI_CODEC if (SND_SOC && !ROCKCHIP_MINI_KERNEL) select VIDEOMODE_HELPERS + select HDMI if ROCKCHIP_MINI_KERNEL help Silicon Image sii902x bridge chip driver. From 9ecb622e0887c89d60dfdd759ce886405f6737da Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 3 Dec 2020 18:23:37 +0800 Subject: [PATCH 039/191] clk: rockchip: add support for pvtpll clk add pvtpll_out internal clock setting. Change-Id: I9d9273d0720166043b2f11e180715646be908d8f Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/Kconfig | 6 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-pvtpll.c | 294 ++++++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/clk/rockchip/clk-pvtpll.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index e486b27cc0b0..23c1b879974c 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -180,6 +180,12 @@ config ROCKCHIP_CLK_PVTM help Say y here to enable clk pvtm. +config ROCKCHIP_CLK_PVTPLL + tristate "Rockchip Clk Pvtpll" + default y if CPU_RV1103B + help + Say y here to enable clk pvtpll. + config ROCKCHIP_DDRCLK bool diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index b181d9dde49e..a84efec6f418 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -19,6 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o obj-$(CONFIG_ROCKCHIP_CLK_OUT) += clk-out.o +obj-$(CONFIG_ROCKCHIP_CLK_PVTPLL) += clk-pvtpll.o obj-$(CONFIG_CLK_PX30) += clk-px30.o obj-$(CONFIG_CLK_RV1106) += clk-rv1106.o diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c new file mode 100644 index 000000000000..ab44eb93e6de --- /dev/null +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +#define RV1103B_PVTPLL_GCK_CFG 0x20 +#define RV1103B_PVTPLL_GCK_LEN 0x24 +#define RV1103B_GCK_START BIT(0) +#define RV1103B_GCK_EN BIT(1) +#define RV1103B_GCK_MODE BIT(5) +#define RV1103B_GCK_RING_LEN_SEL_OFFSET 0 +#define RV1103B_GCK_RING_LEN_SEL_MASK 0x1ff +#define RV1103B_GCK_RING_SEL_OFFSET 10 +#define RV1103B_GCK_RING_SEL_MASK 0x07 + +static DEFINE_MUTEX(pvtpll_reg_mutex); + +struct rockchip_clock_pvtpll; + +struct pvtpll_table { + unsigned int rate; + u32 length; + u32 length_frac; + u32 ring_sel; +}; + +struct rockchip_clock_pvtpll_info { + unsigned int table_size; + struct pvtpll_table *table; + int (*config)(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table); +}; + +struct rockchip_clock_pvtpll { + const struct rockchip_clock_pvtpll_info *info; + struct regmap *regmap; + struct clk_hw hw; + struct clk *main_clk; + struct clk *sclk; + struct clk *pvtpll_clk; + struct clk *pvtpll_out; + struct notifier_block pvtpll_nb; + unsigned long cur_rate; +}; + +#define ROCKCHIP_PVTPLL(_rate, _sel, _len) \ +{ \ + .rate = _rate##U, \ + .ring_sel = _sel, \ + .length = _len, \ +} + +static struct pvtpll_table rv1103b_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length */ + ROCKCHIP_PVTPLL(1608000000, 1, 6), + ROCKCHIP_PVTPLL(1512000000, 1, 6), + ROCKCHIP_PVTPLL(1416000000, 1, 6), + ROCKCHIP_PVTPLL(1296000000, 1, 6), + ROCKCHIP_PVTPLL(1200000000, 1, 14), + ROCKCHIP_PVTPLL(1008000000, 1, 32), + ROCKCHIP_PVTPLL(816000000, 1, 60), +}; + +static struct pvtpll_table rv1103b_npu_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(1000000000, 1, 12), + ROCKCHIP_PVTPLL(900000000, 1, 12), + ROCKCHIP_PVTPLL(800000000, 1, 16), + ROCKCHIP_PVTPLL(700000000, 1, 36), +}; + +static struct pvtpll_table +*rockchip_get_pvtpll_settings(struct rockchip_clock_pvtpll *pvtpll, + unsigned long rate) +{ + const struct rockchip_clock_pvtpll_info *info = pvtpll->info; + int i; + + for (i = 0; i < info->table_size; i++) { + if (rate == info->table[i].rate) + return &info->table[i]; + } + return NULL; +} + +static int rv1103b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table) +{ + u32 val; + int ret = 0; + + val = HIWORD_UPDATE(table->ring_sel, RV1103B_GCK_RING_SEL_MASK, + RV1103B_GCK_RING_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + + val = HIWORD_UPDATE(table->length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, + RV1103B_GCK_EN | (RV1103B_GCK_EN << 16) | + RV1103B_GCK_MODE | (RV1103B_GCK_MODE << 16)); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, + RV1103B_GCK_START | (RV1103B_GCK_START << 16)); + if (ret) + return ret; + + return ret; +} + +static int rockchip_clock_pvtpll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rockchip_clock_pvtpll *pvtpll; + struct pvtpll_table *table; + int ret = 0; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + table = rockchip_get_pvtpll_settings(pvtpll, rate); + if (!table) + return 0; + + ret = pvtpll->info->config(pvtpll, table); + + pvtpll->cur_rate = rate; + return ret; +} + +static unsigned long +rockchip_clock_pvtpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rockchip_clock_pvtpll *pvtpll; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + return pvtpll->cur_rate; +} + +static long rockchip_clock_pvtpll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct rockchip_clock_pvtpll *pvtpll; + struct pvtpll_table *table; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + table = rockchip_get_pvtpll_settings(pvtpll, rate); + if (!table) + return 0; + + return rate; +} + +static const struct clk_ops clock_pvtpll_ops = { + .recalc_rate = rockchip_clock_pvtpll_recalc_rate, + .round_rate = rockchip_clock_pvtpll_round_rate, + .set_rate = rockchip_clock_pvtpll_set_rate, +}; + +static int clock_pvtpll_regitstor(struct device *dev, + struct rockchip_clock_pvtpll *pvtpll) +{ + struct clk_init_data init = {}; + + init.parent_names = NULL; + init.num_parents = 0; + init.flags = CLK_GET_RATE_NOCACHE; + init.name = "pvtpll"; + init.ops = &clock_pvtpll_ops; + + pvtpll->hw.init = &init; + + /* optional override of the clockname */ + of_property_read_string_index(dev->of_node, "clock-output-names", + 0, &init.name); + pvtpll->pvtpll_out = devm_clk_register(dev, &pvtpll->hw); + if (IS_ERR(pvtpll->pvtpll_out)) + return PTR_ERR(pvtpll->pvtpll_out); + + return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, + pvtpll->pvtpll_out); +} + +static const struct rockchip_clock_pvtpll_info rv1103b_core_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_core_pvtpll_table), + .table = rv1103b_core_pvtpll_table, +}; + +static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_npu_pvtpll_table), + .table = rv1103b_npu_pvtpll_table, +}; + +static const struct of_device_id rockchip_clock_pvtpll_match[] = { + { + .compatible = "rockchip,rv1103b-core-pvtpll", + .data = (void *)&rv1103b_core_pvtpll_data, + }, + { + .compatible = "rockchip,rv1103b-npu-pvtpll", + .data = (void *)&rv1103b_npu_pvtpll_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, rockchip_clock_pvtpll_match); + +static int rockchip_clock_pvtpll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + struct rockchip_clock_pvtpll *pvtpll; + int error = 0; + + pvtpll = devm_kzalloc(dev, sizeof(*pvtpll), GFP_KERNEL); + if (!pvtpll) + return -ENOMEM; + + pvtpll->info = (const struct rockchip_clock_pvtpll_info *)device_get_match_data(&pdev->dev); + if (!pvtpll->info) + return -EINVAL; + + pvtpll->regmap = device_node_to_regmap(np); + if (IS_ERR(pvtpll->regmap)) + return PTR_ERR(pvtpll->regmap); + + platform_set_drvdata(pdev, pvtpll); + + error = clock_pvtpll_regitstor(&pdev->dev, pvtpll); + if (error) { + dev_err(&pdev->dev, "failed to register clock: %d\n", + error); + } + + return error; +} + +static int rockchip_clock_pvtpll_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + of_clk_del_provider(np); + + return 0; +} + +static struct platform_driver rockchip_clock_pvtpll_driver = { + .driver = { + .name = "rockchip-clcok-pvtpll", + .of_match_table = rockchip_clock_pvtpll_match, + }, + .probe = rockchip_clock_pvtpll_probe, + .remove = rockchip_clock_pvtpll_remove, +}; + +module_platform_driver(rockchip_clock_pvtpll_driver); + +MODULE_DESCRIPTION("Rockchip Clock Pvtpll Driver"); +MODULE_LICENSE("GPL"); From 3226dac8efe4a2622009394e96126c69a9b01bce Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 2 Jul 2024 16:26:26 +0800 Subject: [PATCH 040/191] clk: rockchip: clk-pvtpll: add support for rk3506 Signed-off-by: Liang Chen Change-Id: Ie5f7e94a716ce2e2483cfd8f1604b6007c4d8c0d --- drivers/clk/rockchip/Kconfig | 2 +- drivers/clk/rockchip/clk-pvtpll.c | 56 +++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 23c1b879974c..b2c4d8b99092 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -182,7 +182,7 @@ config ROCKCHIP_CLK_PVTM config ROCKCHIP_CLK_PVTPLL tristate "Rockchip Clk Pvtpll" - default y if CPU_RV1103B + default y if CPU_RV1103B || CPU_RK3506 help Say y here to enable clk pvtpll. diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c index ab44eb93e6de..3ce4fdf7ae65 100644 --- a/drivers/clk/rockchip/clk-pvtpll.c +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -28,6 +28,15 @@ #define RV1103B_GCK_RING_SEL_OFFSET 10 #define RV1103B_GCK_RING_SEL_MASK 0x07 +#define RK3506_GRF_CORE_PVTPLL_CON0_L 0x00 +#define RK3506_GRF_CORE_PVTPLL_CON0_H 0x04 +#define RK3506_OSC_RING_SEL_OFFSET 8 +#define RK3506_OSC_RING_SEL_MASK 0x03 +#define RK3506_OSC_EN BIT(1) +#define RK3506_START BIT(0) +#define RK3506_RING_LENGTH_SEL_OFFSET 0 +#define RK3506_RING_LENGTH_SEL_MASK 0x7f + static DEFINE_MUTEX(pvtpll_reg_mutex); struct rockchip_clock_pvtpll; @@ -84,6 +93,16 @@ static struct pvtpll_table rv1103b_npu_pvtpll_table[] = { ROCKCHIP_PVTPLL(700000000, 1, 36), }; +static struct pvtpll_table rk3506_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length */ + ROCKCHIP_PVTPLL(1608000000, 0, 6), + ROCKCHIP_PVTPLL(1512000000, 0, 6), + ROCKCHIP_PVTPLL(1416000000, 0, 6), + ROCKCHIP_PVTPLL(1296000000, 0, 6), + ROCKCHIP_PVTPLL(1200000000, 0, 8), + ROCKCHIP_PVTPLL(1008000000, 0, 15), +}; + static struct pvtpll_table *rockchip_get_pvtpll_settings(struct rockchip_clock_pvtpll *pvtpll, unsigned long rate) @@ -130,6 +149,33 @@ static int rv1103b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, return ret; } +static int rk3506_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table) +{ + u32 val; + int ret = 0; + + val = HIWORD_UPDATE(table->ring_sel, RK3506_OSC_RING_SEL_MASK, + RK3506_OSC_RING_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_L, val); + if (ret) + return ret; + + val = HIWORD_UPDATE(table->length, RK3506_RING_LENGTH_SEL_MASK, + RK3506_RING_LENGTH_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_H, val); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_L, + RK3506_START | (RK3506_START << 16) | + RK3506_OSC_EN | (RK3506_OSC_EN << 16)); + if (ret) + return ret; + + return ret; +} + static int rockchip_clock_pvtpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) @@ -227,6 +273,12 @@ static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { .table = rv1103b_npu_pvtpll_table, }; +static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = { + .config = rk3506_pvtpll_configs, + .table_size = ARRAY_SIZE(rk3506_core_pvtpll_table), + .table = rk3506_core_pvtpll_table, +}; + static const struct of_device_id rockchip_clock_pvtpll_match[] = { { .compatible = "rockchip,rv1103b-core-pvtpll", @@ -236,6 +288,10 @@ static const struct of_device_id rockchip_clock_pvtpll_match[] = { .compatible = "rockchip,rv1103b-npu-pvtpll", .data = (void *)&rv1103b_npu_pvtpll_data, }, + { + .compatible = "rockchip,rk3506-core-pvtpll", + .data = (void *)&rk3506_core_pvtpll_data, + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_clock_pvtpll_match); From 898db17b5569a863334f51298c8274ed30950f42 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 13 Jun 2023 10:16:00 +0800 Subject: [PATCH 041/191] dt-bindings: clock: add rk3506 cru bindings Document the device tree bindings of the rockchip rk3506 SoC clock and reset unit. Signed-off-by: Finley Xiao Change-Id: If8c0e19fab9687d488ffce1607b8555f3e7cda35 --- .../bindings/clock/rockchip,rk3506-cru.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml new file mode 100644 index 000000000000..ebd1cfb992a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3506 Family Clock and Reset Control Module + +maintainers: + - Finley Xiao + - Heiko Stuebner + +description: | + The RK3506 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_UART2 for the second UART + module. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clock and reset IDs + are defined as preprocessor macros in dt-binding headers. + +properties: + compatible: + enum: + - rockchip,rk3506-cru + - rockchip,rk3506-grf-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + + assigned-clocks: true + + assigned-clock-rates: true + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + phandle to the syscon managing the "general register files". It is used + for GRF muxes, if missing any muxes present in the GRF will not be + available. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff9a0000 { + compatible = "rockchip,rk3506-cru"; + reg = <0xff9a0000 0x20000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From 37685f392acdc5ab48ae4edd4cd6d2888bd0bb0a Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 26 May 2023 14:39:00 +0800 Subject: [PATCH 042/191] clk: rockchip: add dt-binding header for rk3506 Add the dt-bindings header for the rk3506, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3506. Signed-off-by: Finley Xiao Change-Id: Id92261ad2a6cd68d192f2159f0f7f5edffa60a2d --- .../dt-bindings/clock/rockchip,rk3506-cru.h | 489 ++++++++++++++++++ 1 file changed, 489 insertions(+) create mode 100644 include/dt-bindings/clock/rockchip,rk3506-cru.h diff --git a/include/dt-bindings/clock/rockchip,rk3506-cru.h b/include/dt-bindings/clock/rockchip,rk3506-cru.h new file mode 100644 index 000000000000..d8937544a303 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3506-cru.h @@ -0,0 +1,489 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H + +/* cru plls */ +#define PLL_GPLL 1 +#define PLL_V0PLL 2 +#define PLL_V1PLL 3 + +/* cru-clocks indices */ +#define ARMCLK 15 +#define CLK_DDR 16 +#define XIN24M_GATE 17 +#define CLK_GPLL_GATE 18 +#define CLK_V0PLL_GATE 19 +#define CLK_V1PLL_GATE 20 +#define CLK_GPLL_DIV 21 +#define CLK_GPLL_DIV_100M 22 +#define CLK_V0PLL_DIV 23 +#define CLK_V1PLL_DIV 24 +#define CLK_INT_VOICE_MATRIX0 25 +#define CLK_INT_VOICE_MATRIX1 26 +#define CLK_INT_VOICE_MATRIX2 27 +#define CLK_FRAC_UART_MATRIX0_MUX 28 +#define CLK_FRAC_UART_MATRIX1_MUX 29 +#define CLK_FRAC_VOICE_MATRIX0_MUX 30 +#define CLK_FRAC_VOICE_MATRIX1_MUX 31 +#define CLK_FRAC_COMMON_MATRIX0_MUX 32 +#define CLK_FRAC_COMMON_MATRIX1_MUX 33 +#define CLK_FRAC_COMMON_MATRIX2_MUX 34 +#define CLK_FRAC_UART_MATRIX0 35 +#define CLK_FRAC_UART_MATRIX1 36 +#define CLK_FRAC_VOICE_MATRIX0 37 +#define CLK_FRAC_VOICE_MATRIX1 38 +#define CLK_FRAC_COMMON_MATRIX0 39 +#define CLK_FRAC_COMMON_MATRIX1 40 +#define CLK_FRAC_COMMON_MATRIX2 41 +#define CLK_REF_USBPHY_TOP 42 +#define CLK_REF_DPHY_TOP 43 +#define ACLK_CORE_ROOT 44 +#define PCLK_CORE_ROOT 45 +#define PCLK_DBG 48 +#define PCLK_CORE_GRF 49 +#define PCLK_CORE_CRU 50 +#define CLK_CORE_EMA_DETECT 51 +#define CLK_REF_PVTPLL_CORE 52 +#define PCLK_GPIO1 53 +#define DBCLK_GPIO1 54 +#define ACLK_CORE_PERI_ROOT 55 +#define HCLK_CORE_PERI_ROOT 56 +#define PCLK_CORE_PERI_ROOT 57 +#define CLK_DSMC 58 +#define ACLK_DSMC 59 +#define PCLK_DSMC 60 +#define CLK_FLEXBUS_TX 61 +#define CLK_FLEXBUS_RX 62 +#define ACLK_FLEXBUS 63 +#define HCLK_FLEXBUS 64 +#define ACLK_DSMC_SLV 65 +#define HCLK_DSMC_SLV 66 +#define ACLK_BUS_ROOT 67 +#define HCLK_BUS_ROOT 68 +#define PCLK_BUS_ROOT 69 +#define ACLK_SYSRAM 70 +#define HCLK_SYSRAM 71 +#define ACLK_DMAC0 72 +#define ACLK_DMAC1 73 +#define HCLK_M0 74 +#define PCLK_BUS_GRF 75 +#define PCLK_TIMER 76 +#define CLK_TIMER0_CH0 77 +#define CLK_TIMER0_CH1 78 +#define CLK_TIMER0_CH2 79 +#define CLK_TIMER0_CH3 80 +#define CLK_TIMER0_CH4 81 +#define CLK_TIMER0_CH5 82 +#define PCLK_WDT0 83 +#define TCLK_WDT0 84 +#define PCLK_WDT1 85 +#define TCLK_WDT1 86 +#define PCLK_MAILBOX 87 +#define PCLK_INTMUX 88 +#define PCLK_SPINLOCK 89 +#define PCLK_DDRC 90 +#define HCLK_DDRPHY 91 +#define PCLK_DDRMON 92 +#define CLK_DDRMON_OSC 93 +#define PCLK_STDBY 94 +#define HCLK_USBOTG0 95 +#define HCLK_USBOTG0_PMU 96 +#define CLK_USBOTG0_ADP 97 +#define HCLK_USBOTG1 98 +#define HCLK_USBOTG1_PMU 99 +#define CLK_USBOTG1_ADP 100 +#define PCLK_USBPHY 101 +#define ACLK_DMA2DDR 102 +#define PCLK_DMA2DDR 103 +#define STCLK_M0 104 +#define CLK_DDRPHY 105 +#define CLK_DDRC_SRC 106 +#define ACLK_DDRC_0 107 +#define ACLK_DDRC_1 108 +#define CLK_DDRC 109 +#define CLK_DDRMON 110 +#define HCLK_LSPERI_ROOT 111 +#define PCLK_LSPERI_ROOT 112 +#define PCLK_UART0 113 +#define PCLK_UART1 114 +#define PCLK_UART2 115 +#define PCLK_UART3 116 +#define PCLK_UART4 117 +#define SCLK_UART0 118 +#define SCLK_UART1 119 +#define SCLK_UART2 120 +#define SCLK_UART3 121 +#define SCLK_UART4 122 +#define PCLK_I2C0 123 +#define CLK_I2C0 124 +#define PCLK_I2C1 125 +#define CLK_I2C1 126 +#define PCLK_I2C2 127 +#define CLK_I2C2 128 +#define PCLK_PWM1 129 +#define CLK_PWM1 130 +#define CLK_OSC_PWM1 131 +#define CLK_RC_PWM1 132 +#define CLK_FREQ_PWM1 133 +#define CLK_COUNTER_PWM1 134 +#define PCLK_SPI0 135 +#define CLK_SPI0 136 +#define PCLK_SPI1 137 +#define CLK_SPI1 138 +#define PCLK_GPIO2 139 +#define DBCLK_GPIO2 140 +#define PCLK_GPIO3 141 +#define DBCLK_GPIO3 142 +#define PCLK_GPIO4 143 +#define DBCLK_GPIO4 144 +#define HCLK_CAN0 145 +#define CLK_CAN0 146 +#define HCLK_CAN1 147 +#define CLK_CAN1 148 +#define HCLK_PDM 149 +#define MCLK_PDM 150 +#define CLKOUT_PDM 151 +#define MCLK_SPDIFTX 152 +#define HCLK_SPDIFTX 153 +#define HCLK_SPDIFRX 154 +#define MCLK_SPDIFRX 155 +#define MCLK_SAI0 156 +#define HCLK_SAI0 157 +#define MCLK_OUT_SAI0 158 +#define MCLK_SAI1 159 +#define HCLK_SAI1 160 +#define MCLK_OUT_SAI1 161 +#define HCLK_ASRC0 162 +#define CLK_ASRC0 163 +#define HCLK_ASRC1 164 +#define CLK_ASRC1 165 +#define PCLK_CRU 166 +#define PCLK_PMU_ROOT 167 +#define MCLK_ASRC0 168 +#define MCLK_ASRC1 169 +#define MCLK_ASRC2 170 +#define MCLK_ASRC3 171 +#define LRCK_ASRC0_SRC 172 +#define LRCK_ASRC0_DST 173 +#define LRCK_ASRC1_SRC 174 +#define LRCK_ASRC1_DST 175 +#define ACLK_HSPERI_ROOT 176 +#define HCLK_HSPERI_ROOT 177 +#define PCLK_HSPERI_ROOT 178 +#define CCLK_SRC_SDMMC 179 +#define HCLK_SDMMC 180 +#define HCLK_FSPI 181 +#define SCLK_FSPI 182 +#define PCLK_SPI2 183 +#define ACLK_MAC0 184 +#define ACLK_MAC1 185 +#define PCLK_MAC0 186 +#define PCLK_MAC1 187 +#define CLK_MAC_ROOT 188 +#define CLK_MAC0 189 +#define CLK_MAC1 190 +#define MCLK_SAI2 191 +#define HCLK_SAI2 192 +#define MCLK_OUT_SAI2 193 +#define MCLK_SAI3_SRC 194 +#define HCLK_SAI3 195 +#define MCLK_SAI3 196 +#define MCLK_OUT_SAI3 197 +#define MCLK_SAI4_SRC 198 +#define HCLK_SAI4 199 +#define MCLK_SAI4 200 +#define HCLK_DSM 201 +#define MCLK_DSM 202 +#define PCLK_AUDIO_ADC 203 +#define MCLK_AUDIO_ADC 204 +#define MCLK_AUDIO_ADC_DIV4 205 +#define PCLK_SARADC 206 +#define CLK_SARADC 207 +#define PCLK_OTPC_NS 208 +#define CLK_SBPI_OTPC_NS 209 +#define CLK_USER_OTPC_NS 210 +#define PCLK_UART5 211 +#define SCLK_UART5 212 +#define PCLK_GPIO234_IOC 213 +#define CLK_MAC_PTP_ROOT 214 +#define CLK_MAC0_PTP 215 +#define CLK_MAC1_PTP 216 +#define CLK_SPI2 217 +#define ACLK_VIO_ROOT 218 +#define HCLK_VIO_ROOT 219 +#define PCLK_VIO_ROOT 220 +#define HCLK_RGA 221 +#define ACLK_RGA 222 +#define CLK_CORE_RGA 223 +#define ACLK_VOP 224 +#define HCLK_VOP 225 +#define DCLK_VOP 226 +#define PCLK_DPHY 227 +#define PCLK_DSI_HOST 228 +#define PCLK_TSADC 229 +#define CLK_TSADC 230 +#define CLK_TSADC_TSEN 231 +#define PCLK_GPIO1_IOC 232 +#define PCLK_OTPC_S 233 +#define CLK_SBPI_OTPC_S 234 +#define CLK_USER_OTPC_S 235 +#define PCLK_OTP_MASK 236 +#define PCLK_KEYREADER 237 +#define HCLK_BOOTROM 238 +#define PCLK_DDR_SERVICE 239 +#define HCLK_CRYPTO_S 240 +#define HCLK_KEYLAD 241 +#define CLK_CORE_CRYPTO 242 +#define CLK_PKA_CRYPTO 243 +#define CLK_CORE_CRYPTO_S 244 +#define CLK_PKA_CRYPTO_S 245 +#define ACLK_CRYPTO_S 246 +#define HCLK_RNG_S 247 +#define CLK_CORE_CRYPTO_NS 248 +#define CLK_PKA_CRYPTO_NS 249 +#define ACLK_CRYPTO_NS 250 +#define HCLK_CRYPTO_NS 251 +#define HCLK_RNG 252 +#define CLK_PMU 253 +#define PCLK_PMU 254 +#define CLK_PMU_32K 255 +#define PCLK_PMU_CRU 256 +#define PCLK_PMU_GRF 257 +#define PCLK_GPIO0_IOC 258 +#define PCLK_GPIO0 259 +#define DBCLK_GPIO0 260 +#define PCLK_GPIO1_SHADOW 261 +#define DBCLK_GPIO1_SHADOW 262 +#define PCLK_PMU_HP_TIMER 263 +#define CLK_PMU_HP_TIMER 264 +#define CLK_PMU_HP_TIMER_32K 265 +#define PCLK_PWM0 266 +#define CLK_PWM0 267 +#define CLK_OSC_PWM0 268 +#define CLK_RC_PWM0 269 +#define CLK_MAC_OUT 270 +#define CLK_REF_OUT0 271 +#define CLK_REF_OUT1 272 +#define CLK_32K_FRAC 273 +#define CLK_32K_RC 274 +#define CLK_32K 275 +#define CLK_32K_PMU 276 +#define PCLK_TOUCH_KEY 277 +#define CLK_TOUCH_KEY 278 +#define CLK_REF_PHY_PLL 279 +#define CLK_REF_PHY_PMU_MUX 280 +#define CLK_WIFI_OUT 281 +#define CLK_V0PLL_REF 282 +#define CLK_V1PLL_REF 283 + +#define CLK_NR_CLKS (CLK_V1PLL_REF + 1) + +/* soft-reset indices */ + +/********Name=SOFTRST_CON00,Offset=0xA00********/ +#define SRST_NCOREPORESET0_AC 0 +#define SRST_NCOREPORESET1_AC 1 +#define SRST_NCOREPORESET2_AC 2 +#define SRST_NCORESET0_AC 4 +#define SRST_NCORESET1_AC 5 +#define SRST_NCORESET2_AC 6 +#define SRST_NL2RESET_AC 8 +#define SRST_ARESETN_CORE_BIU_AC 9 +#define SRST_HRESETN_M0_AC 10 + +/********Name=SOFTRST_CON02,Offset=0xA08********/ +#define SRST_N_DBG 42 +#define SRST_P_CORE_BIU 46 +#define SRST_PMU 47 + +/********Name=SOFTRST_CON03,Offset=0xA0C********/ +#define SRST_P_DBG 49 +#define SRST_POT_DBG 50 +#define SRST_P_CORE_GRF 52 +#define SRST_CORE_EMA_DETECT 54 +#define SRST_REF_PVTPLL_CORE 55 +#define SRST_P_GPIO1 56 +#define SRST_DB_GPIO1 57 + +/********Name=SOFTRST_CON04,Offset=0xA10********/ +#define SRST_A_CORE_PERI_BIU 67 +#define SRST_A_DSMC 69 +#define SRST_P_DSMC 70 +#define SRST_FLEXBUS 71 +#define SRST_A_FLEXBUS 73 +#define SRST_H_FLEXBUS 74 +#define SRST_A_DSMC_SLV 75 +#define SRST_H_DSMC_SLV 76 +#define SRST_DSMC_SLV 77 + +/********Name=SOFTRST_CON05,Offset=0xA14********/ +#define SRST_A_BUS_BIU 83 +#define SRST_H_BUS_BIU 84 +#define SRST_P_BUS_BIU 85 +#define SRST_A_SYSTEM 86 +#define SRST_H_SySTEM 87 +#define SRST_A_DMAC0 88 +#define SRST_A_DMAC1 89 +#define SRST_H_M0 90 +#define SRST_M0_JTAG 91 +#define SRST_H_CRYPTO 95 + +/********Name=SOFTRST_CON06,Offset=0xA18********/ +#define SRST_H_RNG 96 +#define SRST_P_BUS_GRF 97 +#define SRST_P_TIMER0 98 +#define SRST_TIMER0_CH0 99 +#define SRST_TIMER0_CH1 100 +#define SRST_TIMER0_CH2 101 +#define SRST_TIMER0_CH3 102 +#define SRST_TIMER0_CH4 103 +#define SRST_TIMER0_CH5 104 +#define SRST_P_WDT0 105 +#define SRST_T_WDT0 106 +#define SRST_P_WDT1 107 +#define SRST_T_WDT1 108 +#define SRST_P_MAILBOX 109 +#define SRST_P_INTMUX 110 +#define SRST_P_SPINLOCK 111 + +/********Name=SOFTRST_CON07,Offset=0xA1C********/ +#define SRST_P_DDRC 112 +#define SRST_H_DDRPHY 113 +#define SRST_P_DDRMON 114 +#define SRST_DDRMON_OSC 115 +#define SRST_P_DDR_LPC 116 +#define SRST_H_USBOTG0 117 +#define SRST_USBOTG0_ADP 119 +#define SRST_H_USBOTG1 120 +#define SRST_USBOTG1_ADP 122 +#define SRST_P_USBPHY 123 +#define SRST_USBPHY_POR 124 +#define SRST_USBPHY_OTG0 125 +#define SRST_USBPHY_OTG1 126 + +/********Name=SOFTRST_CON08,Offset=0xA20********/ +#define SRST_A_DMA2DDR 128 +#define SRST_P_DMA2DDR 129 + +/********Name=SOFTRST_CON09,Offset=0xA24********/ +#define SRST_USBOTG0_UTMI 144 +#define SRST_USBOTG1_UTMI 145 + +/********Name=SOFTRST_CON10,Offset=0xA28********/ +#define SRST_A_DDRC_0 160 +#define SRST_A_DDRC_1 161 +#define SRST_A_DDR_BIU 162 +#define SRST_DDRC 163 +#define SRST_DDRMON 164 + +/********Name=SOFTRST_CON11,Offset=0xA2C********/ +#define SRST_H_LSPERI_BIU 178 +#define SRST_P_UART0 180 +#define SRST_P_UART1 181 +#define SRST_P_UART2 182 +#define SRST_P_UART3 183 +#define SRST_P_UART4 184 +#define SRST_UART0 185 +#define SRST_UART1 186 +#define SRST_UART2 187 +#define SRST_UART3 188 +#define SRST_UART4 189 +#define SRST_P_I2C0 190 +#define SRST_I2C0 191 + +/********Name=SOFTRST_CON12,Offset=0xA30********/ +#define SRST_P_I2C1 192 +#define SRST_I2C1 193 +#define SRST_P_I2C2 194 +#define SRST_I2C2 195 +#define SRST_P_PWM1 196 +#define SRST_PWM1 197 +#define SRST_P_SPI0 202 +#define SRST_SPI0 203 +#define SRST_P_SPI1 204 +#define SRST_SPI1 205 +#define SRST_P_GPIO2 206 +#define SRST_DB_GPIO2 207 + +/********Name=SOFTRST_CON13,Offset=0xA34********/ +#define SRST_P_GPIO3 208 +#define SRST_DB_GPIO3 209 +#define SRST_P_GPIO4 210 +#define SRST_DB_GPIO4 211 +#define SRST_H_CAN0 212 +#define SRST_CAN0 213 +#define SRST_H_CAN1 214 +#define SRST_CAN1 215 +#define SRST_H_PDM 216 +#define SRST_M_PDM 217 +#define SRST_PDM 218 +#define SRST_SPDIFTX 219 +#define SRST_H_SPDIFTX 220 +#define SRST_H_SPDIFRX 221 +#define SRST_SPDIFRX 222 +#define SRST_M_SAI0 223 + +/********Name=SOFTRST_CON14,Offset=0xA38********/ +#define SRST_H_SAI0 224 +#define SRST_M_SAI1 226 +#define SRST_H_SAI1 227 +#define SRST_H_ASRC0 229 +#define SRST_ASRC0 230 +#define SRST_H_ASRC1 231 +#define SRST_ASRC1 232 + +/********Name=SOFTRST_CON17,Offset=0xA44********/ +#define SRST_H_HSPERI_BIU 276 +#define SRST_H_SDMMC 279 +#define SRST_H_FSPI 280 +#define SRST_S_FSPI 281 +#define SRST_P_SPI2 282 +#define SRST_A_MAC0 283 +#define SRST_A_MAC1 284 + +/********Name=SOFTRST_CON18,Offset=0xA48********/ +#define SRST_M_SAI2 290 +#define SRST_H_SAI2 291 +#define SRST_H_SAI3 294 +#define SRST_M_SAI3 295 +#define SRST_H_SAI4 298 +#define SRST_M_SAI4 299 +#define SRST_H_DSM 300 +#define SRST_M_DSM 301 +#define SRST_P_AUDIO_ADC 302 +#define SRST_M_AUDIO_ADC 303 + +/********Name=SOFTRST_CON19,Offset=0xA4C********/ +#define SRST_P_SARADC 304 +#define SRST_SARADC 305 +#define SRST_SARADC_PHY 306 +#define SRST_P_OTPC_NS 307 +#define SRST_SBPI_OTPC_NS 308 +#define SRST_USER_OTPC_NS 309 +#define SRST_P_UART5 310 +#define SRST_UART5 311 +#define SRST_P_GPIO234_IOC 312 + +/********Name=SOFTRST_CON21,Offset=0xA54********/ +#define SRST_A_VIO_BIU 339 +#define SRST_H_VIO_BIU 340 +#define SRST_H_RGA 342 +#define SRST_A_RGA 343 +#define SRST_CORE_RGA 344 +#define SRST_A_VOP 345 +#define SRST_H_VOP 346 +#define SRST_VOP 347 +#define SRST_P_DPHY 348 +#define SRST_P_DSI_HOST 349 +#define SRST_P_TSADC 350 +#define SRST_TSADC 351 + +/********Name=SOFTRST_CON22,Offset=0xA58********/ +#define SRST_P_GPIO1_IOC 353 + +#endif From b78cc5271cdf78fe09ad304af559da08561cfcde Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 26 May 2023 14:41:00 +0800 Subject: [PATCH 043/191] clk: rockchip: Add clock controller for the RK3506 Add the clock tree definition for the new RK3506 SoC. Signed-off-by: Finley Xiao Change-Id: Ib5e47bd03620cb7540fa827e29425c243f633a82 --- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3506.c | 895 ++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 12 + 4 files changed, 915 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3506.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index b2c4d8b99092..2bbbc278b899 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -107,6 +107,13 @@ config CLK_RK3399 help Build the driver for RK3399 Clock Driver. +config CLK_RK3506 + tristate "Rockchip RK3506 clock controller support" + depends on CPU_RK3506 || COMPILE_TEST + default y + help + Build the driver for RK3506 Clock Driver. + config CLK_RK3528 tristate "Rockchip RK3528 clock controller support" depends on CPU_RK3528 || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index a84efec6f418..b522ae034b38 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o +obj-$(CONFIG_CLK_RK3506) += clk-rk3506.o obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c new file mode 100644 index 000000000000..0683bc7ea285 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3506.c @@ -0,0 +1,895 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clk.h" + +#define RK3506_GRF_SOC_STATUS 0x100 + +#define PVTPLL_SRC_SEL_PVTPLL (BIT(7) | BIT(23)) + +enum rk3506_plls { + gpll, v0pll, v1pll, +}; + +/* + * [FRAC PLL]: GPLL, V0PLL, V1PLL + * - VCO Frequency: 950MHz to 3800MHZ + * - Output Frequency: 19MHz to 3800MHZ + * - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode) + * - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode) + * - post1div: 1 to 7 + * - post2div: 1 to 7 + */ +static struct rockchip_pll_rate_table rk3506_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), + RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), + RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0), + { /* sentinel */ }, +}; + +#define RK3506_DIV_ACLK_CORE_MASK 0xf +#define RK3506_DIV_ACLK_CORE_SHIFT 9 +#define RK3506_DIV_PCLK_CORE_MASK 0xf +#define RK3506_DIV_PCLK_CORE_SHIFT 0 + +#define RK3506_CLKSEL15(_aclk_core_div) \ +{ \ + .reg = RK3506_CLKSEL_CON(15), \ + .val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \ + RK3506_DIV_ACLK_CORE_SHIFT), \ +} + +#define RK3506_CLKSEL16(_pclk_core_div) \ +{ \ + .reg = RK3506_CLKSEL_CON(16), \ + .val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \ + RK3506_DIV_PCLK_CORE_SHIFT), \ +} + +/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */ +#define RK3506_CPUCLK_RATE(_prate, _aclk_core_div, _pclk_core_div) \ +{ \ + .prate = _prate, \ + .divs = { \ + RK3506_CLKSEL15(_aclk_core_div), \ + RK3506_CLKSEL16(_pclk_core_div), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = { + RK3506_CPUCLK_RATE(1608000000, 3, 12), + RK3506_CPUCLK_RATE(1512000000, 3, 12), + RK3506_CPUCLK_RATE(1416000000, 2, 11), + RK3506_CPUCLK_RATE(1296000000, 2, 10), + RK3506_CPUCLK_RATE(1200000000, 2, 9), + RK3506_CPUCLK_RATE(1179648000, 2, 9), + RK3506_CPUCLK_RATE(1008000000, 1, 7), + RK3506_CPUCLK_RATE(903168000, 1, 7), + RK3506_CPUCLK_RATE(800000000, 1, 6), + RK3506_CPUCLK_RATE(589824000, 1, 4), + RK3506_CPUCLK_RATE(400000000, 1, 3), + RK3506_CPUCLK_RATE(200000000, 1, 1), +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" }; +PNAME(gpll_v0pll_v1pll_g_parents_p) = { "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" }; +PNAME(gpll_v0pll_v1pll_div_parents_p) = { "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" }; +PNAME(xin24m_gpll_v0pll_v1pll_g_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" }; +PNAME(xin24m_g_gpll_v0pll_v1pll_g_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" }; +PNAME(xin24m_g_gpll_v0pll_v1pll_div_parents_p) = { "xin24m_gate", "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" }; +PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" }; +PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" }; +PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai0_mclk_in", "sai0_sclk_in" }; +PNAME(clk_timer1_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai1_mclk_in", "sai1_sclk_in" }; +PNAME(clk_timer2_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai2_mclk_in", "sai2_sclk_in" }; +PNAME(clk_timer3_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai3_mclk_in", "sai3_sclk_in" }; +PNAME(clk_timer4_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc0" }; +PNAME(clk_timer5_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc1" }; +PNAME(sclk_uart_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_frac_uart_matrix0", "clk_frac_uart_matrix1", + "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" }; +PNAME(clk_mac_ptp_root_parents_p) = { "gpll", "v0pll", "v1pll" }; +PNAME(clk_pwm_parents_p) = { "clk_rc", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai0_sclk_in", "sai1_sclk_in", + "sai2_sclk_in", "sai3_sclk_in", "mclk_asrc0", "mclk_asrc1" }; +PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voice_matrix1", + "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" }; +PNAME(clk_pdm_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2", + "clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1", + "clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "clk_gpll_div" }; +PNAME(mclk_sai_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2", + "clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1", + "clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in" }; +PNAME(lrck_asrc_parents_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", "mclk_spdiftx", "clk_spdifrx_to_asrc", "clkout_pdm", + "sai0_fs", "sai1_fs", "sai2_fs", "sai3_fs", "sai4_fs" }; +PNAME(cclk_src_sdmmc_parents_p) = { "xin24m_gate", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" }; +PNAME(dclk_vop_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voice_matrix1", + "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" }; +PNAME(dbclk_gpio0_parents_p) = { "xin24m", "clk_rc", "clk_32k_pmu" }; +PNAME(clk_pmu_hp_timer_parents_p) = { "xin24m", "gpll_div_100m", "clk_core_pvtpll" }; +PNAME(clk_ref_out_parents_p) = { "xin24m", "gpll", "v0pll", "v1pll" }; +PNAME(clk_32k_frac_parents_p) = { "xin24m", "v0pll", "v1pll", "clk_rc" }; +PNAME(clk_32k_parents_p) = { "xin32k", "clk_32k_rc", "clk_32k_frac" }; +PNAME(clk_ref_phy_pmu_mux_parents_p) = { "xin24m", "clk_ref_phy_pll" }; +PNAME(clk_vpll_ref_parents_p) = { "xin24m", "clk_pll_ref_io" }; +PNAME(mux_armclk_p) = { "armclk_pll", "clk_core_pvtpll" }; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = { + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + CLK_IS_CRITICAL, RK3506_PLL_CON(0), + RK3506_MODE_CON, 0, 2, 0, rk3506_pll_rates), + [v0pll] = PLL(pll_rk3328, PLL_V0PLL, "v0pll", mux_pll_p, + CLK_IS_CRITICAL, RK3506_PLL_CON(8), + RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates), + [v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p, + CLK_IS_CRITICAL, RK3506_PLL_CON(16), + RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates), +}; + +static struct rockchip_clk_branch rk3506_armclk __initdata = + MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + RK3506_CLKSEL_CON(15), 8, 1, MFLAGS); + +static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* top */ + GATE(XIN24M_GATE, "xin24m_gate", "xin24m", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(0), 1, GFLAGS), + GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(0), 2, GFLAGS), + GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV, "clk_gpll_div", "clk_gpll_gate", CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(0), 6, 4, DFLAGS, + RK3506_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV_100M, "clk_gpll_div_100m", "clk_gpll_div", 0, + RK3506_CLKSEL_CON(0), 10, 4, DFLAGS, + RK3506_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_V0PLL_DIV, "clk_v0pll_div", "clk_v0pll_gate", CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(1), 0, 4, DFLAGS, + RK3506_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(1), 4, 4, DFLAGS, + RK3506_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX0, "clk_int_voice_matrix0", "clk_v0pll_gate", 0, + RK3506_CLKSEL_CON(1), 8, 5, DFLAGS, + RK3506_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX1, "clk_int_voice_matrix1", "clk_v1pll_gate", 0, + RK3506_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3506_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX2, "clk_int_voice_matrix2", "clk_v0pll_gate", 0, + RK3506_CLKSEL_CON(2), 5, 5, DFLAGS, + RK3506_CLKGATE_CON(0), 11, GFLAGS), + MUX(CLK_FRAC_UART_MATRIX0_MUX, "clk_frac_uart_matrix0_mux", clk_frac_uart_matrix0_mux_parents_p, 0, + RK3506_CLKSEL_CON(3), 9, 2, MFLAGS), + MUX(CLK_FRAC_UART_MATRIX1_MUX, "clk_frac_uart_matrix1_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(3), 11, 2, MFLAGS), + MUX(CLK_FRAC_VOICE_MATRIX0_MUX, "clk_frac_voice_matrix0_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(3), 13, 2, MFLAGS), + MUX(CLK_FRAC_VOICE_MATRIX1_MUX, "clk_frac_voice_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(4), 0, 2, MFLAGS), + MUX(CLK_FRAC_COMMON_MATRIX0_MUX, "clk_frac_common_matrix0_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(4), 2, 2, MFLAGS), + MUX(CLK_FRAC_COMMON_MATRIX1_MUX, "clk_frac_common_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(4), 4, 2, MFLAGS), + MUX(CLK_FRAC_COMMON_MATRIX2_MUX, "clk_frac_common_matrix2_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(4), 6, 2, MFLAGS), + COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX0, "clk_frac_uart_matrix0", "clk_frac_uart_matrix0_mux", 0, + RK3506_CLKSEL_CON(5), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(0), 13, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX1, "clk_frac_uart_matrix1", "clk_frac_uart_matrix1_mux", 0, + RK3506_CLKSEL_CON(6), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(0), 14, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX0, "clk_frac_voice_matrix0", "clk_frac_voice_matrix0_mux", 0, + RK3506_CLKSEL_CON(7), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX1, "clk_frac_voice_matrix1", "clk_frac_voice_matrix1_mux", 0, + RK3506_CLKSEL_CON(9), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX0, "clk_frac_common_matrix0", "clk_frac_common_matrix0_mux", 0, + RK3506_CLKSEL_CON(11), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX1, "clk_frac_common_matrix1", "clk_frac_common_matrix1_mux", 0, + RK3506_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX2, "clk_frac_common_matrix2", "clk_frac_common_matrix2_mux", 0, + RK3506_CLKSEL_CON(13), CLK_FRAC_DIVIDER_NO_LIMIT, + RK3506_CLKGATE_CON(1), 3, GFLAGS), + GATE(CLK_REF_USBPHY_TOP, "clk_ref_usbphy_top", "xin24m", 0, + RK3506_CLKGATE_CON(1), 4, GFLAGS), + GATE(CLK_REF_DPHY_TOP, "clk_ref_dphy_top", "xin24m", 0, + RK3506_CLKGATE_CON(1), 5, GFLAGS), + + /* core */ + COMPOSITE_NOGATE(0, "armclk_pll", gpll_v0pll_v1pll_parents_p, CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(ACLK_CORE_ROOT, "aclk_core_root", "armclk", CLK_IGNORE_UNUSED, + RK3506_CLKSEL_CON(15), 9, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3506_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_NOMUX(PCLK_CORE_ROOT, "pclk_core_root", "armclk", CLK_IGNORE_UNUSED, + RK3506_CLKSEL_CON(16), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3506_CLKGATE_CON(2), 12, GFLAGS), + GATE(PCLK_DBG, "pclk_dbg", "pclk_core_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(3), 1, GFLAGS), + GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_core_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(3), 4, GFLAGS), + GATE(PCLK_CORE_CRU, "pclk_core_cru", "pclk_core_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(3), 5, GFLAGS), + GATE(CLK_CORE_EMA_DETECT, "clk_core_ema_detect", "xin24m_gate", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(3), 6, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "aclk_core_root", 0, + RK3506_CLKGATE_CON(3), 8, GFLAGS), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m_gate", 0, + RK3506_CLKGATE_CON(3), 9, GFLAGS), + + /* core peri */ + COMPOSITE(ACLK_CORE_PERI_ROOT, "aclk_core_peri_root", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(18), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(4), 0, GFLAGS), + GATE(HCLK_CORE_PERI_ROOT, "hclk_core_peri_root", "aclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 1, GFLAGS), + GATE(PCLK_CORE_PERI_ROOT, "pclk_core_peri_root", "aclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE(CLK_DSMC, "clk_dsmc", xin24m_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(18), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(4), 4, GFLAGS), + GATE(ACLK_DSMC, "aclk_dsmc", "aclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 5, GFLAGS), + GATE(PCLK_DSMC, "pclk_dsmc", "pclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 6, GFLAGS), + COMPOSITE(CLK_FLEXBUS_TX, "clk_flexbus_tx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(19), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(4), 7, GFLAGS), + COMPOSITE(CLK_FLEXBUS_RX, "clk_flexbus_rx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(19), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(4), 8, GFLAGS), + GATE(ACLK_FLEXBUS, "aclk_flexbus", "aclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 9, GFLAGS), + GATE(HCLK_FLEXBUS, "hclk_flexbus", "hclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 10, GFLAGS), + GATE(ACLK_DSMC_SLV, "aclk_dsmc_slv", "aclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 11, GFLAGS), + GATE(HCLK_DSMC_SLV, "hclk_dsmc_slv", "hclk_core_peri_root", 0, + RK3506_CLKGATE_CON(4), 12, GFLAGS), + + /* bus */ + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(21), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE(HCLK_BUS_ROOT, "hclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(21), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(5), 1, GFLAGS), + COMPOSITE(PCLK_BUS_ROOT, "pclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(5), 2, GFLAGS), + GATE(ACLK_SYSRAM, "aclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(5), 6, GFLAGS), + GATE(HCLK_SYSRAM, "hclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(5), 7, GFLAGS), + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, + RK3506_CLKGATE_CON(5), 8, GFLAGS), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, + RK3506_CLKGATE_CON(5), 9, GFLAGS), + GATE(HCLK_M0, "hclk_m0", "aclk_bus_root", 0, + RK3506_CLKGATE_CON(5), 10, GFLAGS), + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_bus_root", 0, + RK3506_CLKGATE_CON(5), 14, GFLAGS), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(5), 15, GFLAGS), + GATE(HCLK_RNG, "hclk_rng", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 0, GFLAGS), + GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(6), 1, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 2, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH0, "clk_timer0_ch0", clk_timer0_parents_p, 0, + RK3506_CLKSEL_CON(22), 7, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 3, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH1, "clk_timer0_ch1", clk_timer1_parents_p, 0, + RK3506_CLKSEL_CON(22), 10, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 4, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH2, "clk_timer0_ch2", clk_timer2_parents_p, 0, + RK3506_CLKSEL_CON(22), 13, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 5, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH3, "clk_timer0_ch3", clk_timer3_parents_p, 0, + RK3506_CLKSEL_CON(23), 0, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 6, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH4, "clk_timer0_ch4", clk_timer4_parents_p, 0, + RK3506_CLKSEL_CON(23), 3, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 7, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_CH5, "clk_timer0_ch5", clk_timer5_parents_p, 0, + RK3506_CLKSEL_CON(23), 6, 3, MFLAGS, + RK3506_CLKGATE_CON(6), 8, GFLAGS), + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 9, GFLAGS), + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m_gate", 0, + RK3506_CLKGATE_CON(6), 10, GFLAGS), + GATE(PCLK_WDT1, "pclk_wdt1", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 11, GFLAGS), + GATE(TCLK_WDT1, "tclk_wdt1", "xin24m_gate", 0, + RK3506_CLKGATE_CON(6), 12, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 13, GFLAGS), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 14, GFLAGS), + GATE(PCLK_SPINLOCK, "pclk_spinlock", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(6), 15, GFLAGS), + GATE(PCLK_DDRC, "pclk_ddrc", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(7), 0, GFLAGS), + GATE(HCLK_DDRPHY, "hclk_ddrphy", "hclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(7), 1, GFLAGS), + GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(7), 2, GFLAGS), + GATE(CLK_DDRMON_OSC, "clk_ddrmon_osc", "xin24m_gate", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_STDBY, "pclk_stdby", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(7), 4, GFLAGS), + GATE(HCLK_USBOTG0, "hclk_usbotg0", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(7), 5, GFLAGS), + GATE(HCLK_USBOTG0_PMU, "hclk_usbotg0_pmu", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(7), 6, GFLAGS), + GATE(CLK_USBOTG0_ADP, "clk_usbotg0_adp", "clk_32k", 0, + RK3506_CLKGATE_CON(7), 7, GFLAGS), + GATE(HCLK_USBOTG1, "hclk_usbotg1", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(7), 8, GFLAGS), + GATE(HCLK_USBOTG1_PMU, "hclk_usbotg1_pmu", "hclk_bus_root", 0, + RK3506_CLKGATE_CON(7), 9, GFLAGS), + GATE(CLK_USBOTG1_ADP, "clk_usbotg1_adp", "clk_32k", 0, + RK3506_CLKGATE_CON(7), 10, GFLAGS), + GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_bus_root", 0, + RK3506_CLKGATE_CON(7), 11, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(8), 0, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_NOMUX(STCLK_M0, "stclk_m0", "xin24m_gate", 0, + RK3506_CLKSEL_CON(23), 9, 6, DFLAGS, + RK3506_CLKGATE_CON(8), 2, GFLAGS), + COMPOSITE(CLK_DDRPHY, "clk_ddrphy", gpll_v0pll_v1pll_parents_p, CLK_IGNORE_UNUSED, + RK3506_PMU_CLKSEL_CON(4), 4, 2, MFLAGS, 0, 4, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 10, GFLAGS), + FACTOR(CLK_DDRC_SRC, "clk_ddrc_src", "clk_ddrphy", 0, 1, 4), + GATE(ACLK_DDRC_0, "aclk_ddrc_0", "clk_ddrc_src", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(10), 0, GFLAGS), + GATE(ACLK_DDRC_1, "aclk_ddrc_1", "clk_ddrc_src", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(10), 1, GFLAGS), + GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(10), 3, GFLAGS), + GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(10), 4, GFLAGS), + + /* ls peri */ + COMPOSITE(HCLK_LSPERI_ROOT, "hclk_lsperi_root", gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(29), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 0, GFLAGS), + GATE(PCLK_LSPERI_ROOT, "pclk_lsperi_root", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 1, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 4, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 5, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 6, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 7, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 8, GFLAGS), + COMPOSITE(SCLK_UART0, "sclk_uart0", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(29), 12, 3, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 9, GFLAGS), + COMPOSITE(SCLK_UART1, "sclk_uart1", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(30), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(SCLK_UART2, "sclk_uart2", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(30), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 11, GFLAGS), + COMPOSITE(SCLK_UART3, "sclk_uart3", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 12, GFLAGS), + COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3506_CLKGATE_CON(11), 13, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(11), 14, GFLAGS), + COMPOSITE(CLK_I2C0, "clk_i2c0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(32), 4, 2, MFLAGS, 0, 4, DFLAGS, + RK3506_CLKGATE_CON(11), 15, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 0, GFLAGS), + COMPOSITE(CLK_I2C1, "clk_i2c1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(32), 10, 2, MFLAGS, 6, 4, DFLAGS, + RK3506_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 2, GFLAGS), + COMPOSITE(CLK_I2C2, "clk_i2c2", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(33), 4, 2, MFLAGS, 0, 4, DFLAGS, + RK3506_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 4, GFLAGS), + COMPOSITE(CLK_PWM1, "clk_pwm1", gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(33), 10, 2, MFLAGS, 6, 4, DFLAGS, + RK3506_CLKGATE_CON(12), 5, GFLAGS), + GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, + RK3506_CLKGATE_CON(12), 6, GFLAGS), + GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_rc", 0, + RK3506_CLKGATE_CON(12), 7, GFLAGS), + COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_pwm_parents_p, 0, + RK3506_CLKSEL_CON(33), 12, 4, MFLAGS, + RK3506_CLKGATE_CON(12), 8, GFLAGS), + COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_pwm_parents_p, 0, + RK3506_CLKSEL_CON(34), 0, 4, MFLAGS, + RK3506_CLKGATE_CON(12), 9, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 10, GFLAGS), + COMPOSITE(CLK_SPI0, "clk_spi0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(34), 8, 2, MFLAGS, 4, 4, DFLAGS, + RK3506_CLKGATE_CON(12), 11, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 12, GFLAGS), + COMPOSITE(CLK_SPI1, "clk_spi1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(34), 14, 2, MFLAGS, 10, 4, DFLAGS, + RK3506_CLKGATE_CON(12), 13, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(12), 14, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", xin24m_400k_32k_parents_p, 0, + RK3506_CLKSEL_CON(35), 0, 2, MFLAGS, + RK3506_CLKGATE_CON(12), 15, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", xin24m_400k_32k_parents_p, 0, + RK3506_CLKSEL_CON(35), 2, 2, MFLAGS, + RK3506_CLKGATE_CON(13), 1, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 2, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", xin24m_400k_32k_parents_p, 0, + RK3506_CLKSEL_CON(35), 4, 2, MFLAGS, + RK3506_CLKGATE_CON(13), 3, GFLAGS), + GATE(HCLK_CAN0, "hclk_can0", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 4, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", clk_can_parents_p, 0, + RK3506_CLKSEL_CON(35), 11, 3, MFLAGS, 6, 5, DFLAGS, + RK3506_CLKGATE_CON(13), 5, GFLAGS), + GATE(HCLK_CAN1, "hclk_can1", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 6, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", clk_can_parents_p, 0, + RK3506_CLKSEL_CON(36), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(13), 7, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 8, GFLAGS), + COMPOSITE(MCLK_PDM, "mclk_pdm", clk_pdm_parents_p, 0, + RK3506_CLKSEL_CON(37), 5, 4, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(13), 9, GFLAGS), + COMPOSITE(CLKOUT_PDM, "clkout_pdm", clk_pdm_parents_p, 0, + RK3506_CLKSEL_CON(38), 10, 4, MFLAGS, 0, 10, DFLAGS, + RK3506_CLKGATE_CON(13), 10, GFLAGS), + COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(39), 5, 4, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(13), 11, GFLAGS), + GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 12, GFLAGS), + GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(13), 13, GFLAGS), + COMPOSITE(MCLK_SPDIFRX, "mclk_spdifrx", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(39), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3506_CLKGATE_CON(13), 14, GFLAGS), + COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(13), 15, GFLAGS), + GATE(HCLK_SAI0, "hclk_sai0", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(14), 0, GFLAGS), + GATE(MCLK_OUT_SAI0, "mclk_out_sai0", "mclk_sai0", 0, + RK3506_CLKGATE_CON(14), 1, GFLAGS), + COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(14), 2, GFLAGS), + GATE(HCLK_SAI1, "hclk_sai1", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(14), 3, GFLAGS), + GATE(MCLK_OUT_SAI1, "mclk_out_sai1", "mclk_sai1", 0, + RK3506_CLKGATE_CON(14), 4, GFLAGS), + GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(14), 5, GFLAGS), + COMPOSITE(CLK_ASRC0, "clk_asrc0", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(42), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(14), 6, GFLAGS), + GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_lsperi_root", 0, + RK3506_CLKGATE_CON(14), 7, GFLAGS), + COMPOSITE(CLK_ASRC1, "clk_asrc1", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(42), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(14), 8, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_lsperi_root", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(14), 9, GFLAGS), + GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "pclk_lsperi_root", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(14), 10, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(46), 0, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(46), 4, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 1, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(46), 8, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 2, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(46), 12, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 3, GFLAGS), + COMPOSITE_NODIV(LRCK_ASRC0_SRC, "lrck_asrc0_src", lrck_asrc_parents_p, 0, + RK3506_CLKSEL_CON(47), 0, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 4, GFLAGS), + COMPOSITE_NODIV(LRCK_ASRC0_DST, "lrck_asrc0_dst", lrck_asrc_parents_p, 0, + RK3506_CLKSEL_CON(47), 4, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 5, GFLAGS), + COMPOSITE_NODIV(LRCK_ASRC1_SRC, "lrck_asrc1_src", lrck_asrc_parents_p, 0, + RK3506_CLKSEL_CON(47), 8, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 6, GFLAGS), + COMPOSITE_NODIV(LRCK_ASRC1_DST, "lrck_asrc1_dst", lrck_asrc_parents_p, 0, + RK3506_CLKSEL_CON(47), 12, 4, MFLAGS, + RK3506_CLKGATE_CON(16), 7, GFLAGS), + + /* hs peri */ + COMPOSITE(ACLK_HSPERI_ROOT, "aclk_hsperi_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL, + RK3506_CLKSEL_CON(49), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(17), 0, GFLAGS), + GATE(HCLK_HSPERI_ROOT, "hclk_hsperi_root", "aclk_hsperi_root", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(17), 1, GFLAGS), + GATE(PCLK_HSPERI_ROOT, "pclk_hsperi_root", "hclk_hsperi_root", CLK_IS_CRITICAL, + RK3506_CLKGATE_CON(17), 2, GFLAGS), + COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", cclk_src_sdmmc_parents_p, 0, + RK3506_CLKSEL_CON(49), 13, 2, MFLAGS, 7, 6, DFLAGS, + RK3506_CLKGATE_CON(17), 6, GFLAGS), + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 7, GFLAGS), + GATE(HCLK_FSPI, "hclk_fspi", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 8, GFLAGS), + COMPOSITE(SCLK_FSPI, "sclk_fspi", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(50), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(17), 9, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 10, GFLAGS), + GATE(ACLK_MAC0, "aclk_mac0", "aclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 11, GFLAGS), + GATE(ACLK_MAC1, "aclk_mac1", "aclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 12, GFLAGS), + GATE(PCLK_MAC0, "pclk_mac0", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 13, GFLAGS), + GATE(PCLK_MAC1, "pclk_mac1", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(17), 14, GFLAGS), + COMPOSITE_NOMUX(CLK_MAC_ROOT, "clk_mac_root", "gpll", 0, + RK3506_CLKSEL_CON(50), 7, 5, DFLAGS, + RK3506_CLKGATE_CON(17), 15, GFLAGS), + GATE(CLK_MAC0, "clk_mac0", "clk_mac_root", 0, + RK3506_CLKGATE_CON(18), 0, GFLAGS), + GATE(CLK_MAC1, "clk_mac1", "clk_mac_root", 0, + RK3506_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(18), 2, GFLAGS), + GATE(HCLK_SAI2, "hclk_sai2", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(18), 3, GFLAGS), + GATE(MCLK_OUT_SAI2, "mclk_out_sai2", "mclk_sai2", 0, + RK3506_CLKGATE_CON(18), 4, GFLAGS), + COMPOSITE(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(18), 5, GFLAGS), + GATE(HCLK_SAI3, "hclk_sai3", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(18), 6, GFLAGS), + GATE(MCLK_SAI3, "mclk_sai3", "mclk_sai3_src", 0, + RK3506_CLKGATE_CON(18), 7, GFLAGS), + GATE(MCLK_OUT_SAI3, "mclk_out_sai3", "mclk_sai3_src", 0, + RK3506_CLKGATE_CON(18), 8, GFLAGS), + COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_asrc_parents_p, 0, + RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(18), 9, GFLAGS), + GATE(HCLK_SAI4, "hclk_sai4", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(18), 10, GFLAGS), + GATE(MCLK_SAI4, "mclk_sai4", "mclk_sai4_src", 0, + RK3506_CLKGATE_CON(18), 11, GFLAGS), + GATE(HCLK_DSM, "hclk_dsm", "hclk_hsperi_root", 0, + RK3506_CLKGATE_CON(18), 12, GFLAGS), + GATE(MCLK_DSM, "mclk_dsm", "mclk_sai3_src", 0, + RK3506_CLKGATE_CON(18), 13, GFLAGS), + GATE(PCLK_AUDIO_ADC, "pclk_audio_adc", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(18), 14, GFLAGS), + GATE(MCLK_AUDIO_ADC, "mclk_audio_adc", "mclk_sai4_src", 0, + RK3506_CLKGATE_CON(18), 15, GFLAGS), + FACTOR(MCLK_AUDIO_ADC_DIV4, "mclk_audio_adc_div4", "mclk_audio_adc", 0, 1, 4), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(19), 0, GFLAGS), + COMPOSITE(CLK_SARADC, "clk_saradc", xin24m_400k_32k_parents_p, 0, + RK3506_CLKSEL_CON(54), 4, 2, MFLAGS, 0, 4, DFLAGS, + RK3506_CLKGATE_CON(19), 1, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(19), 3, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m_gate", 0, + RK3506_CLKGATE_CON(19), 4, GFLAGS), + FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2), + GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0, + RK3506_CLKGATE_CON(19), 6, GFLAGS), + COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0, + RK3506_CLKSEL_CON(54), 11, 3, MFLAGS, 6, 5, DFLAGS, + RK3506_CLKGATE_CON(19), 7, GFLAGS), + GATE(PCLK_GPIO234_IOC, "pclk_gpio234_ioc", "pclk_hsperi_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(19), 8, GFLAGS), + COMPOSITE(CLK_MAC_PTP_ROOT, "clk_mac_ptp_root", clk_mac_ptp_root_parents_p, 0, + RK3506_CLKSEL_CON(55), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(19), 9, GFLAGS), + GATE(CLK_MAC0_PTP, "clk_mac0_ptp", "clk_mac_ptp_root", 0, + RK3506_CLKGATE_CON(19), 10, GFLAGS), + GATE(CLK_MAC1_PTP, "clk_mac1_ptp", "clk_mac_ptp_root", 0, + RK3506_CLKGATE_CON(19), 11, GFLAGS), + COMPOSITE(ACLK_VIO_ROOT, "aclk_vio_root", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(58), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(21), 0, GFLAGS), + COMPOSITE(HCLK_VIO_ROOT, "hclk_vio_root", gpll_v0pll_v1pll_div_parents_p, 0, + RK3506_CLKSEL_CON(58), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3506_CLKGATE_CON(21), 1, GFLAGS), + GATE(PCLK_VIO_ROOT, "pclk_vio_root", "hclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 2, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 6, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 7, GFLAGS), + COMPOSITE(CLK_CORE_RGA, "clk_core_rga", gpll_v0pll_v1pll_g_parents_p, 0, + RK3506_CLKSEL_CON(59), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3506_CLKGATE_CON(21), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 9, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 10, GFLAGS), + COMPOSITE(DCLK_VOP, "dclk_vop", dclk_vop_parents_p, 0, + RK3506_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3506_CLKGATE_CON(21), 11, GFLAGS), + GATE(PCLK_DPHY, "pclk_dphy", "pclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 12, GFLAGS), + GATE(PCLK_DSI_HOST, "pclk_dsi_host", "pclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 13, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vio_root", 0, + RK3506_CLKGATE_CON(21), 14, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m_gate", 0, + RK3506_CLKSEL_CON(61), 0, 8, DFLAGS, + RK3506_CLKGATE_CON(21), 15, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m_gate", 0, + RK3506_CLKSEL_CON(61), 8, 3, DFLAGS, + RK3506_CLKGATE_CON(22), 0, GFLAGS), + GATE(PCLK_GPIO1_IOC, "pclk_gpio1_ioc", "pclk_vio_root", CLK_IGNORE_UNUSED, + RK3506_CLKGATE_CON(22), 1, GFLAGS), + + /* pmu */ + GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 1, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_GPIO0_IOC, "pclk_gpio0_ioc", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, + RK3506_PMU_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", dbclk_gpio0_parents_p, 0, + RK3506_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, + RK3506_PMU_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_GPIO1_SHADOW, "pclk_gpio1_shadow", "pclk_pmu_root", 0, + RK3506_PMU_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO1_SHADOW, "dbclk_gpio1_shadow", dbclk_gpio0_parents_p, 0, + RK3506_PMU_CLKSEL_CON(0), 2, 2, MFLAGS, + RK3506_PMU_CLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 12, GFLAGS), + MUX(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", clk_pmu_hp_timer_parents_p, CLK_IGNORE_UNUSED, + RK3506_PMU_CLKSEL_CON(0), 4, 2, MFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu_root", 0, + RK3506_PMU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NOMUX(CLK_PWM0, "clk_pwm0", "clk_gpll_div_100m", 0, + RK3506_PMU_CLKSEL_CON(0), 6, 4, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 0, GFLAGS), + GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0, + RK3506_PMU_CLKGATE_CON(1), 1, GFLAGS), + GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_rc", 0, + RK3506_PMU_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_MAC_OUT, "clk_mac_out", "gpll", 0, + RK3506_PMU_CLKSEL_CON(0), 10, 6, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE(CLK_REF_OUT0, "clk_ref_out0", clk_ref_out_parents_p, 0, + RK3506_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 4, GFLAGS), + COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0, + RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS), + COMPOSITE_DIV_OFFSET(CLK_32K_FRAC, "clk_32k_frac", clk_32k_frac_parents_p, CLK_IGNORE_UNUSED, + RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS, + RK3506_PMU_CLKSEL_CON(2), 0, 32, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL, + RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE_NODIV(CLK_32K, "clk_32k", clk_32k_parents_p, CLK_IS_CRITICAL, + RK3506_PMU_CLKSEL_CON(3), 7, 2, MFLAGS, + RK3506_PMU_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NODIV(CLK_32K_PMU, "clk_32k_pmu", clk_32k_parents_p, CLK_IS_CRITICAL, + RK3506_PMU_CLKSEL_CON(3), 9, 2, MFLAGS, + RK3506_PMU_CLKGATE_CON(1), 9, GFLAGS), + GATE(CLK_PMU_32K, "clk_pmu_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_PMU_HP_TIMER_32K, "clk_pmu_hp_timer_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_TOUCH_KEY, "pclk_touch_key", "pclk_pmu_root", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(CLK_TOUCH_KEY, "clk_touch_key", "xin24m", CLK_IGNORE_UNUSED, + RK3506_PMU_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE(CLK_REF_PHY_PLL, "clk_ref_phy_pll", gpll_v0pll_v1pll_parents_p, 0, + RK3506_PMU_CLKSEL_CON(4), 13, 2, MFLAGS, 6, 7, DFLAGS, + RK3506_PMU_CLKGATE_CON(1), 14, GFLAGS), + MUX(CLK_REF_PHY_PMU_MUX, "clk_ref_phy_pmu_mux", clk_ref_phy_pmu_mux_parents_p, 0, + RK3506_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), + GATE(CLK_WIFI_OUT, "clk_wifi_out", "xin24m", 0, + RK3506_PMU_CLKGATE_CON(2), 0, GFLAGS), + MUX(CLK_V0PLL_REF, "clk_v0pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED, + RK3506_PMU_CLKSEL_CON(6), 0, 1, MFLAGS), + MUX(CLK_V1PLL_REF, "clk_v1pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED, + RK3506_PMU_CLKSEL_CON(6), 1, 1, MFLAGS), + + /* secure ns */ + GATE(CLK_CORE_CRYPTO_NS, "clk_core_crypto_ns", "clk_core_crypto", 0, + RK3506_CLKGATE_CON(5), 12, GFLAGS), + GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto", 0, + RK3506_CLKGATE_CON(5), 13, GFLAGS), + + /* io */ + GATE(CLK_SPI2, "clk_spi2", "clk_spi2_io", 0, + RK3506_CLKGATE_CON(20), 0, GFLAGS), +}; + +static void __iomem *rk3506_cru_base; + +static void rk3506_dump_cru(void) +{ + if (rk3506_cru_base) { + pr_warn("CRU:\n"); + print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, + 32, 4, rk3506_cru_base, + 0xc30, false); + pr_warn("PMU CRU:\n"); + print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, + 32, 4, rk3506_cru_base + RK3506_PMU_CRU_BASE, + 0xa08, false); + } +} + +static void __init rk3506_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + rk3506_cru_base = reg_base; + + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rk3506_pll_clks, + ARRAY_SIZE(rk3506_pll_clks), + RK3506_GRF_SOC_STATUS); + + rockchip_clk_register_armclk_v2(ctx, &rk3506_armclk, + rk3506_cpuclk_rates, + ARRAY_SIZE(rk3506_cpuclk_rates)); + + rockchip_clk_register_branches(ctx, rk3506_clk_branches, + ARRAY_SIZE(rk3506_clk_branches)); + + rockchip_register_softrst(np, 23, reg_base + RK3506_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + + rockchip_register_restart_notifier(ctx, RK3506_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); + + if (!rk_dump_cru) + rk_dump_cru = rk3506_dump_cru; + + /* pvtpll src init */ + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RK3506_CLKSEL_CON(15)); +} + +CLK_OF_DECLARE(rk3506_cru, "rockchip,rk3506-cru", rk3506_clk_init); + +#ifdef MODULE +struct clk_rk3506_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3506_inits clk_3506_cru_init = { + .inits = rk3506_clk_init, +}; + +static const struct of_device_id clk_rk3506_match_table[] = { + { + .compatible = "rockchip,rk3506-cru", + .data = &clk_3506_cru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3506_match_table); + +static int clk_rk3506_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + const struct clk_rk3506_inits *init_data; + + match = of_match_device(clk_rk3506_match_table, &pdev->dev); + if (!match || !match->data) + return -EINVAL; + + init_data = match->data; + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct platform_driver clk_rk3506_driver = { + .probe = clk_rk3506_probe, + .driver = { + .name = "clk-rk3506", + .of_match_table = clk_rk3506_match_table, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(clk_rk3506_driver); + +MODULE_DESCRIPTION("Rockchip RK3506 Clock Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clk-rk3506"); +#endif /* MODULE */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 3e858db66051..2fd3526a2abe 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -305,6 +305,18 @@ struct clk; #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) +#define RK3506_PMU_CRU_BASE 0x10000 +#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE) +#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE) +#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE) +#define RK3506_MODE_CON 0x280 +#define RK3506_GLB_CNT_TH 0xc00 +#define RK3506_GLB_SRST_FST 0xc08 +#define RK3506_GLB_SRST_SND 0xc0c + #define RK3528_PMU_CRU_BASE 0x10000 #define RK3528_PCIE_CRU_BASE 0x20000 #define RK3528_DDRPHY_CRU_BASE 0x28000 From 5844aebe0fa2eac84d9be320aef8038753e200e7 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Fri, 19 May 2023 08:57:10 +0000 Subject: [PATCH 044/191] soc: rockchip: Adds CPU_RK3506 config Signed-off-by: Huibin Hong Change-Id: Ia4b66dabe6a582cf0a581a7d753d20381d571eca --- drivers/soc/rockchip/Kconfig.cpu | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/rockchip/Kconfig.cpu b/drivers/soc/rockchip/Kconfig.cpu index b3c014ec5618..7cfcabf7c942 100644 --- a/drivers/soc/rockchip/Kconfig.cpu +++ b/drivers/soc/rockchip/Kconfig.cpu @@ -61,6 +61,9 @@ config CPU_RK3368 config CPU_RK3399 bool "RK3399" +config CPU_RK3506 + bool "RK3506" + config CPU_RK3528 bool "RK3528" From 3e6bcbb063c9bcaa836d2dfc3fb63a71d1acc429 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 May 2023 17:05:35 +0800 Subject: [PATCH 045/191] drm/rockchip: rgb: add support for rk3506 It is needed to enable both dclk_bypass and data_bypass in mcu mode. Signed-off-by: Damon Ding Change-Id: I019a2242a6566fa5cfad0d9b981f020dc755c241 --- drivers/gpu/drm/rockchip/rockchip_rgb.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 78f7bc1f6d74..0322641101af 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -54,6 +54,9 @@ #define RK3288_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 8, 8) #define RK3288_LVDS_CON_TTL_EN(x) HIWORD_UPDATE(x, 6, 6) +#define RK3506_GRF_SOC_CON2 0x0008 +#define RK3506_GRF_VOP_DATA_BYPASS(v) HIWORD_UPDATE(v, 1, 2) + #define RK3562_GRF_IOC_VO_IO_CON 0x10500 #define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6) @@ -1080,6 +1083,22 @@ static const struct rockchip_rgb_data rk3288_rgb = { .funcs = &rk3288_rgb_funcs, }; +static void rk3506_rgb_enable(struct rockchip_rgb *rgb) +{ + regmap_write(rgb->grf, RK3506_GRF_SOC_CON2, + RK3506_GRF_VOP_DATA_BYPASS(rgb->data_sync_bypass ? 0x3 : 0x0)); +} + +static const struct rockchip_rgb_funcs rk3506_rgb_funcs = { + .enable = rk3506_rgb_enable, +}; + +static const struct rockchip_rgb_data rk3506_rgb = { + .rgb_max_dclk_rate = 120000, + .mcu_max_dclk_rate = 120000, + .funcs = &rk3506_rgb_funcs, +}; + static void rk3562_rgb_enable(struct rockchip_rgb *rgb) { regmap_write(rgb->grf, RK3562_GRF_IOC_VO_IO_CON, @@ -1167,6 +1186,7 @@ static const struct of_device_id rockchip_rgb_dt_ids[] = { { .compatible = "rockchip,rk3288-rgb", .data = &rk3288_rgb }, { .compatible = "rockchip,rk3308-rgb", }, { .compatible = "rockchip,rk3368-rgb", }, + { .compatible = "rockchip,rk3506-rgb", .data = &rk3506_rgb }, { .compatible = "rockchip,rk3562-rgb", .data = &rk3562_rgb }, { .compatible = "rockchip,rk3568-rgb", .data = &rk3568_rgb }, { .compatible = "rockchip,rk3576-rgb", .data = &rk3576_rgb }, From 08fbbdb571ef9073be5e5d62ce3034626e233320 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 May 2023 17:04:03 +0800 Subject: [PATCH 046/191] drm/rockchip: vop: add support for rk3506 Signed-off-by: Damon Ding Change-Id: I7a22f0cc3a3830d23d009213048c44db57854250 --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 132 ++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 2 + 2 files changed, 134 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index ecf4927c7447..f2fdf6f65150 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1991,6 +1991,134 @@ static const struct vop_data rv1106_vop = { .win_size = ARRAY_SIZE(rv1106_vop_win_data), }; +static const struct vop_ctrl rk3506_ctrl_data = { + .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), + + .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), + + .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), + .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), + + .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), + .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), + .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), + .yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4), + + .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), + .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), + .bt1120_uv_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 5), + .bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6), + .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), + .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), + .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), + .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), + .bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30), + .bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31), + + .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), + .dsp_interlace_pol = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 1), + .dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), + .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), + .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), + .dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6), + .dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7), + .dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), + .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), + .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9), + .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11), + .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12), + .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), + .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), + .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), + + .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), + .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), + .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), + .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), + .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), + .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), + + .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), + .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), + .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), + .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), + .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), + .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), + + .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), + .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), + .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), + .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), + .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), + .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), + + .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), + .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), + .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), + .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), + .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), + .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), + .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), + .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), + .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), + .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), + .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), + .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, + 0xffffffff, 0), +}; + +static const struct vop_win_phy rk3506_lit_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + + .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), + .csc_mode = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 2), + .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), + .interlace_read = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 8), + .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), + + .channel = VOP_REG(RK3366_LIT_WIN1_CTRL1, 0xf, 8), + + .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), + + .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), + + .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), + + .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), + + .color_key = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0), + .color_key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24), + + .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), + .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 2), + .global_alpha_val = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0xff, 4), +}; + +static const struct vop_win_data rk3506_vop_win_data[] = { + { .phy = NULL }, + { .base = 0x00, .phy = &rk3506_lit_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_grf_ctrl rk3506_grf_ctrl = { + .grf_dclk_inv = VOP_REG(RK3506_GRF_SOC_CON2, 0x1, 0), +}; + +static const struct vop_data rk3506_vop = { + .soc_id = 0x3506, + .vop_id = 0, + .version = VOP_VERSION(2, 0xc), + .max_input = {1280, 1280}, + .max_output = {1280, 1280}, + .ctrl = &rk3506_ctrl_data, + .intr = &rk3366_lit_intr, + .grf = &rk3506_grf_ctrl, + .win = rk3506_vop_win_data, + .win_size = ARRAY_SIZE(rk3506_vop_win_data), +}; + static const struct vop_ctrl rk3576_lit_ctrl_data = { .cfg_done = VOP_REG(EBC_CONFIG_DONE, 0x1, 0), @@ -2178,6 +2306,10 @@ static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3328-vop", .data = &rk3328_vop }, #endif +#if IS_ENABLED(CONFIG_CPU_RK3506) + { .compatible = "rockchip,rk3506-vop", + .data = &rk3506_vop }, +#endif #if IS_ENABLED(CONFIG_CPU_RK3576) { .compatible = "rockchip,rk3576-vop-lit", .data = &rk3576_vop_lit }, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 9aea51e0a8ad..e42c07dbcf9b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1039,6 +1039,8 @@ #define RV1126_GRF_IOFUNC_CON3 0x1026c +#define RK3506_GRF_SOC_CON2 0x0008 + #define RK3562_GRF_IOC_VO_IO_CON 0x10500 /* rk3568 vop registers definition */ From c95d3b236d055c9575f3b9d1ce92b3278509b2e7 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Mon, 1 Apr 2024 15:19:12 +0800 Subject: [PATCH 047/191] drm/rockchip: ROCKCHIP_VOP depends on CPU_RK3506 Signed-off-by: Tao Huang Change-Id: I406b3842c7adcdb4dd8bc7478bbcec02cb140e5c --- drivers/gpu/drm/rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 34932688d467..46523da01eec 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -49,7 +49,7 @@ config ROCKCHIP_VOP CPU_PX30 || CPU_RK3308 || CPU_RV1106 || \ CPU_RV1126 || CPU_RK3288 || CPU_RK3368 || \ CPU_RK3399 || CPU_RK322X || CPU_RK3328 || \ - CPU_RK3576 + CPU_RK3576 || CPU_RK3506 default y if !ROCKCHIP_MINI_KERNEL help This selects support for the VOP driver. You should enable it From 0ac32f541e108e05869116fb903636e88136ed74 Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Wed, 8 May 2024 15:03:13 +0800 Subject: [PATCH 048/191] pinctrl: rockchip: add rk3506 support Signed-off-by: Ye Zhang Change-Id: I7df8bb9b94908c7773258bf363684768a9387be0 --- drivers/pinctrl/pinctrl-rockchip.c | 451 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 4 + 2 files changed, 441 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 39e464decde4..103fe41638aa 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -123,6 +123,29 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \ + iom1, iom2, iom3, \ + offset0, offset1, \ + offset2, offset3, drv0, \ + drv1, drv2, drv3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num = id, \ @@ -236,6 +259,35 @@ .pull_type[3] = pull3, \ } +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \ + label, iom0, iom1, \ + iom2, iom3, offset0, \ + offset1, offset2, \ + offset3, drv0, drv1, \ + drv2, drv3, pull0, \ + pull1, pull2, pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ { \ .bank_num = ID, \ @@ -1134,6 +1186,13 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) else regmap = info->regmap_base; + if (ctrl->type == RK3506) { + if (bank->bank_num == 1) + regmap = info->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; reg = bank->iomux[iomux_num].offset; @@ -1254,6 +1313,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + if (ctrl->type == RK3506) { + if (bank->bank_num == 1) + regmap = info->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + } + regmap_sys = info->regmap_sys_grf; /* get basic quadrupel of mux registers and the correct reg inside */ @@ -2352,6 +2418,262 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg = RK3506_DRV_GPIO0_D_OFFSET; + *bit = 3; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_DRV_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_DRV_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_DRV_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_DRV_GPIO4_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_DRV_PINS_PER_REG; + *bit *= RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg = RK3506_PULL_GPIO0_D_OFFSET; + *bit = 5; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_PULL_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_PULL_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_PULL_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_PULL_GPIO4_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_PULL_PINS_PER_REG; + *bit *= RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = info->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg = RK3506_SMT_GPIO0_D_OFFSET; + *bit = 9; + + return 0; + } + break; + + case 1: + *regmap = info->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_SMT_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = info->regmap_base; + if (pin_num < 17) + *reg = RK3506_SMT_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = info->regmap_base; + if (pin_num < 15) + *reg = RK3506_SMT_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_SMT_GPIO4_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_SMT_PINS_PER_REG; + *bit *= RK3506_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3528_DRV_BITS_PER_PIN 8 #define RK3528_DRV_PINS_PER_REG 2 #define RK3528_DRV_GPIO0_OFFSET 0x100 @@ -3140,6 +3462,25 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_SMIC: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + data &= (1 << 8) - 1; + + ret = hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; @@ -3193,6 +3534,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, ret = strength; goto config; } else if (ctrl->type == RV1106 || + ctrl->type == RK3506 || ctrl->type == RK3528 || ctrl->type == RK3562 || ctrl->type == RK3568) { @@ -3273,6 +3615,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, } config: + if (ctrl->type == RK3506) { + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + rmask_bits = 2; + ret = strength; + } + } /* enable the write to the equivalent lower bits */ data = ((1 << rmask_bits) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -3371,6 +3719,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3308: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3434,6 +3783,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3308: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3554,6 +3904,10 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) break; } + if (ctrl->type == RK3506) + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) + return data & 0x3; + return data & 0x1; } @@ -3589,6 +3943,14 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, break; } + if (ctrl->type == RK3506) { + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + data = 0x3 << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x3 : 0) << bit); + } + } + return regmap_update_bits(regmap, reg, rmask, data); } @@ -3786,6 +4148,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3308: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -4505,22 +4868,13 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) } /* try to find the optional reference to the sys_grf syscon */ - node = of_parse_phandle(np, "rockchip,sys-grf", 0); - if (node) { - info->regmap_sys_grf = syscon_node_to_regmap(node); - of_node_put(node); - if (IS_ERR(info->regmap_sys_grf)) - return PTR_ERR(info->regmap_sys_grf); - } + info->regmap_sys_grf = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,sys-grf"); /* try to find the optional reference to the pmu syscon */ - node = of_parse_phandle(np, "rockchip,pmu", 0); - if (node) { - info->regmap_pmu = syscon_node_to_regmap(node); - of_node_put(node); - if (IS_ERR(info->regmap_pmu)) - return PTR_ERR(info->regmap_pmu); - } + info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu"); + + /* try to find the optional reference to the ioc1 syscon */ + info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) { ret = rk3308_soc_data_init(info); @@ -5093,6 +5447,71 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl __maybe_unused = { .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3506_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 0, 0, 0, 1), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 1, 1, 1, 1), +}; + +static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = { + .pin_banks = rk3506_pin_banks, + .nr_banks = ARRAY_SIZE(rk3506_pin_banks), + .label = "RK3506-GPIO", + .type = RK3506, + .pull_calc_reg = rk3506_calc_pull_reg_and_bit, + .drv_calc_reg = rk3506_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3528_pin_banks[] = { PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_WIDTH_4BIT, @@ -5338,6 +5757,10 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, #endif +#ifdef CONFIG_CPU_RK3506 + { .compatible = "rockchip,rk3506-pinctrl", + .data = &rk3506_pin_ctrl }, +#endif #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-pinctrl", .data = &rk3528_pin_ctrl }, diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 528088ecbb73..e3bb0f85ebe5 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -197,6 +197,7 @@ enum rockchip_pinctrl_type { RK3308, RK3368, RK3399, + RK3506, RK3528, RK3562, RK3568, @@ -262,6 +263,8 @@ enum rockchip_pin_drv_type { DRV_TYPE_IO_1V8_3V0_AUTO, DRV_TYPE_IO_3V3_ONLY, DRV_TYPE_IO_SMIC, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, DRV_TYPE_MAX }; @@ -465,6 +468,7 @@ struct rockchip_pinctrl { struct regmap *regmap_pull; struct regmap *regmap_pmu; struct regmap *regmap_sys_grf; + struct regmap *regmap_ioc1; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; From 7bcacad517cff047ebda36d5f777c46fe50fb2fd Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Mon, 13 May 2024 15:24:40 +0800 Subject: [PATCH 049/191] pinctrl: rockchip: add rk3506 rmio support Signed-off-by: Ye Zhang Change-Id: I1de1e16f0780a34c72e69262914ba8073375db02 --- drivers/pinctrl/pinctrl-rockchip.c | 75 ++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 76 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 103fe41638aa..dced0bb26c36 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1272,6 +1272,74 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, return 0; } +static int rockchip_set_rmio(struct rockchip_pin_bank *bank, int pin, int *mux) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct regmap *regmap; + int reg, function; + u32 data, rmask; + int ret = 0; + int iomux_num = (pin / 8); + u32 iomux_max, mux_type; + + mux_type = bank->iomux[iomux_num].type; + if (mux_type & IOMUX_WIDTH_4BIT) + iomux_max = (1 << 4) - 1; + else if (mux_type & IOMUX_WIDTH_3BIT) + iomux_max = (1 << 3) - 1; + else + iomux_max = (1 << 2) - 1; + + if (*mux > iomux_max) + function = *mux - iomux_max; + else + return 0; + + switch (ctrl->type) { + case RK3506: + regmap = info->regmap_rmio; + if (bank->bank_num == 0) { + if (pin < 24) + reg = 0x80 + 0x4 * pin; + else + ret = -EINVAL; + } else if (bank->bank_num == 1) { + if (pin >= 9 && pin <= 11) + reg = 0xbc + 0x4 * pin; + else if (pin >= 18 && pin <= 19) + reg = 0xa4 + 0x4 * pin; + else if (pin >= 25 && pin <= 27) + reg = 0x90 + 0x4 * pin; + else + ret = -EINVAL; + } else { + ret = -EINVAL; + } + + if (ret) { + dev_err(info->dev, + "rmio unsupported bank_num %d function %d\n", + bank->bank_num, function); + + return -EINVAL; + } + + rmask = 0x7f007f; + data = 0x7f0000 | function; + *mux = 7; + ret = regmap_update_bits(regmap, reg, rmask, data); + if (ret) + return ret; + break; + + default: + break; + } + + return 0; +} + /* * Set a new mux function for a pin. * @@ -1306,6 +1374,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + ret = rockchip_set_rmio(bank, pin, &mux); + if (ret) + return ret; + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) regmap = info->regmap_pmu; else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) @@ -4876,6 +4948,9 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + /* try to find the optional reference to the rmio syscon */ + info->regmap_rmio = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,rmio"); + if (IS_ENABLED(CONFIG_CPU_RK3308) && ctrl->type == RK3308) { ret = rk3308_soc_data_init(info); if (ret) diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index e3bb0f85ebe5..808c58c93c47 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -469,6 +469,7 @@ struct rockchip_pinctrl { struct regmap *regmap_pmu; struct regmap *regmap_sys_grf; struct regmap *regmap_ioc1; + struct regmap *regmap_rmio; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; From 0d6962db93ac635a553e37b73e31ff748b62d90d Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 5 Jan 2024 10:34:37 +0800 Subject: [PATCH 050/191] video: rockchip: rga3: add support guass3x3 Change-Id: I75f6d899986f9ced6beabaa9b4e67d53b5d266d6 Signed-off-by: Yu Qiaowei --- drivers/video/rockchip/rga3/include/rga.h | 11 +++- .../rockchip/rga3/include/rga2_reg_info.h | 12 ++++ drivers/video/rockchip/rga3/rga2_reg_info.c | 61 ++++++++++++++++++- 3 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/video/rockchip/rga3/include/rga.h b/drivers/video/rockchip/rga3/include/rga.h index 7f8e5e6c01bc..91efb7b8a9a2 100644 --- a/drivers/video/rockchip/rga3/include/rga.h +++ b/drivers/video/rockchip/rga3/include/rga.h @@ -421,6 +421,11 @@ struct rga_mosaic_info { uint8_t mode; }; +struct rga_gauss_config { + uint32_t size; + uint64_t coe_ptr; +}; + /* MAX(min, (max - channel_value)) */ struct rga_osd_invert_factor { uint8_t alpha_max; @@ -745,7 +750,9 @@ struct rga_req { struct rga_rgba5551_alpha rgba5551_alpha; - uint8_t reservr[39]; + struct rga_gauss_config gauss_config; + + uint8_t reservr[27]; }; struct rga_alpha_config { @@ -878,6 +885,8 @@ struct rga2_req { struct rga_iommu_prefetch iommu_prefetch; struct rga_rgba5551_alpha rgba5551_alpha; + + struct rga_gauss_config gauss_config; }; struct rga3_req { diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h index dcb4da13cd79..cca8a20b16b2 100644 --- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h +++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h @@ -61,6 +61,7 @@ #define RGA2_OSD_CTRL1_OFFSET 0x024 // repeat #define RGA2_SRC_BG_COLOR_OFFSET 0x028 #define RGA2_OSD_COLOR0_OFFSET 0x028 // repeat +#define RGA2_GAUSS_COE_OFFSET 0x028 // repeat #define RGA2_SRC_FG_COLOR_OFFSET 0x02c #define RGA2_OSD_COLOR1_OFFSET 0x02c // repeat #define RGA2_SRC_TR_COLOR0_OFFSET 0x030 @@ -209,6 +210,7 @@ #define m_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN (0x1 << 12) #define m_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN (0x1 << 13) #define m_RGA2_MODE_CTRL_SW_FBC_IN_EN (0x1 << 16) +#define m_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN (0x1 << 17) #define m_RGA2_MODE_CTRL_SW_FBC_BSP_DIS (0x1 << 18) #define m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS (0x1 << 19) #define m_RGA2_MODE_CTRL_SW_AXI_WR128_DIS (0x1 << 20) @@ -226,6 +228,7 @@ #define s_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN(x) ((x & 0x1) << 12) #define s_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN(x) ((x & 0x1) << 13) #define s_RGA2_MODE_CTRL_SW_FBC_IN_EN(x) ((x & 0x1) << 16) +#define s_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN(x) ((x & 0x1) << 17) #define s_RGA2_MODE_CTRL_SW_FBC_BSP_DIS(x) ((x & 0x1) << 18) #define s_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS(x) ((x & 0x1) << 19) #define s_RGA2_MODE_CTRL_SW_AXI_WR128_DIS(x) ((x & 0x1) << 20) @@ -312,6 +315,15 @@ #define s_RGA2_OSD_CTRL0_SW_OSD_FIX_WIDTH(x) ((x & 0x3ff) << 20) #define s_RGA2_OSD_CTRL0_SW_OSD_2BPP_MODE(x) ((x & 0x1) << 30) +/* RGA2_GAUSS_COE */ +#define m_RGA2_GAUSS_COE_SW_COE0 (0x3f << 0) +#define m_RGA2_GAUSS_COE_SW_COE1 (0x3f << 8) +#define m_RGA2_GAUSS_COE_SW_COE2 (0xff << 16) + +#define s_RGA2_GAUSS_COE_SW_COE0(x) ((x & 0x3f) << 0) +#define s_RGA2_GAUSS_COE_SW_COE1(x) ((x & 0x3f) << 8) +#define s_RGA2_GAUSS_COE_SW_COE2(x) ((x & 0xff) << 16) + /* RGA2_OSD_CTRL1 */ #define m_RGA2_OSD_CTRL1_SW_OSD_COLOR_SEL (0x1 << 0) #define m_RGA2_OSD_CTRL1_SW_OSD_FLAG_SEL (0x1 << 1) diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index 531401e45054..5995e60879f0 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -225,6 +225,10 @@ static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg) reg = ((reg & (~m_RGA2_MODE_CTRL_SW_OSD_E)) | (s_RGA2_MODE_CTRL_SW_OSD_E(msg->osd_info.enable))); + if (msg->gauss_config.size > 0) + reg = ((reg & (~m_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN)) | + (s_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN(1))); + *bRGA_MODE_CTL = reg; } @@ -1905,6 +1909,50 @@ static void RGA_set_reg_mosaic(u8 *base, struct rga2_req *msg) *bRGA_MOSAIC_MODE = (u32)(msg->mosaic_info.mode & 0x7); } +static int RGA_set_reg_gauss(u8 *base, struct rga2_req *msg) +{ + uint32_t *bRGA_GAUSS_COE; + uint32_t reg = 0; + uint32_t *coe; + + bRGA_GAUSS_COE = (u32 *)(base + RGA2_GAUSS_COE_OFFSET); + + if (msg->gauss_config.size != 3) { + pr_err("Gaussian blur only support 3x3\n"); + return -EINVAL; + } + + coe = kmalloc(sizeof(uint32_t) * msg->gauss_config.size, GFP_KERNEL); + if (coe == NULL) { + pr_err("Gaussian blur alloc coe buffer error!\n"); + return -ENOMEM; + } + + if (unlikely(copy_from_user(coe, + u64_to_user_ptr(msg->gauss_config.coe_ptr), + sizeof(uint32_t) * msg->gauss_config.size))) { + pr_err("Gaussian blur coe copy_from_user failed\n"); + + kfree(coe); + return -EFAULT; + } + + reg = ((reg & (~m_RGA2_GAUSS_COE_SW_COE0)) | + (s_RGA2_GAUSS_COE_SW_COE0(coe[0]))); + + reg = ((reg & (~m_RGA2_GAUSS_COE_SW_COE1)) | + (s_RGA2_GAUSS_COE_SW_COE1(coe[1]))); + + reg = ((reg & (~m_RGA2_GAUSS_COE_SW_COE2)) | + (s_RGA2_GAUSS_COE_SW_COE2(coe[2]))); + + *bRGA_GAUSS_COE = reg; + + kfree(coe); + + return 0; +} + static void RGA2_set_reg_osd(u8 *base, struct rga2_req *msg) { u32 *bRGA_OSD_CTRL0; @@ -2213,6 +2261,7 @@ static void RGA2_set_mmu_reg_info(struct rga_scheduler_t *scheduler, u8 *base, s static int rga2_gen_reg_info(struct rga_scheduler_t *scheduler, u8 *base, struct rga2_req *msg) { + int ret; u8 dst_nn_quantize_en = 0; RGA2_set_mode_ctrl(base, msg); @@ -2236,6 +2285,11 @@ static int rga2_gen_reg_info(struct rga_scheduler_t *scheduler, u8 *base, struct RGA_set_reg_mosaic(base, msg); if (msg->osd_info.enable) RGA2_set_reg_osd(base, msg); + if (msg->gauss_config.size > 0) { + ret = RGA_set_reg_gauss(base, msg); + if (ret < 0) + return ret; + } break; case COLOR_FILL_MODE: @@ -2266,7 +2320,7 @@ static int rga2_gen_reg_info(struct rga_scheduler_t *scheduler, u8 *base, struct break; default: pr_err("ERROR msg render mode %d\n", msg->render_mode); - break; + return -EINVAL; } RGA2_set_mmu_reg_info(scheduler, base, msg); @@ -2428,6 +2482,8 @@ static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler, /* RGA2 1106 add */ memcpy(&req->mosaic_info, &req_rga->mosaic_info, sizeof(req_rga->mosaic_info)); + memcpy(&req->gauss_config, &req_rga->gauss_config, sizeof(req_rga->gauss_config)); + if ((scheduler->data->feature & RGA_YIN_YOUT) && rga_is_only_y_format(req->src.format) && rga_is_only_y_format(req->dst.format)) @@ -2767,7 +2823,8 @@ static int rga2_init_reg(struct rga_job *job) if (scheduler->data->mmu == RGA_IOMMU) req.CMD_fin_int_enable = 1; - if (rga2_gen_reg_info(scheduler, (uint8_t *)job->cmd_buf->vaddr, &req) == -1) { + ret = rga2_gen_reg_info(scheduler, (uint8_t *)job->cmd_buf->vaddr, &req); + if (ret < 0) { pr_err("gen reg info error\n"); return -EINVAL; } From 8962a64e90be56615e19b34ae0c1e4c18f823b44 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Fri, 12 Apr 2024 10:15:00 +0800 Subject: [PATCH 051/191] video: rockchip: rga3: support RK3506 Signed-off-by: Yu Qiaowei Change-Id: Idc97b31050002130cb2ce07b53f8e42e9acaaa76 --- drivers/video/rockchip/rga3/include/rga.h | 1 + .../rockchip/rga3/include/rga_hw_config.h | 1 + drivers/video/rockchip/rga3/rga_drv.c | 2 + drivers/video/rockchip/rga3/rga_hw_config.c | 59 +++++++++++++++++++ 4 files changed, 63 insertions(+) diff --git a/drivers/video/rockchip/rga3/include/rga.h b/drivers/video/rockchip/rga3/include/rga.h index 91efb7b8a9a2..857d98ffe14a 100644 --- a/drivers/video/rockchip/rga3/include/rga.h +++ b/drivers/video/rockchip/rga3/include/rga.h @@ -159,6 +159,7 @@ enum { RGA_OSD = 0x1 << 11, RGA_PRE_INTR = 0x1 << 12, RGA_FULL_CSC = 0x1 << 13, + RGA_GAUSS = 0x1 << 14, }; enum rga_surf_format { diff --git a/drivers/video/rockchip/rga3/include/rga_hw_config.h b/drivers/video/rockchip/rga3/include/rga_hw_config.h index 61390902175a..c4982e037e42 100644 --- a/drivers/video/rockchip/rga3/include/rga_hw_config.h +++ b/drivers/video/rockchip/rga3/include/rga_hw_config.h @@ -76,6 +76,7 @@ struct rga_hw_data { extern const struct rga_hw_data rga3_data; extern const struct rga_hw_data rga2e_data; extern const struct rga_hw_data rga2e_1106_data; +extern const struct rga_hw_data rga2e_3506_data; extern const struct rga_hw_data rga2e_iommu_data; extern const struct rga_hw_data rga2p_iommu_data; extern const struct rga_hw_data rga2p_lite_1103b_data; diff --git a/drivers/video/rockchip/rga3/rga_drv.c b/drivers/video/rockchip/rga3/rga_drv.c index ac74808581e7..d692f58df3eb 100644 --- a/drivers/video/rockchip/rga3/rga_drv.c +++ b/drivers/video/rockchip/rga3/rga_drv.c @@ -1371,6 +1371,8 @@ static int rga_drv_probe(struct platform_device *pdev) } else if (!strcmp(scheduler->version.str, "3.6.92812") || !strcmp(scheduler->version.str, "3.7.93215")) { scheduler->data = &rga2e_iommu_data; + } else if (!strcmp(scheduler->version.str, "3.a.07135")) { + scheduler->data = &rga2e_3506_data; } else if (!strcmp(scheduler->version.str, "3.e.19357")) { scheduler->data = &rga2p_iommu_data; rga_hw_set_issue_mask(scheduler, RGA_HW_ISSUE_DIS_AUTO_RST); diff --git a/drivers/video/rockchip/rga3/rga_hw_config.c b/drivers/video/rockchip/rga3/rga_hw_config.c index f1d1bc8da799..6eccd4ec1148 100644 --- a/drivers/video/rockchip/rga3/rga_hw_config.c +++ b/drivers/video/rockchip/rga3/rga_hw_config.c @@ -399,6 +399,41 @@ const struct rga_win_data rga2e_win_data[] = { }, }; +const struct rga_win_data rga2e_3506_win_data[] = { + { + .name = "rga2e-src0", + .formats[RGA_RASTER_INDEX] = rga2e_input_raster_format, + .formats_count[RGA_RASTER_INDEX] = ARRAY_SIZE(rga2e_input_raster_format), + .supported_rotations = RGA_MODE_ROTATE_MASK, + .scale_up_mode = RGA_SCALE_UP_BIC, + .scale_down_mode = RGA_SCALE_DOWN_AVG, + .rd_mode = RGA_RASTER_MODE, + + }, + + { + .name = "rga2e-src1", + .formats[RGA_RASTER_INDEX] = rga2p_input_raster_format, + .formats_count[RGA_RASTER_INDEX] = ARRAY_SIZE(rga2p_input_raster_format), + .supported_rotations = RGA_MODE_ROTATE_MASK, + .scale_up_mode = RGA_SCALE_UP_BIC, + .scale_down_mode = RGA_SCALE_DOWN_AVG, + .rd_mode = RGA_RASTER_MODE, + + }, + + { + .name = "rga2-dst", + .formats[RGA_RASTER_INDEX] = rga2e_output_raster_format, + .formats_count[RGA_RASTER_INDEX] = ARRAY_SIZE(rga2e_output_raster_format), + .supported_rotations = 0, + .scale_up_mode = RGA_SCALE_UP_NONE, + .scale_down_mode = RGA_SCALE_DOWN_NONE, + .rd_mode = RGA_RASTER_MODE, + + }, +}; + const struct rga_win_data rga2p_win_data[] = { { .name = "rga2p-src0", @@ -537,6 +572,30 @@ const struct rga_hw_data rga2e_1106_data = { .mmu = RGA_NONE_MMU, }; +const struct rga_hw_data rga2e_3506_data = { + .version = 0, + .input_range = {{2, 2}, {1280, 1280}}, + .output_range = {{2, 2}, {1280, 1280}}, + + .win = rga2e_3506_win_data, + .win_size = ARRAY_SIZE(rga2e_3506_win_data), + /* 1 << factor mean real factor */ + .max_upscale_factor = 4, + .max_downscale_factor = 4, + + .byte_stride_align = 4, + .max_byte_stride = WORD_TO_BYTE(8192), + + .feature = RGA_COLOR_FILL | RGA_COLOR_PALETTE | + RGA_COLOR_KEY | RGA_YIN_YOUT | RGA_YUV_HDS | RGA_YUV_VDS | + RGA_PRE_INTR | RGA_FULL_CSC | RGA_GAUSS, + .csc_r2y_mode = RGA_MODE_CSC_BT601L | RGA_MODE_CSC_BT601F | + RGA_MODE_CSC_BT709, + .csc_y2r_mode = RGA_MODE_CSC_BT601L | RGA_MODE_CSC_BT601F | + RGA_MODE_CSC_BT709, + .mmu = RGA_NONE_MMU, +}; + const struct rga_hw_data rga2e_iommu_data = { .version = 0, .input_range = {{2, 2}, {8192, 8192}}, From 76d1edc652a1f945c9c1a15afc86b27c522ae4ca Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Tue, 18 Jun 2024 14:24:34 +0800 Subject: [PATCH 052/191] ASoC: codecs: rk_dsm: support rk3506 Change-Id: I7962f87ebece05e444d86e79605521421124ced8 Signed-off-by: Jason Zhu --- sound/soc/codecs/rk_dsm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/sound/soc/codecs/rk_dsm.c b/sound/soc/codecs/rk_dsm.c index 8228111f2392..1849fadea025 100644 --- a/sound/soc/codecs/rk_dsm.c +++ b/sound/soc/codecs/rk_dsm.c @@ -23,6 +23,8 @@ #include #include "rk_dsm.h" +#define RK3506_GRF_SOC_CON0 (0x0) +#define RK3506_DSM_SEL (9) #define RK3562_GRF_PERI_AUDIO_CON (0x0070) #define RK3576_SYS_GRF_SOC_CON2 (0x0008) #define RK3576_DSM_SEL (0x0) @@ -460,6 +462,27 @@ static const struct regmap_config rd_regmap_config = { .cache_type = REGCACHE_FLAT, }; +static int rk3506_soc_init(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + + /* enable internal codec to sai3 */ + return regmap_write(rd->grf, RK3506_GRF_SOC_CON0, + BIT(RK3506_DSM_SEL) << 16 | BIT(RK3506_DSM_SEL)); +} + +static void rk3506_soc_deinit(struct device *dev) +{ + struct rk_dsm_priv *rd = dev_get_drvdata(dev); + + regmap_write(rd->grf, RK3506_GRF_SOC_CON0, BIT(RK3506_DSM_SEL) << 16); +} + +static const struct rk_dsm_soc_data rk3506_data = { + .init = rk3506_soc_init, + .deinit = rk3506_soc_deinit, +}; + static int rk3562_soc_init(struct device *dev) { struct rk_dsm_priv *rd = dev_get_drvdata(dev); @@ -504,6 +527,7 @@ static const struct rk_dsm_soc_data rk3576_data = { #ifdef CONFIG_OF static const struct of_device_id rd_of_match[] = { + { .compatible = "rockchip,rk3506-dsm", .data = &rk3506_data }, { .compatible = "rockchip,rk3562-dsm", .data = &rk3562_data }, { .compatible = "rockchip,rk3576-dsm", .data = &rk3576_data }, {}, From f0e2691515822b8876f3f1dca846a2d4224451c9 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 17 Jun 2024 17:46:35 +0800 Subject: [PATCH 053/191] ethernet: stmmac: dwmac-rk: Add RK3506 GMAC support Change-Id: I1fbb1adbc09f6575b304975b934954d5e603faeb Signed-off-by: David Wu --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index c73d147230d3..a0d227a6fec2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -1393,6 +1393,84 @@ static const struct rk_gmac_ops rk3399_ops = { .set_rmii_speed = rk3399_set_rmii_speed, }; +#define RK3506_GRF_SOC_CON8 0X0020 +#define RK3506_GRF_SOC_CON11 0X002c + +#define RK3506_GMAC_RMII_MODE GRF_BIT(1) + +#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3) + +#define RK3506_GMAC_CLK_SELET_CRU GRF_CLR_BIT(5) +#define RK3506_GMAC_CLK_SELET_IO GRF_BIT(5) + +#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) +#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) + +static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + struct device *dev = &bsp_priv->pdev->dev; + unsigned int id = bsp_priv->id, offset; + + if (IS_ERR(bsp_priv->grf)) { + dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); + return; + } + + offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; + regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE); +} + +static void rk3506_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev = &bsp_priv->pdev->dev; + unsigned int val, offset, id = bsp_priv->id; + + switch (speed) { + case 10: + val = RK3506_GMAC_CLK_RMII_DIV20; + break; + case 100: + val = RK3506_GMAC_CLK_RMII_DIV2; + break; + default: + goto err; + } + + offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; + regmap_write(bsp_priv->grf, offset, val); + + return; +err: + dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed); +} + +static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv, + bool input, bool enable) +{ + unsigned int value, offset, id = bsp_priv->id; + + offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; + + value = input ? RK3506_GMAC_CLK_SELET_IO : + RK3506_GMAC_CLK_SELET_CRU; + value |= enable ? RK3506_GMAC_CLK_RMII_NOGATE : + RK3506_GMAC_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, offset, value); +} + +static const struct rk_gmac_ops rk3506_ops = { + .set_to_rmii = rk3506_set_to_rmii, + .set_rmii_speed = rk3506_set_rmii_speed, + .set_clock_selection = rk3506_set_clock_selection, + .regs_valid = true, + .regs = { + 0xff4c8000, /* gmac0 */ + 0xff4d0000, /* gmac1 */ + 0x0, /* sentinel */ + }, +}; + #define RK3528_VO_GRF_GMAC_CON 0X60018 #define RK3528_VPU_GRF_GMAC_CON5 0X40018 #define RK3528_VPU_GRF_GMAC_CON6 0X4001c @@ -3147,6 +3225,9 @@ static const struct of_device_id rk_gmac_dwmac_match[] = { #ifdef CONFIG_CPU_RK3399 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, #endif +#ifdef CONFIG_CPU_RK3506 + { .compatible = "rockchip,rk3506-gmac", .data = &rk3506_ops }, +#endif #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, #endif From 76642536d5fdb4edaaa3623046657164e103bd18 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 18 Jun 2024 21:50:36 +0800 Subject: [PATCH 054/191] nvmem: rockchip-otp: Add support for rk3506 This adds the necessary data for handling otp on the rk3506. Change-Id: I370c60b768674dfcda3942a511a120a56d250bb6 Signed-off-by: Finley Xiao --- drivers/nvmem/rockchip-otp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 1a323d620a20..3e43dbe7b08b 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -866,6 +866,12 @@ static const struct of_device_id rockchip_otp_match[] = { .data = (void *)&px30s_data, }, #endif +#ifdef CONFIG_CPU_RK3506 + { + .compatible = "rockchip,rk3506-otp", + .data = (void *)&rk3528_data, + }, +#endif #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-otp", From 84fe01e06ea0ab7f859178cc81a5b65edc5ce2eb Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Wed, 19 Jun 2024 10:48:40 +0800 Subject: [PATCH 055/191] crypto: rockchip: Kconfig: select crypto v3 if RK3506 Signed-off-by: Lin Jinhan Change-Id: I4e617eaac045d111bdd09bfedbd086cf5857df49 --- drivers/crypto/rockchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/rockchip/Kconfig b/drivers/crypto/rockchip/Kconfig index 3efdb1fc73ac..22df0d84381f 100644 --- a/drivers/crypto/rockchip/Kconfig +++ b/drivers/crypto/rockchip/Kconfig @@ -12,8 +12,8 @@ config CRYPTO_DEV_ROCKCHIP_V2 default y config CRYPTO_DEV_ROCKCHIP_V3 - bool "crypto v3/v4 for RV1106/RK3528/RK3562/RK3576" - depends on CPU_RV1106 || CPU_RK3528 || CPU_RK3562 || CPU_RK3576 + bool "crypto v3/v4 for RV1106/RK3506/RK3528/RK3562/RK3576" + depends on CPU_RV1106 || CPU_RK3506 || CPU_RK3528 || CPU_RK3562 || CPU_RK3576 default y endif From f492da7b0759e2c09e064fa603d5711300cc6706 Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Thu, 20 Jun 2024 20:32:51 +0800 Subject: [PATCH 056/191] thermal: rockchip: Support RK3506 SoC in the thermal driver Signed-off-by: Ye Zhang Change-Id: I006c0fae994ffa00557a62b8da8355cefc96f53a --- drivers/thermal/rockchip_thermal.c | 70 ++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 979aea9bc46c..97f3d5b12e09 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -274,8 +274,11 @@ struct rockchip_thermal_data { #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ #define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */ #define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ +#define TSADCV13_AUTO_PERIOD_TIME 2500 /* 2.5ms */ +#define TSADCV13_AUTO_PERIOD_HT_TIME 2500 /* 2.5ms */ #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ #define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */ +#define TSADCV13_Q_MAX_VAL 0x3ff /* 10bit 1023 */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -293,6 +296,8 @@ struct rockchip_thermal_data { #define RK1808_BUS_GRF_SOC_CON0 0x0400 +#define RK3506_GRF_TSADC_CON 0x10 + #define RK3528_GRF_TSADC_CON 0x40030 #define RK3562_GRF_TSADC_CON 0x0580 @@ -644,6 +649,17 @@ static const struct tsadc_table rk3399_code_table[] = { {TSADCV3_DATA_MASK, MAX_TEMP}, }; +static const struct tsadc_table rk3506_code_table[] = { + {0, MIN_TEMP}, + {362, MIN_TEMP}, + {395, -40000}, + {503, 25000}, + {604, 85000}, + {672, 125000}, + {757, MAX_TEMP}, + {TSADCV2_DATA_MASK, MAX_TEMP}, +}; + static const struct tsadc_table rk3528_code_table[] = { {0, MIN_TEMP}, {1386, MIN_TEMP}, @@ -1213,6 +1229,33 @@ static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs, } } +static void rk_tsadcv13_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + regmap_write(grf, RK3506_GRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN); + udelay(10); + regmap_write(grf, RK3506_GRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA); + udelay(100); + + writel_relaxed(TSADCV13_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV13_AUTO_PERIOD_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + writel_relaxed(TSADCV13_Q_MAX_VAL, regs + TSADCV9_Q_MAX); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, + regs + TSADCV2_AUTO_CON); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -1855,6 +1898,27 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3506_tsadc_data = { + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + .chn_num = 1, /* seven channels for tsadc */ + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + .initialize = rk_tsadcv13_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv4_tshut_mode, + .table = { + .id = rk3506_code_table, + .length = ARRAY_SIZE(rk3506_code_table), + .data_mask = TSADCV3_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3528_tsadc_data = { .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ .chn_num = 1, /* one channels for tsadc */ @@ -2057,6 +2121,12 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .data = (void *)&rk3399_tsadc_data, }, #endif +#ifdef CONFIG_CPU_RK3506 + { + .compatible = "rockchip,rk3506-tsadc", + .data = (void *)&rk3506_tsadc_data, + }, +#endif #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-tsadc", From 17ba1d1825d379626973d011e96f9fd1e19ee1e8 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Mon, 17 Jun 2024 15:50:03 +0800 Subject: [PATCH 057/191] mfd: rockchip-flexbus: Support RK3506 Change-Id: Ie33e497abdbdd7e614ddcaa9c2056eb06de705bf Signed-off-by: Wesley Yao --- drivers/mfd/rockchip-flexbus.c | 70 ++++++++++++++++++++++++++-- include/linux/mfd/rockchip-flexbus.h | 19 ++++---- 2 files changed, 77 insertions(+), 12 deletions(-) diff --git a/drivers/mfd/rockchip-flexbus.c b/drivers/mfd/rockchip-flexbus.c index 4109a7112c9f..26030f8d347f 100644 --- a/drivers/mfd/rockchip-flexbus.c +++ b/drivers/mfd/rockchip-flexbus.c @@ -65,6 +65,43 @@ void rockchip_flexbus_clrsetbits(struct rockchip_flexbus *rkfb, unsigned int reg } EXPORT_SYMBOL_GPL(rockchip_flexbus_clrsetbits); +static struct rockchip_flexbus_dfs_reg rockchip_flexbus_dfs_reg_v0 = { + .dfs_2bit = 0x0, + .dfs_4bit = 0x1, + .dfs_8bit = 0x2, + .dfs_16bit = 0x3, + .dfs_mask = 0x3, +}; + +static struct rockchip_flexbus_dfs_reg rockchip_flexbus_dfs_reg_v1 = { + .dfs_1bit = (0x0 << 29), + .dfs_2bit = (0x1 << 29), + .dfs_4bit = (0x2 << 29), + .dfs_8bit = (0x3 << 29), + .dfs_16bit = (0x4 << 29), + .dfs_mask = (0x7 << 29), +}; + +#define RK3506_GRF_SOC_CON1 0x0004 +static void rk3506_flexbus_init_config(struct rockchip_flexbus *rkfb) +{ + regmap_write(rkfb->regmap_grf, RK3506_GRF_SOC_CON1, BIT(4 + 16)); +} + +static void rk3506_flexbus_grf_config(struct rockchip_flexbus *rkfb, bool slave_mode, bool cpol, + bool cpha) +{ + u32 val = 0x3 << 16; + + if (slave_mode) { + if ((!cpol && cpha) || (cpol && !cpha)) + val |= BIT(1); + } else { + val |= BIT(0); + } + regmap_write(rkfb->regmap_grf, RK3506_GRF_SOC_CON1, val); +} + #define RK3576_VCCIO_IOC_MISC_CON0 0x6400 static void rk3576_flexbus_grf_config(struct rockchip_flexbus *rkfb, bool slave_mode, bool cpol, bool cpha) @@ -146,8 +183,10 @@ static int rockchip_flexbus_probe(struct platform_device *pdev) rkfb->regmap_grf = syscon_regmap_lookup_by_phandle_optional(pdev->dev.of_node, "rockchip,grf"); - if (!rkfb->regmap_grf) - dev_warn(&pdev->dev, "failed to get rockchip,grf node.\n"); + if (!rkfb->regmap_grf) { + dev_err(&pdev->dev, "failed to get rockchip,grf node.\n"); + return -ENODEV; + } rkfb->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rkfb->clks); if (rkfb->num_clks <= 0) { @@ -166,6 +205,9 @@ static int rockchip_flexbus_probe(struct platform_device *pdev) return ret; } + if (rkfb->config->init_config) + rkfb->config->init_config(rkfb); + if (rkfb->opmode0 != ROCKCHIP_FLEXBUS0_OPMODE_NULL && rkfb->opmode1 != ROCKCHIP_FLEXBUS1_OPMODE_NULL) rockchip_flexbus_writel(rkfb, FLEXBUS_COM_CTL, FLEXBUS_TX_AND_RX); @@ -174,15 +216,35 @@ static int rockchip_flexbus_probe(struct platform_device *pdev) else rockchip_flexbus_writel(rkfb, FLEXBUS_COM_CTL, FLEXBUS_RX_ONLY); + switch (rockchip_flexbus_readl(rkfb, FLEXBUS_REVISION) >> 24 & 0xff) { + case 0x0: + rkfb->dfs_reg = &rockchip_flexbus_dfs_reg_v0; + break; + case 0x1: + rkfb->dfs_reg = &rockchip_flexbus_dfs_reg_v1; + break; + default: + dev_err(&pdev->dev, "failed to get large version.\n"); + return -EINVAL; + } + return devm_of_platform_populate(&pdev->dev); } +static const struct rockchip_flexbus_config rk3506_flexbus_config = { + .init_config = rk3506_flexbus_init_config, + .grf_config = rk3506_flexbus_grf_config, + .txwat_start_max = 255, +}; + static const struct rockchip_flexbus_config rk3576_flexbus_config = { - .grf_config = rk3576_flexbus_grf_config, - .txwat_start_max = 511, + .init_config = NULL, + .grf_config = rk3576_flexbus_grf_config, + .txwat_start_max = 511, }; static const struct of_device_id rockchip_flexbus_of_match[] = { + { .compatible = "rockchip,rk3506-flexbus", .data = &rk3506_flexbus_config}, { .compatible = "rockchip,rk3576-flexbus", .data = &rk3576_flexbus_config}, { /* sentinel */ } }; diff --git a/include/linux/mfd/rockchip-flexbus.h b/include/linux/mfd/rockchip-flexbus.h index 6eb7ff630102..185702a5da41 100644 --- a/include/linux/mfd/rockchip-flexbus.h +++ b/include/linux/mfd/rockchip-flexbus.h @@ -79,7 +79,6 @@ #define FLEXBUS_CONTINUE_MODE BIT(4) #define FLEXBUS_CPOL BIT(3) #define FLEXBUS_CPHA BIT(2) -#define FLEXBUS_DFS_SHIFT 0 /* Bit fields in TX_CTL */ #define FLEXBUS_TX_CTL_MSB BIT(13) @@ -113,7 +112,17 @@ struct rockchip_flexbus; +struct rockchip_flexbus_dfs_reg { + u32 dfs_1bit; + u32 dfs_2bit; + u32 dfs_4bit; + u32 dfs_8bit; + u32 dfs_16bit; + u32 dfs_mask; +}; + struct rockchip_flexbus_config { + void (*init_config)(struct rockchip_flexbus *rkfb); void (*grf_config)(struct rockchip_flexbus *rkfb, bool slave_mode, bool cpol, bool cpha); u32 txwat_start_max; }; @@ -130,16 +139,10 @@ struct rockchip_flexbus { void *fb1_data; void (*fb0_isr)(struct rockchip_flexbus *rkfb, u32 isr); void (*fb1_isr)(struct rockchip_flexbus *rkfb, u32 isr); + struct rockchip_flexbus_dfs_reg *dfs_reg; const struct rockchip_flexbus_config *config; }; -enum rockchip_flexbus_dfs { - FLEXBUS_DFS_2BIT = 0x0, - FLEXBUS_DFS_4BIT, - FLEXBUS_DFS_8BIT, - FLEXBUS_DFS_16BIT, -}; - unsigned int rockchip_flexbus_readl(struct rockchip_flexbus *rkfb, unsigned int reg); void rockchip_flexbus_writel(struct rockchip_flexbus *rkfb, unsigned int reg, unsigned int val); void rockchip_flexbus_clrbits(struct rockchip_flexbus *rkfb, unsigned int reg, From 4ba43fe12daf505b1c62f3d61f373d6790a46d69 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Mon, 17 Jun 2024 15:51:10 +0800 Subject: [PATCH 058/191] iio: adc: rockchip-flexbus-adc: Support RK3506 Change-Id: I2c0b2c61b2ecd11781f3493268dfaa22e560ea49 Signed-off-by: Wesley Yao --- drivers/iio/adc/rockchip-flexbus-adc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/rockchip-flexbus-adc.c b/drivers/iio/adc/rockchip-flexbus-adc.c index 26be5e01c15f..cfb5e4f9953e 100644 --- a/drivers/iio/adc/rockchip-flexbus-adc.c +++ b/drivers/iio/adc/rockchip-flexbus-adc.c @@ -259,13 +259,13 @@ static int rockchip_flexbus_adc_init(struct rockchip_flexbus_adc *rkfb_adc) switch (rkfb_adc->dfs) { case 4: - val = FLEXBUS_DFS_4BIT; + val = rkfb->dfs_reg->dfs_4bit; break; case 8: - val = FLEXBUS_DFS_8BIT; + val = rkfb->dfs_reg->dfs_8bit; break; case 16: - val = FLEXBUS_DFS_16BIT; + val = rkfb->dfs_reg->dfs_16bit; break; default: return -EINVAL; From 9c318483fa8fc78a8452d11c3c3a592007115059 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Mon, 17 Jun 2024 15:53:03 +0800 Subject: [PATCH 059/191] iio: dac: rockchip-flexbus-dac: Support RK3506 Change-Id: I85d46dc49b6dffc987c154725d6afbea7e1aa3e7 Signed-off-by: Wesley Yao --- drivers/iio/dac/rockchip-flexbus-dac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/dac/rockchip-flexbus-dac.c b/drivers/iio/dac/rockchip-flexbus-dac.c index 3b94e7fa11f9..1057bb820efb 100644 --- a/drivers/iio/dac/rockchip-flexbus-dac.c +++ b/drivers/iio/dac/rockchip-flexbus-dac.c @@ -288,13 +288,13 @@ static int rockchip_flexbus_dac_init(struct rockchip_flexbus_dac *rkfb_dac) switch (rkfb_dac->dfs) { case 4: - val = FLEXBUS_DFS_4BIT; + val = rkfb->dfs_reg->dfs_4bit; break; case 8: - val = FLEXBUS_DFS_8BIT; + val = rkfb->dfs_reg->dfs_8bit; break; case 16: - val = FLEXBUS_DFS_16BIT; + val = rkfb->dfs_reg->dfs_16bit; break; default: return -EINVAL; From 35cee86e0b50568cea98662d83854122d261c1d9 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Mon, 24 Jun 2024 15:36:19 +0800 Subject: [PATCH 060/191] drm/rockchip: dsi: Add support for rk3506 enable dsiphy of lane0 and lane1 for rk3506 Change-Id: I939794c765d56f49a4cc91097d7174a6a3396654 Signed-off-by: Hongming Zou --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 273fb701325c..372a27e3bfa4 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -185,6 +185,13 @@ #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) +#define RK3506_SYS_GRF_SOC_CON6 0x0018 +#define RK3506_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3506_DSI_PHY_ENABLE_LANE1 BIT(9) +#define RK3506_DSI_PHY_ENABLE_LANE0 BIT(8) +#define RK3506_DSI_TURNDISABLE BIT(2) +#define RK3506_DSI_FORCERXMODE BIT(0) + #define RK3562_SYS_GRF_VO_CON1 0x05d4 #define RK3562_DSI_FORCETXSTOPMODE (0xf << 4) #define RK3562_DSI_TURNDISABLE (0x1 << 2) @@ -247,6 +254,7 @@ enum soc_type { RK3128, RK3288, RK3399, + RK3506, RK3562, RK3568, RV1126, @@ -1770,6 +1778,25 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { + { + .reg = 0xff640000, + .lanecfg1_grf_reg = RK3506_SYS_GRF_SOC_CON6, + .lanecfg1 = HIWORD_UPDATE(RK3506_DSI_PHY_ENABLE_LANE0 | + RK3506_DSI_PHY_ENABLE_LANE1, + RK3506_DSI_TURNDISABLE | + RK3506_DSI_FORCERXMODE | + RK3506_DSI_FORCETXSTOPMODE | + RK3506_DSI_PHY_ENABLE_LANE0 | + RK3506_DSI_PHY_ENABLE_LANE1), + + .max_data_lanes = 2, + .max_bit_rate_per_lane = 1500000000UL, + .soc_type = RK3506, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3562_chip_data[] = { { .reg = 0xffb10000, @@ -1843,6 +1870,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, + }, { + .compatible = "rockchip,rk3506-mipi-dsi", + .data = &rk3506_chip_data, }, { .compatible = "rockchip,rk3562-mipi-dsi", .data = &rk3562_chip_data, From 08a7064ac526645673b523c82e3c913175f6b278 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Thu, 27 Jun 2024 14:33:19 +0800 Subject: [PATCH 061/191] ASoC: rockchip: pdm_v2: support pdm gain ctrl in rk3506 Since the pdm gain ctrl is moved to new register. Change-Id: I794cba30256b011816a0894928c9377ceb90f381 Signed-off-by: Jason Zhu --- sound/soc/rockchip/rockchip_pdm_v2.c | 94 ++++++++++++++++++++++------ sound/soc/rockchip/rockchip_pdm_v2.h | 34 +++++++++- 2 files changed, 107 insertions(+), 21 deletions(-) diff --git a/sound/soc/rockchip/rockchip_pdm_v2.c b/sound/soc/rockchip/rockchip_pdm_v2.c index 488e9441badf..334445f364a0 100644 --- a/sound/soc/rockchip/rockchip_pdm_v2.c +++ b/sound/soc/rockchip/rockchip_pdm_v2.c @@ -30,6 +30,9 @@ #define QUIRK_ALWAYS_ON BIT(0) +#define RK3506_PDM 0x2311 +#define RK3576_PDM 0x2302 + struct rk_pdm_v2_clkref { unsigned int sr; unsigned int clk; @@ -65,6 +68,7 @@ struct rk_pdm_v2_dev { unsigned int start_delay_ms; unsigned int clk_ref_frq; unsigned int quirks; + unsigned int version; }; static int get_pdm_v2_clkref(struct rk_pdm_v2_dev *pdm, unsigned int sr) @@ -205,9 +209,18 @@ static int rockchip_pdm_v2_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(pdm->regmap, PDM_V2_CTRL, PDM_V2_SJM_SEL_MSK, PDM_V2_SJM_SEL_L); - regmap_update_bits(pdm->regmap, PDM_V2_FILTER_CTRL, - PDM_V2_HPF_R_MSK | PDM_V2_HPF_L_MSK | PDM_V2_HPF_FREQ_MSK, - PDM_V2_HPF_R_EN | PDM_V2_HPF_L_EN | PDM_V2_HPF_FREQ_60); + if (pdm->version == RK3506_PDM) { + regmap_update_bits(pdm->regmap, PDM_V2_FILTER_CTRL, + PDM_V2_HPF_V2_R_MSK | PDM_V2_HPF_V2_L_MSK | + PDM_V2_HPF_V2_FREQ_MSK, + PDM_V2_HPF_V2_R_EN | PDM_V2_HPF_V2_L_EN | + PDM_V2_HPF_V2_FREQ_60); + } else if (pdm->version == RK3576_PDM) { + regmap_update_bits(pdm->regmap, PDM_V2_FILTER_CTRL, + PDM_V2_HPF_R_MSK | PDM_V2_HPF_L_MSK | PDM_V2_HPF_FREQ_MSK, + PDM_V2_HPF_R_EN | PDM_V2_HPF_L_EN | PDM_V2_HPF_FREQ_60); + } + rockchip_pdm_v2_set_samplerate(pdm, params_rate(params)); switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: @@ -317,12 +330,20 @@ static int rockchip_pdm_v2_prepare(struct snd_pcm_substream *substream, return 0; } +static const struct snd_kcontrol_new rk3506_controls[]; +static const struct snd_kcontrol_new rk3576_controls[]; + static int rockchip_pdm_v2_dai_probe(struct snd_soc_dai *dai) { struct rk_pdm_v2_dev *pdm = to_info(dai); dai->capture_dma_data = &pdm->capture_dma_data; + if (pdm->version == RK3506_PDM) + snd_soc_add_component_controls(dai->component, rk3506_controls, 1); + else if (pdm->version == RK3576_PDM) + snd_soc_add_component_controls(dai->component, rk3576_controls, 1); + return 0; } @@ -411,9 +432,16 @@ static const char * const hpf_cutoff_text[] = { "3.79Hz", "60Hz", "243Hz", "493Hz", }; +static const char * const hpf_v2_cutoff_text[] = { + "0.234Hz", "0.468Hz", "0.937Hz", "1.875Hz", "3.75Hz", + "7.5Hz", "15Hz", "30Hz", "60Hz", "122Hz", "251Hz", + "528Hz", "1183Hz", "3152Hz", +}; + static SOC_ENUM_SINGLE_DECL(hpf_cutoff_enum, PDM_V2_FILTER_CTRL, 19, hpf_cutoff_text); - +static SOC_ENUM_SINGLE_DECL(hpf_v2_cutoff_enum, PDM_V2_FILTER_CTRL, + 21, hpf_v2_cutoff_text); static const DECLARE_TLV_DB_SCALE(pdm_v2_digtal_gain_tlv, -6563, 75, 0); static const struct snd_kcontrol_new rockchip_pdm_v2_controls[] = { @@ -422,17 +450,6 @@ static const struct snd_kcontrol_new rockchip_pdm_v2_controls[] = { SOC_ENUM("Receive PATH1 Source Select", rpath1_enum), SOC_ENUM("Receive PATH0 Source Select", rpath0_enum), - SOC_ENUM("HPF Cutoff", hpf_cutoff_enum), - SOC_SINGLE("HPFL Switch", PDM_V2_FILTER_CTRL, 22, 1, 0), - SOC_SINGLE("HPFR Switch", PDM_V2_FILTER_CTRL, 21, 1, 0), - - SOC_SINGLE_RANGE_TLV("Gain Volume", - PDM_V2_FILTER_CTRL, - PDM_V2_GAIN_CTRL_SHIFT, - PDM_V2_GAIN_MIN, - PDM_V2_GAIN_MAX, - 0, pdm_v2_digtal_gain_tlv), - SOC_SINGLE_EXT("Start Delay Ms", 0, 0, PDM_V2_START_DELAY_MS_MAX, 0, rockchip_pdm_v2_start_delay_get, rockchip_pdm_v2_start_delay_put), @@ -442,6 +459,30 @@ static const struct snd_kcontrol_new rockchip_pdm_v2_controls[] = { rockchip_pdm_v2_clk_ref_frq_put), }; +static const struct snd_kcontrol_new rk3506_controls[] = { + SOC_SINGLE_RANGE_TLV("Gain Volume", + PDM_V2_GAIN_CTRL, + PDM_V2_GAIN_CTRL_SHIFT, + PDM_V2_GAIN_CTRL_MIN, + PDM_V2_GAIN_CTRL_MAX, + 0, pdm_v2_digtal_gain_tlv), + SOC_ENUM("HPF Cutoff", hpf_v2_cutoff_enum), + SOC_SINGLE("HPFL Switch", PDM_V2_FILTER_CTRL, 20, 1, 0), + SOC_SINGLE("HPFR Switch", PDM_V2_FILTER_CTRL, 19, 1, 0), +}; + +static const struct snd_kcontrol_new rk3576_controls[] = { + SOC_SINGLE_RANGE_TLV("Gain Volume", + PDM_V2_FILTER_CTRL, + PDM_V2_GAIN_SHIFT, + PDM_V2_GAIN_MIN, + PDM_V2_GAIN_MAX, + 0, pdm_v2_digtal_gain_tlv), + SOC_ENUM("HPF Cutoff", hpf_cutoff_enum), + SOC_SINGLE("HPFL Switch", PDM_V2_FILTER_CTRL, 22, 1, 0), + SOC_SINGLE("HPFR Switch", PDM_V2_FILTER_CTRL, 21, 1, 0), +}; + static const struct snd_soc_component_driver rockchip_pdm_v2_component = { .name = "rockchip-pdm-v2", .controls = rockchip_pdm_v2_controls, @@ -534,6 +575,7 @@ static bool rockchip_pdm_v2_volatile_reg(struct device *dev, unsigned int reg) switch (reg) { case PDM_V2_FIFO_CTRL: case PDM_V2_RXFIFO_DATA: + case PDM_V2_VERSION: return true; default: return false; @@ -553,7 +595,6 @@ static bool rockchip_pdm_v2_precious_reg(struct device *dev, unsigned int reg) static const struct reg_default rockchip_pdm_v2_reg_defaults[] = { { PDM_V2_SYSCONFIG, 0x00000002 }, { PDM_V2_CTRL, 0x001C8797 }, - { PDM_V2_FILTER_CTRL, 0x57800000 }, { PDM_V2_FIFO_CTRL, 0x0003E000 }, }; @@ -561,7 +602,7 @@ static const struct regmap_config rockchip_pdm_v2_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = PDM_V2_VERSION, + .max_register = PDM_V2_GAIN_CTRL, .reg_defaults = rockchip_pdm_v2_reg_defaults, .num_reg_defaults = ARRAY_SIZE(rockchip_pdm_v2_reg_defaults), .writeable_reg = rockchip_pdm_v2_wr_reg, @@ -572,6 +613,7 @@ static const struct regmap_config rockchip_pdm_v2_regmap_config = { }; static const struct of_device_id rockchip_pdm_v2_match[] __maybe_unused = { + { .compatible = "rockchip,rk3506-pdm", }, { .compatible = "rockchip,rk3576-pdm", }, {}, }; @@ -723,6 +765,15 @@ static int rockchip_pdm_v2_probe(struct platform_device *pdev) rockchip_pdm_v2_set_samplerate(pdm, PDM_V2_DEFAULT_RATE); rockchip_pdm_v2_rxctrl(pdm, 0); + regmap_read(pdm->regmap, PDM_V2_VERSION, &pdm->version); + /* + * The pdm version rule: + * Low 16bit is soc number. + * High 16bit is PDM release time. + * The Only soc number is changed with every chips. So use the + * release time here. + */ + pdm->version = (pdm->version >> 16) & 0xffff; /* * Set the default gain 24dB, this parameter can get better * performance if the voice energy is lower. In other words this @@ -732,8 +783,13 @@ static int rockchip_pdm_v2_probe(struct platform_device *pdev) * If you want to record stronger sound intensity, you must set * PDM gain register but not soft gain-controller. */ - regmap_update_bits(pdm->regmap, PDM_V2_FILTER_CTRL, PDM_V2_GAIN_CTRL_MSK, - PDM_V2_GAIN_24DB); + if (pdm->version == RK3506_PDM) { + regmap_update_bits(pdm->regmap, PDM_V2_GAIN_CTRL, PDM_V2_GAIN_CTRL_MSK, + PDM_V2_GAIN_CTRL_24DB); + } else if (pdm->version == RK3576_PDM) { + regmap_update_bits(pdm->regmap, PDM_V2_FILTER_CTRL, PDM_V2_GAIN_MSK, + PDM_V2_GAIN_24DB); + } ret = rockchip_pdm_v2_path_parse(pdm, node); if (ret != 0 && ret != -ENOENT) diff --git a/sound/soc/rockchip/rockchip_pdm_v2.h b/sound/soc/rockchip/rockchip_pdm_v2.h index 027dfc7460b7..30f4060d8ace 100644 --- a/sound/soc/rockchip/rockchip_pdm_v2.h +++ b/sound/soc/rockchip/rockchip_pdm_v2.h @@ -23,6 +23,7 @@ #define PDM_V2_DATA3R 0x0030 #define PDM_V2_DATA3L 0x0034 #define PDM_V2_VERSION 0x0038 +#define PDM_V2_GAIN_CTRL 0x003c #define PDM_V2_INCR_RXDR 0x0400 /* PDM_V2_SYSCONFIG */ @@ -75,8 +76,29 @@ /* PDM_V2_FILTER_CTRL */ /* 0.375dB every step. 0: mute, 1: -65.25dB, 255: 30dB */ -#define PDM_V2_GAIN_CTRL_MSK (0xff << 23) -#define PDM_V2_GAIN_CTRL_SHIFT 24 +#define PDM_V2_HPF_V2_R_MSK (0x1 << 19) +#define PDM_V2_HPF_V2_R_EN (0x1 << 19) +#define PDM_V2_HPF_V2_R_DIS (0x0 << 19) +#define PDM_V2_HPF_V2_L_MSK (0x1 << 20) +#define PDM_V2_HPF_V2_L_EN (0x1 << 20) +#define PDM_V2_HPF_V2_L_DIS (0x0 << 20) +#define PDM_V2_HPF_V2_FREQ_MSK (0xf << 21) +#define PDM_V2_HPF_V2_FREQ_0_234 (0x0 << 21) +#define PDM_V2_HPF_V2_FREQ_0_468 (0x1 << 21) +#define PDM_V2_HPF_V2_FREQ_0_937 (0x2 << 21) +#define PDM_V2_HPF_V2_FREQ_1_875 (0x3 << 21) +#define PDM_V2_HPF_V2_FREQ_3_75 (0x4 << 21) +#define PDM_V2_HPF_V2_FREQ_7_5 (0x5 << 21) +#define PDM_V2_HPF_V2_FREQ_15 (0x6 << 21) +#define PDM_V2_HPF_V2_FREQ_30 (0x7 << 21) +#define PDM_V2_HPF_V2_FREQ_60 (0x8 << 21) +#define PDM_V2_HPF_V2_FREQ_122 (0x9 << 21) +#define PDM_V2_HPF_V2_FREQ_251 (0xa << 21) +#define PDM_V2_HPF_V2_FREQ_528 (0xb << 21) +#define PDM_V2_HPF_V2_FREQ_1183 (0xc << 21) +#define PDM_V2_HPF_V2_FREQ_3152 (0xd << 21) +#define PDM_V2_GAIN_MSK (0xff << 23) +#define PDM_V2_GAIN_SHIFT 24 #define PDM_V2_GAIN_MIN 0 #define PDM_V2_GAIN_MAX 0x7f #define PDM_V2_GAIN_0DB (175 << 23) @@ -123,4 +145,12 @@ /* PDM FIFO CTRL */ #define PDM_V2_FIFO_CNT(x) (((x) >> 20) & 0xff) +/* PDM_V2_GAIN_CTRL */ +/* 0.375dB every step. 0: mute, 1: -65.25dB, 255: 30dB */ +#define PDM_V2_GAIN_CTRL_MSK (0xff << 0) +#define PDM_V2_GAIN_CTRL_SHIFT 1 +#define PDM_V2_GAIN_CTRL_MIN 0 +#define PDM_V2_GAIN_CTRL_MAX 0x7f +#define PDM_V2_GAIN_CTRL_24DB (239 << 0) + #endif From f9b44b942068fef640b525535bacc322d80d6fa5 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Tue, 25 Jun 2024 16:21:19 +0800 Subject: [PATCH 062/191] phy/rockchip: inno-dsidphy: add support rk3506 Change-Id: I128c62bb7393de6cd301e5ad159df2f1854778be Signed-off-by: Hongming Zou --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 97 ++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index bd5e57ba8054..25c02ebde0f4 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -106,6 +106,30 @@ #define VOD_MID_RANGE 0x3 #define VOD_BIG_RANGE 0x7 #define VOD_MAX_RANGE 0xf +#define RK3506_VOD_MIN_RANGE 0x8 +#define RK3506_VOD_MID_RANGE 0xc +#define RK3506_VOD_BIG_RANGE 0xe +#define RK3506_VOD_MAX_RANGE 0xf +/* Analog Register Part: reg18 */ +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) +#define LANE0_PRE_EMPHASIS_DISABLE 0 +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) +#define LANE1_PRE_EMPHASIS_DISABLE 0 +/* Analog Register Part: reg19 */ +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +/* Analog Register Part: reg1A */ +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +/* Analog Register Part: reg1B */ +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +#define PRE_EMPHASIS_MIN_RANGE 0x0 +#define PRE_EMPHASIS_MID_RANGE 0x1 +#define PRE_EMPHASIS_MAX_RANGE 0x2 +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 /* Analog Register Part: reg1E */ #define PLL_MODE_SEL_MASK GENMASK(6, 5) #define PLL_MODE_SEL_LVDS_MODE 0 @@ -208,6 +232,7 @@ enum soc_type { PX30S, RK3128, RK3368, + RK3506, RK3562, RK3568, RV1126, @@ -215,6 +240,7 @@ enum soc_type { enum phy_max_rate { MAX_1GHZ, + MAX_1_5GHZ, MAX_2_5GHZ, }; @@ -223,6 +249,7 @@ struct inno_dsidphy_plat_data { const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; const unsigned int num_timings; enum phy_max_rate max_rate; + unsigned int max_lanes; }; struct inno_dsidphy { @@ -283,6 +310,23 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { {1000, 0x0, 0x09, 0x20, 0x09, 0x27}, }; +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, +}; + static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, @@ -450,6 +494,35 @@ static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_dsidphy *inno) REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); } +static void inno_mipi_dphy_max_1_5GHz_pll_enable(struct inno_dsidphy *inno) +{ + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, + REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, + REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, + REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, + PRE_EMPHASIS_RANGE_SET_MASK, + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, + CLOCK_LANE_VOD_RANGE_SET_MASK, + CLOCK_LANE_VOD_RANGE_SET(RK3506_VOD_MAX_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, + REG_LDOPD_MASK | REG_PLLPD_MASK, + REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); +} + static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_dsidphy *inno) { /* Configure PLL */ @@ -637,6 +710,8 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) if (inno->pdata->max_rate == MAX_2_5GHZ) inno_mipi_dphy_max_2_5GHz_pll_enable(inno); + else if (inno->pdata->max_rate == MAX_1_5GHZ) + inno_mipi_dphy_max_1_5GHz_pll_enable(inno); else inno_mipi_dphy_max_1GHz_pll_enable(inno); @@ -880,6 +955,7 @@ static const struct inno_dsidphy_plat_data px30_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, }; static const struct inno_dsidphy_plat_data px30s_video_phy_plat_data = { @@ -887,6 +963,7 @@ static const struct inno_dsidphy_plat_data px30s_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static const struct inno_dsidphy_plat_data rk3128_video_phy_plat_data = { @@ -894,6 +971,7 @@ static const struct inno_dsidphy_plat_data rk3128_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, }; static const struct inno_dsidphy_plat_data rk3368_video_phy_plat_data = { @@ -901,6 +979,15 @@ static const struct inno_dsidphy_plat_data rk3368_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, +}; + +static const struct inno_dsidphy_plat_data rk3506_video_phy_plat_data = { + .soc_type = RK3506, + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), + .max_rate = MAX_1_5GHZ, + .max_lanes = 2, }; static const struct inno_dsidphy_plat_data rk3562_video_phy_plat_data = { @@ -908,6 +995,7 @@ static const struct inno_dsidphy_plat_data rk3562_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static const struct inno_dsidphy_plat_data rk3568_video_phy_plat_data = { @@ -915,6 +1003,7 @@ static const struct inno_dsidphy_plat_data rk3568_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static const struct inno_dsidphy_plat_data rv1126_video_phy_plat_data = { @@ -922,6 +1011,7 @@ static const struct inno_dsidphy_plat_data rv1126_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static int inno_dsidphy_probe(struct platform_device *pdev) @@ -993,7 +1083,9 @@ static int inno_dsidphy_probe(struct platform_device *pdev) } if (device_property_read_u32(dev, "inno,lanes", &inno->lanes)) - inno->lanes = 4; + inno->lanes = inno->pdata->max_lanes; + else if (inno->lanes > inno->pdata->max_lanes) + inno->lanes = inno->pdata->max_lanes; if (device_property_read_u32(dev, "inno,lvds-vcom", &inno->lvds_vcom)) inno->lvds_vcom = 950; @@ -1037,6 +1129,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { }, { .compatible = "rockchip,rk3368-dsi-dphy", .data = &rk3368_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3506-dsi-dphy", + .data = &rk3506_video_phy_plat_data, }, { .compatible = "rockchip,rk3562-dsi-dphy", .data = &rk3562_video_phy_plat_data, From 1e8819482b384086ed2077c9e3f2845cd09ca985 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 29 Jun 2024 10:35:33 +0800 Subject: [PATCH 063/191] drm/rockchip: vop: fix vop version to VOP_VERSION(2, 0xe) for rk3506 The version read from reg VOP_LITE_VERSION is VOP_VERSION(2, 0xc), which is the same as RV1106. But there are many differences between RV1106 vop and RK3506 vop, we set the version to VOP_VERSION(2, 0xe) on the software. Change-Id: I3f6e1e24d839aaab73b728d87cfa0738c23d540b Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index f2fdf6f65150..5de662b3433d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -2109,7 +2109,7 @@ static const struct vop_grf_ctrl rk3506_grf_ctrl = { static const struct vop_data rk3506_vop = { .soc_id = 0x3506, .vop_id = 0, - .version = VOP_VERSION(2, 0xc), + .version = VOP_VERSION(2, 0xe), .max_input = {1280, 1280}, .max_output = {1280, 1280}, .ctrl = &rk3506_ctrl_data, From e15a9b211973a969471d75e2b5ce3cd72cce7a75 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 29 Jun 2024 10:55:15 +0800 Subject: [PATCH 064/191] drm/rockchip: vop: add mcu display support for rk3506 The process of sending commands through mcu display interface in rk3506 is the same as rk3576 vop lite. Change-Id: Id2d1a072befb5f13a6073ec854dab193c318f1b4 Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 9f972b4ad46d..48f7f7c43b26 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -3144,7 +3144,7 @@ static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value) vop = to_vop(crtc); adjusted_mode = &crtc->state->adjusted_mode; - if (vop->version == VOP_VERSION(2, 0xd)) { + if (vop->version >= VOP_VERSION(2, 0xd)) { /* * 1.set mcu bypass mode timing. * 2.set dclk rate to 150M. @@ -3176,7 +3176,7 @@ static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value) } mutex_unlock(&vop->vop_lock); - if (vop->version == VOP_VERSION(2, 0xd)) { + if (vop->version >= VOP_VERSION(2, 0xd)) { /* * 1.restore mcu data mode timing. * 2.restore dclk rate to crtc_clock. @@ -3497,7 +3497,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, vop_crtc_load_lut(crtc); if (vop->mcu_timing.mcu_pix_total) { - if (vop->version == VOP_VERSION(2, 0xd)) + if (vop->version >= VOP_VERSION(2, 0xd)) vop_set_out_mode(vop, s->output_mode); else vop_set_out_mode(vop, ROCKCHIP_OUT_MODE_P888); From 006610d33d7895fdaf163870472983b27515a2fe Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sat, 22 Jun 2024 15:44:16 +0800 Subject: [PATCH 065/191] ASoC: codecs: support rk3506 acodec Change-Id: Ieaab0511bebfc0cfdda4cd4b05848adb8f87ac5c Signed-off-by: Jason Zhu --- sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rk3506_codec.c | 555 ++++++++++++++++++++++++++++++++ sound/soc/codecs/rk3506_codec.h | 380 ++++++++++++++++++++++ 4 files changed, 942 insertions(+) create mode 100644 sound/soc/codecs/rk3506_codec.c create mode 100644 sound/soc/codecs/rk3506_codec.h diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index d82aaa8afb9b..02c908c3e282 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -174,6 +174,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_RK3228 imply SND_SOC_RK3308 imply SND_SOC_RK3328 + imply SND_SOC_RK3506 imply SND_SOC_RK3528 imply SND_SOC_RK730 imply SND_SOC_RK817 @@ -1279,6 +1280,10 @@ config SND_SOC_RK3328 tristate "Rockchip RK3328 audio CODEC" select REGMAP_MMIO +config SND_SOC_RK3506 + tristate "Rockchip RK3506 audio CODEC" + select REGMAP_MMIO + config SND_SOC_RK3528 tristate "Rockchip RK3528 audio CODEC" select REGMAP_MMIO diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index a7ed3cdc885e..0360cde6b76d 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -195,6 +195,7 @@ snd-soc-rk312x-objs := rk312x_codec.o snd-soc-rk3228-objs := rk3228_codec.o snd-soc-rk3308-objs := rk3308_codec.o snd-soc-rk3328-objs := rk3328_codec.o +snd-soc-rk3506-objs := rk3506_codec.o snd-soc-rk3528-objs := rk3528_codec.o snd-soc-rk730-objs := rk730.o snd-soc-rk817-objs := rk817_codec.o @@ -569,6 +570,7 @@ obj-$(CONFIG_SND_SOC_RK312X) += snd-soc-rk312x.o obj-$(CONFIG_SND_SOC_RK3228) += snd-soc-rk3228.o obj-$(CONFIG_SND_SOC_RK3308) += snd-soc-rk3308.o obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o +obj-$(CONFIG_SND_SOC_RK3506) += snd-soc-rk3506.o obj-$(CONFIG_SND_SOC_RK3528) += snd-soc-rk3528.o obj-$(CONFIG_SND_SOC_RK730) += snd-soc-rk730.o obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o diff --git a/sound/soc/codecs/rk3506_codec.c b/sound/soc/codecs/rk3506_codec.c new file mode 100644 index 000000000000..8b36a6570b5f --- /dev/null +++ b/sound/soc/codecs/rk3506_codec.c @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * rk3506_codec.c - Rockchip RK3506 SoC Codec Driver + * + * Copyright (C) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rk3506_codec.h" + +#define CODEC_DRV_NAME "rk3506-acodec" + +#define MCLK_REFERENCE_8000 32768000 +#define MCLK_REFERENCE_11025 45158400 +#define MCLK_REFERENCE_12000 49152000 +#define MCLK_I2S_REFERENCE_DIV 4 +#define I2S_MCLK_FS 64 + +struct rk3506_codec_priv { + const struct device *plat_dev; + struct reset_control *reset; + struct regmap *regmap; + struct clk *pclk; + struct clk *mclk; + struct snd_soc_component *component; +}; + +static unsigned int samplerate_to_bit(unsigned int samplerate) +{ + switch (samplerate) { + case 8000: + case 11025: + case 12000: + return 0; + case 16000: + case 22050: + case 24000: + return 1; + case 32000: + case 44100: + case 48000: + return 2; + case 64000: + case 88200: + case 96000: + return 3; + case 128000: + case 176400: + case 192000: + return 4; + default: + return 2; + } +} + +static void rk3506_codec_power_on(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_PGA0, + PGA_PWD_MSK, PGA_PWD_EN); + snd_soc_component_update_bits(component, AUDIO_ADC_ADC0, + ADC_PWD_MSK | ADC_DEM_CTRL, ADC_PWD_EN | ADC_DEM_DWA); + udelay(10); +} + +static void rk3506_codec_power_off(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_PGA0, + PGA_PWD_MSK, PGA_PWD_DIS); + snd_soc_component_update_bits(component, AUDIO_ADC_ADC0, + ADC_PWD_MSK, ADC_PWD_DIS); +} + +static void rk3506_codec_adc_enable(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + ADC_MSK | ADC_CKE_MSK, + ADC_EN | ADC_CKE_EN); + udelay(10); +} + +static void rk3506_codec_adc_disable(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + ADC_MSK | ADC_CKE_MSK, + ADC_DIS | ADC_CKE_DIS); +} + +static void rk3506_codec_tx_start(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_TXCR2_TXCMD, + TXC_MSK | TXS_MSK, + TXC_DIS | TXS_START); + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + I2STX_MSK | I2STX_CKE_MSK, + I2STX_EN | I2STX_CKE_EN); +} + +static void rk3506_codec_tx_stop(struct snd_soc_component *component) +{ + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_TXCR2_TXCMD, + TXC_MSK | TXS_MSK, + TXC_EN | TXS_STOP); + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + I2STX_MSK | I2STX_CKE_MSK, + I2STX_DIS | I2STX_CKE_DIS); +} + +static void rk3506_codec_capture_on(struct snd_soc_component *component) +{ + rk3506_codec_adc_enable(component); + rk3506_codec_tx_start(component); + rk3506_codec_power_on(component); +} + +static void rk3506_codec_capture_off(struct snd_soc_component *component) +{ + rk3506_codec_tx_stop(component); + rk3506_codec_adc_disable(component); + rk3506_codec_power_off(component); +} + +static int rk3506_codec_reset(struct snd_soc_component *component) +{ + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + + clk_prepare_enable(rk3506->pclk); + /* Auto clear reset */ + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + SRST_MSK, SRST_EN); + udelay(10); + + /* Set parameters */ + snd_soc_component_update_bits(component, AUDIO_ADC_LDO, + ADC_IP_MSK | LDO_VSEL_MSK, ADC_IP_EN | LDO_VSEL_1_65V); + snd_soc_component_update_bits(component, AUDIO_ADC_PGA1, + PGA_CHOP_SEL_MSK, + PGA_CHOP_SEL_200K); + snd_soc_component_update_bits(component, AUDIO_ADC_HK0, + HK_VAG_BUF_MSK | HK_ADC_BUF_MSK, + HK_VAG_BUF_ON | HK_ADC_BUF_ON); + + snd_soc_component_update_bits(component, AUDIO_ADC_ADC2, + ADC_CHOP_MSK | ADC_CAPTRIM_MSK, + ADC_CHOP_OFF | ADC_CAPTRIM_100_PCT); + snd_soc_component_update_bits(component, AUDIO_ADC_AGC0, + ADC_BYPS_MSK | ADC_NG_MODE_MSK, + ADC_BYPS_EN | ADC_NG_MODE_EN); + + snd_soc_component_update_bits(component, AUDIO_ADC_HK1, + HK_VREF_1P2V_SEL_MSK, + HK_VREF_1P2V_SEL_N10M); + snd_soc_component_update_bits(component, AUDIO_ADC_PGA2, + PGA_BUF_IB_SEL_MSK | PGA_BUF_CHOP_SEL_MSK, + PGA_BUF_IB_SEL_167_PCT | PGA_BUF_CHOP_SEL_400K); + + clk_disable_unprepare(rk3506->pclk); + + return 0; +} + +static int rk3506_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_component *component = codec_dai->component; + int val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + val = I2S_SLAVE; + break; + case SND_SOC_DAIFMT_CBM_CFM: + val = I2S_MASTER; + break; + default: + return -EINVAL; + } + + /* I2S mode, MSB */ + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_CKM, + I2S_MST_MSK | SCK_MSK, + val | SCK_EN); + + return 0; +} + +static int rk3506_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + unsigned int width, rate; + int ratio; + + if ((params_rate(params) % 12000) == 0) { + clk_set_rate(rk3506->mclk, MCLK_REFERENCE_12000); + ratio = MCLK_REFERENCE_12000 / MCLK_I2S_REFERENCE_DIV / + (I2S_MCLK_FS * params_rate(params)); + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_CKM, + SCK_DIV_MSK, SCK_DIV(ratio)); + } else if ((params_rate(params) % 11025) == 0) { + clk_set_rate(rk3506->mclk, MCLK_REFERENCE_11025); + ratio = MCLK_REFERENCE_11025 / MCLK_I2S_REFERENCE_DIV / + (I2S_MCLK_FS * params_rate(params)); + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_CKM, + SCK_DIV_MSK, SCK_DIV(ratio)); + } else if ((params_rate(params) % 8000) == 0) { + clk_set_rate(rk3506->mclk, MCLK_REFERENCE_8000); + ratio = MCLK_REFERENCE_8000 / MCLK_I2S_REFERENCE_DIV / + (I2S_MCLK_FS * params_rate(params)); + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_CKM, + SCK_DIV_MSK, SCK_DIV(ratio)); + } + + udelay(10); + switch (params_rate(params)) { + case 8000: + case 11025: + case 12000: + case 64000: + case 88200: + case 96000: + case 128000: + case 176400: + case 192000: + snd_soc_component_update_bits(component, AUDIO_ADC_FILTER, + AUDIO_ADC_FILTER_MSK, + AUDIO_ADC_FILTER_MODE1); + break; + case 16000: + case 24000: + case 22050: + snd_soc_component_update_bits(component, AUDIO_ADC_FILTER, + AUDIO_ADC_FILTER_MSK, + AUDIO_ADC_FILTER_MODE3); + break; + case 32000: + case 44100: + case 48000: + snd_soc_component_update_bits(component, AUDIO_ADC_FILTER, + AUDIO_ADC_FILTER_MSK, + AUDIO_ADC_FILTER_MODE2); + break; + default: + snd_soc_component_update_bits(component, AUDIO_ADC_FILTER, + AUDIO_ADC_FILTER_MSK, + AUDIO_ADC_FILTER_MODE2); + } + + width = min(params_width(params), 24); + rate = samplerate_to_bit(params_rate(params)); + snd_soc_component_update_bits(component, AUDIO_ADC_I2S_TSD, + VDW_TX_MSK, VDW_TX(width)); + snd_soc_component_update_bits(component, AUDIO_ADC_DIGEN_CLKE, + ADCSRT_MSK, ADCSRT(rate)); + rk3506_codec_capture_on(component); + + return 0; +} + +static void rk3506_pcm_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + + rk3506_codec_capture_off(component); + regcache_cache_only(rk3506->regmap, false); + regcache_sync(rk3506->regmap); +} + +static const struct snd_soc_dai_ops rk3506_dai_ops = { + .hw_params = rk3506_hw_params, + .set_fmt = rk3506_set_dai_fmt, + .shutdown = rk3506_pcm_shutdown, + .no_capture_mute = 1, +}; + +static struct snd_soc_dai_driver rk3506_dai[] = { + { + .name = "rk3506-hifi", + .id = ACODEC_HIFI, + .capture = { + .stream_name = "HiFi Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE), + }, + .ops = &rk3506_dai_ops, + }, +}; + +static int rk3506_codec_probe(struct snd_soc_component *component) +{ + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + + rk3506->component = component; + rk3506_codec_reset(component); + regcache_cache_only(rk3506->regmap, false); + regcache_sync(rk3506->regmap); + + return 0; +} + +static void rk3506_codec_remove(struct snd_soc_component *component) +{ + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rk3506->regmap, false); + regcache_sync(rk3506->regmap); +} + +static int rk3506_codec_suspend(struct snd_soc_component *component) +{ + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rk3506->regmap, true); + clk_disable_unprepare(rk3506->mclk); + clk_disable_unprepare(rk3506->pclk); + + return 0; +} + +static int rk3506_codec_resume(struct snd_soc_component *component) +{ + struct rk3506_codec_priv *rk3506 = snd_soc_component_get_drvdata(component); + int ret = 0; + + ret = clk_prepare_enable(rk3506->pclk); + if (ret < 0) { + dev_err(rk3506->plat_dev, + "Failed to enable acodec pclk: %d\n", ret); + goto pclk_error; + } + + ret = clk_prepare_enable(rk3506->mclk); + if (ret < 0) { + dev_err(rk3506->plat_dev, + "Failed to enable acodec mclk: %d\n", ret); + goto mclk_error; + } + + regcache_cache_only(rk3506->regmap, false); + ret = regcache_sync(rk3506->regmap); + if (ret) + goto reg_error; + + return 0; +reg_error: + clk_disable_unprepare(rk3506->mclk); +mclk_error: + clk_disable_unprepare(rk3506->pclk); +pclk_error: + return ret; +} + +static const DECLARE_TLV_DB_SCALE(adc_dig_gain_tlv, -9500, 75, 0); +static const DECLARE_TLV_DB_SCALE(adc_pga_gain_tlv, 0, 300, 0); + +static const char * const adc_hpf_cutoff_text[] = { + "3.79Hz", "60Hz", "243Hz", "493Hz", +}; + +static SOC_ENUM_SINGLE_DECL(adc_hpf_cutoff_enum, AUDIO_ADC_FILTER, + 6, adc_hpf_cutoff_text); + +static const struct snd_kcontrol_new rk3506_codec_dapm_controls[] = { + SOC_ENUM("HPF Cutoff", adc_hpf_cutoff_enum), + SOC_SINGLE("HPF Switch", AUDIO_ADC_FILTER, 4, 1, 0), + SOC_SINGLE_RANGE_TLV("Digital Gain Volume", + AUDIO_ADC_VOLL, + ADCLV_SHIFT, + ADCLV_MIN, + ADCLV_MAX, + 0, adc_dig_gain_tlv), + SOC_SINGLE_RANGE_TLV("PGA Gain Volume", + AUDIO_ADC_PGA0, + PGA_GAIN_SHIFT, + PGA_GAIN_MIN, + PGA_GAIN_MAX, + 0, adc_pga_gain_tlv), + SOC_SINGLE("ADC Switch", AUDIO_ADC_AGC0, 0, 1, 0), +}; + +static const struct snd_soc_component_driver soc_codec_dev_rk3506 = { + .probe = rk3506_codec_probe, + .remove = rk3506_codec_remove, + .suspend = rk3506_codec_suspend, + .resume = rk3506_codec_resume, + .controls = rk3506_codec_dapm_controls, + .num_controls = ARRAY_SIZE(rk3506_codec_dapm_controls), +}; + +/* Set the default value or reset value */ +static const struct reg_default rk3506_codec_reg_defaults[] = { + { AUDIO_ADC_BG_LPF0, 0x3 }, +}; + +static bool rk3506_codec_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AUDIO_ADC_BG_LPF0 ... AUDIO_ADC_AGC8: + return true; + case AUDIO_ADC_FILTER ... AUDIO_ADC_I2S_TXCR2_TXCMD: + return true; + default: + return false; + } + + return true; +} + +static bool rk3506_codec_readable_reg(struct device *dev, unsigned int reg) +{ + return reg >= AUDIO_ADC_BG_LPF0; +} + +static bool rk3506_codec_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg >= AUDIO_ADC_BG_LPF0; +} + +static const struct regmap_config rk3506_codec_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = ACODEC_REG_MAX, + .writeable_reg = rk3506_codec_writeable_reg, + .readable_reg = rk3506_codec_readable_reg, + .volatile_reg = rk3506_codec_volatile_reg, + .reg_defaults = rk3506_codec_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(rk3506_codec_reg_defaults), + .cache_type = REGCACHE_FLAT, +}; + +static const struct of_device_id rk3506_codec_of_match[] = { + { .compatible = "rockchip,rk3506-codec", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, rk3506_codec_of_match); + +static int rk3506_platform_probe(struct platform_device *pdev) +{ + struct rk3506_codec_priv *rk3506; + struct resource *res; + void __iomem *base; + int ret; + + rk3506 = devm_kzalloc(&pdev->dev, sizeof(*rk3506), GFP_KERNEL); + if (!rk3506) + return -ENOMEM; + + rk3506->plat_dev = &pdev->dev; + rk3506->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "acodec"); + if (IS_ERR(rk3506->reset)) + return PTR_ERR(rk3506->reset); + + rk3506->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(rk3506->pclk)) { + dev_err(&pdev->dev, "Can't get acodec pclk\n"); + return -EINVAL; + } + + rk3506->mclk = devm_clk_get(&pdev->dev, "mclk"); + if (IS_ERR(rk3506->mclk)) { + dev_err(&pdev->dev, "Can't get acodec mclk\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(rk3506->pclk); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(rk3506->mclk); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enable acodec mclk: %d\n", ret); + goto failed_1; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + dev_err(&pdev->dev, "Failed to ioremap resource\n"); + goto failed; + } + + rk3506->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &rk3506_codec_regmap_config); + if (IS_ERR(rk3506->regmap)) { + ret = PTR_ERR(rk3506->regmap); + dev_err(&pdev->dev, "Failed to regmap mmio\n"); + goto failed; + } + + platform_set_drvdata(pdev, rk3506); + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3506, + rk3506_dai, ARRAY_SIZE(rk3506_dai)); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register codec: %d\n", ret); + goto failed; + } + + return ret; + +failed: + clk_disable_unprepare(rk3506->mclk); +failed_1: + clk_disable_unprepare(rk3506->pclk); + + return ret; +} + +static int rk3506_platform_remove(struct platform_device *pdev) +{ + struct rk3506_codec_priv *rk3506 = + (struct rk3506_codec_priv *)platform_get_drvdata(pdev); + + clk_disable_unprepare(rk3506->mclk); + clk_disable_unprepare(rk3506->pclk); + + return 0; +} + +static struct platform_driver rk3506_codec_driver = { + .driver = { + .name = CODEC_DRV_NAME, + .of_match_table = of_match_ptr(rk3506_codec_of_match), + }, + .probe = rk3506_platform_probe, + .remove = rk3506_platform_remove, +}; +module_platform_driver(rk3506_codec_driver); + +MODULE_DESCRIPTION("ASoC RK3506 Codec Driver"); +MODULE_AUTHOR("Jason Zhu "); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rk3506_codec.h b/sound/soc/codecs/rk3506_codec.h new file mode 100644 index 000000000000..709c7a6c4cf2 --- /dev/null +++ b/sound/soc/codecs/rk3506_codec.h @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * rk3506_codec.h - Rockchip RK3506 SoC Codec Driver + * + * Copyright (C) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef _RK3506_CODEC_H_ +#define _RK3506_CODEC_H_ + +#define AUDIO_ADC_BG_LPF0 0x00 +#define AUDIO_ADC_BG_LPF1 0x04 +#define AUDIO_ADC_ADC0 0x08 +#define AUDIO_ADC_ADC1 0x0c +#define AUDIO_ADC_ADC2 0x10 +#define AUDIO_ADC_PGA0 0x14 +#define AUDIO_ADC_PGA1 0x18 +#define AUDIO_ADC_PGA2 0x1c +#define AUDIO_ADC_LDO 0x20 +#define AUDIO_ADC_HK0 0x24 +#define AUDIO_ADC_HK1 0x28 +#define AUDIO_ADC_DIGEN_CLKE 0x2c +#define AUDIO_ADC_VOLL 0x30 +#define AUDIO_ADC_AGC0 0x34 +#define AUDIO_ADC_AGC1 0x38 +#define AUDIO_ADC_AGC2 0x3c +#define AUDIO_ADC_AGC3 0x40 +#define AUDIO_ADC_AGC4 0x44 +#define AUDIO_ADC_AGC5 0x48 +#define AUDIO_ADC_AGC6 0x4c +#define AUDIO_ADC_AGC7 0x50 +#define AUDIO_ADC_AGC8 0x54 +#define AUDIO_ADC_READ1 0x58 +#define AUDIO_ADC_READ2 0x5c +#define AUDIO_ADC_FILTER 0x60 +#define AUDIO_ADC_I2S_CKM 0x64 +#define AUDIO_ADC_I2S_TSD 0x68 +#define AUDIO_ADC_I2S_TXCR1 0x6c +#define AUDIO_ADC_I2S_TXCR2_TXCMD 0x70 + +#define ACODEC_REG_MAX AUDIO_ADC_I2S_TXCR2_TXCMD +#define ACODEC_HIFI 0x0 + +/* AUDIO_ADC_BG_LPF0 */ +#define LPF_PWD_MSK (0x1 << 0) +#define LPF_PWD_EN (0x0 << 0) +#define LPF_PWD_DIS (0x1 << 0) +#define LPF_CHOP_MSK (0x1 << 1) +#define LPF_CHOP_EN (0x0 << 1) +#define LPF_CHOP_DIS (0x1 << 1) +#define LPF_SW_TIME_MSK (0x1 << 2) +#define LPF_SW_TIME_124US (0x1 << 2) +#define LPF_SW_TIME_64US (0x0 << 2) +#define LPF_CLK_MSK (0x1 << 3) +#define LPF_CLK_EN (0x1 << 3) +#define LPF_CLK_DIS (0x0 << 3) +#define LPF_DELAY_TIME_MSK (0x7 << 4) +#define LPF_DELAY_TIME_2MS (0x0 << 4) +#define LPF_DELAY_TIME_4MS (0x1 << 4) +#define LPF_DELAY_TIME_8MS (0x2 << 4) +#define LPF_DELAY_TIME_16MS (0x3 << 4) +#define LPF_DELAY_TIME_32MS (0x4 << 4) +#define LPF_DELAY_TIME_64MS (0x5 << 4) +#define LPF_DELAY_TIME_128MS (0x6 << 4) +#define LPF_DELAY_TIME_256MS (0x7 << 4) + +/* AUDIO_ADC_BG_LPF1 */ +#define LPF_FORCE_BG_CHARGE_MSK (0x1 << 0) +#define LPF_FORCE_BG_CHARGE_EN (0x1 << 0) +#define LPF_FORCE_BG_CHARGE_DIS (0x1 << 0) +#define LPF_FORCE_RCFILT_MODE_MSK (0x1 << 1) +#define LPF_FORCE_RCFILT_MODE_EN (0x1 << 1) +#define LPF_FORCE_RCFILT_MODE_DIS (0x0 << 1) + +/* AUDIO_ADC_ADC0 */ +#define ADC_PWD_MSK (0x1 << 0) +#define ADC_PWD_EN (0x0 << 0) +#define ADC_PWD_DIS (0x1 << 0) +#define ADC_ZERO_MSK (0x1 << 1) +#define ADC_ZERO_EN (0x1 << 1) +#define ADC_ZERO_DIS (0x0 << 1) +#define ADC_DEM_CTRL (0x3 << 2) +#define ADC_DEM_DEFAULT (0x0 << 2) +#define ADC_DEM_DWA (0x1 << 2) +#define ADC_DEM_ONE (0x2 << 2) +#define ADC_DEM_DUAL (0x3 << 2) +#define ADC_DELAY_SARSEL_MSK (0x3 << 4) +#define ADC_DELAY_SARSEL_100_PCT (0x0 << 4) +#define ADC_DELAY_SARSEL_75_PCT (0x1 << 4) +#define ADC_DELAY_SARSEL_50_PCT (0x2 << 4) +#define ADC_DELAY_SARSEL_25_PCT (0x3 << 4) +#define ADC_DELAY_CLKSEL_MSK (0x3 << 6) +#define ADC_DELAY_CLKSEL_100_PCT (0x0 << 6) +#define ADC_DELAY_CLKSEL_75_PCT (0x1 << 6) +#define ADC_DELAY_CLKSEL_50_PCT (0x2 << 6) +#define ADC_DELAY_CLKSEL_25_PCT (0x3 << 6) + +/* AUDIO_ADC_ADC1 */ +#define ADC_IBOP1_CTRL_MSK (0x3 << 0) +#define ADC_IBOP1_50_PCT (0x0 << 0) +#define ADC_IBOP1_100_PCT (0x1 << 0) +#define ADC_IBOP1_150_PCT (0x2 << 0) +#define ADC_IBOP1_200_PCT (0x3 << 0) +#define ADC_IBOP2_INC_MSK (0x1 << 2) +#define ADC_IBOP2_INC_100_PCT (0x0 << 2) +#define ADC_IBOP2_INC_200_PCT (0x1 << 2) +#define ADC_IBOP3_INC_MSK (0x1 << 3) +#define ADC_IBOP3_INC_100_PCT (0x0 << 3) +#define ADC_IBOP3_INC_150_PCT (0x1 << 3) +#define ADC_IBCTRL_MSK (0x7 << 4) +#define ADC_IBCTRL_133_PCT (0x0 << 4) +#define ADC_IBCTRL_114_PCT (0x1 << 4) +#define ADC_IBCTRL_100_PCT (0x2 << 4) +#define ADC_IBCTRL_89_PCT (0x3 << 4) +#define ADC_IBCTRL_80_PCT (0x4 << 4) +#define ADC_IBCTRL_73_PCT (0x5 << 4) +#define ADC_IBCTRL_67_PCT (0x6 << 4) +#define ADC_IBCTRL_62_PCT (0x7 << 4) +#define ADC_STOP_RTZ_MSK (0x1 << 7) +#define ADC_STOP_RTZ_ON (0x0 << 7) +#define ADC_STOP_RTZ_OFF (0x1 << 7) + +/* AUDIO_ADC_ADC2 */ +#define ADC_CAPTRIM_MSK (0x7 << 0) +#define ADC_CAPTRIM_80_PCT (0x0 << 0) +#define ADC_CAPTRIM_90_PCT (0x1 << 0) +#define ADC_CAPTRIM_100_PCT (0x2 << 0) +#define ADC_CAPTRIM_110_PCT (0x3 << 0) +#define ADC_CAPTRIM_120_PCT (0x4 << 0) +#define ADC_CAPTRIM_130_PCT (0x5 << 0) +#define ADC_CAPTRIM_140_PCT (0x6 << 0) +#define ADC_CAPTRIM_150_PCT (0x7 << 0) +#define ADC_ELD_MSK (0x1 << 3) +#define ADC_ELD_ON (0x0 << 3) +#define ADC_ELD_OFF (0x1 << 3) +#define ADC_CHOP_MSK (0x1 << 4) +#define ADC_CHOP_ON (0x0 << 4) +#define ADC_CHOP_OFF (0x1 << 4) +#define ADC_CHOP_SEL_MSK (0x1 << 5) +#define ADC_CHOP_SEL_FS_50_PCT (0x0 << 5) +#define ADC_CHOP_SEL_FS_6_25_PCT (0x1 << 5) +#define ADC_OUT_SEL_MSK (0x1 << 6) +#define ADC_OUT_SEL_SDM (0x0 << 6) +#define ADC_OUT_SEL_6K_CLK (0x1 << 6) + +/* AUDIO_ADC_PGA0 */ +#define PGA_PWD_MSK (0x1 << 0) +#define PGA_PWD_EN (0x0 << 0) +#define PGA_PWD_DIS (0x1 << 0) +#define PGA_INPUT_DEC_MSK (0x3 << 1) +#define PGA_INPUT_DEC_N1_34DB (0x0 << 1) +#define PGA_INPUT_DEC_N4_34DB (0x1 << 1) +#define PGA_INPUT_DEC_N7_34DB (0x2 << 1) +#define PGA_INPUT_DEC_N10_34DB (0x3 << 1) +#define PGA_GAIN_SHIFT (0x3) +#define PGA_GAIN_MIN (0x0) +#define PGA_GAIN_MAX (0x1f) + +/* AUDIO_ADC_PGA1 */ +#define PGA_CHOP_SEL_MSK (0x3 << 0) +#define PGA_CHOP_SEL_NONE (0x0 << 0) +#define PGA_CHOP_SEL_200K (0x1 << 0) +#define PGA_CHOP_SEL_400K (0x2 << 0) +#define PGA_CHOP_SEL_800K (0x3 << 0) +#define PGA_IBIAS_CTRL_MSK (0x3 << 2) +#define PGA_IBIAS_100_PCT (0x0 << 2) +#define PGA_IBIAS_67_PCT (0x1 << 1) +#define PGA_IBIAS_133_PCT (0x2 << 1) +#define PGA_IBIAS_167_PCT (0x3 << 1) + +/* AUDIO_ADC_PGA2 */ +#define PGA_BUF_GAIN_MSK (0x1 << 0) +#define PGA_BUF_GAIN_0DB (0x0 << 0) +#define PGA_BUF_GAIN_6DB (0x1 << 0) +#define PGA_BUF_IB_SEL_MSK (0x3 << 1) +#define PGA_BUF_IB_SEL_100_PCT (0x0 << 1) +#define PGA_BUF_IB_SEL_67_PCT (0x1 << 1) +#define PGA_BUF_IB_SEL_133_PCT (0x2 << 1) +#define PGA_BUF_IB_SEL_167_PCT (0x3 << 1) +#define PGA_BUF_CHOP_SEL_MSK (0x3 << 3) +#define PGA_BUF_CHOP_SEL_200K (0x1 << 3) +#define PGA_BUF_CHOP_SEL_400K (0x2 << 3) +#define PGA_BUF_CHOP_SEL_800K (0x3 << 3) + +/* AUDIO_ADC_LDO */ +#define LDO_MSK (0x1 << 0) +#define LDO_EN (0x1 << 0) +#define LDO_DIS (0x0 << 0) +#define LDO_BYPASS_MSK (0x1 << 1) +#define LDO_BYPASS_ON (0x1 << 1) +#define LDO_BYPASS_OFF (0x0 << 1) +#define LDO_VSEL_MSK (0x3 << 2) +#define LDO_VSEL_1_5V (0x0 << 2) +#define LDO_VSEL_1_55V (0x1 << 2) +#define LDO_VSEL_1_6V (0x2 << 2) +#define LDO_VSEL_1_65V (0x3 << 2) +#define ADC_IP_MSK (0x1 << 7) +#define ADC_IP_EN (0x1 << 7) +#define ADC_IP_DIS (0x0 << 7) + +/* AUDIO_ADC_HK0 */ +#define HK_HALF_VAG_BUF_MSK (0x1 << 0) +#define HK_HALF_VAG_BUF_ON (0x1 << 0) +#define HK_HALF_VAG_BUF_OFF (0x0 << 0) +#define HK_HALF_ADC_BUF_MSK (0x1 << 1) +#define HK_HALF_ADC_BUF_ON (0x1 << 1) +#define HK_HALF_ADC_BUF_OFF (0x0 << 1) +#define HK_VAG_BUF_MSK (0x1 << 2) +#define HK_VAG_BUF_ON (0x1 << 2) +#define HK_VAG_BUF_OFF (0x0 << 2) +#define HK_ADC_BUF_MSK (0x1 << 3) +#define HK_ADC_BUF_ON (0x1 << 3) +#define HK_ADC_BUF_OFF (0x0 << 3) +#define HK_IBIAS_SEL_MSK (0xf << 4) +#define HK_IBIAS_SEL_200_PCT (0x8 << 4) +#define HK_IBIAS_SEL_160_PCT (0x9 << 4) +#define HK_IBIAS_SEL_133_PCT (0xa << 4) +#define HK_IBIAS_SEL_114_PCT (0xb << 4) +#define HK_IBIAS_SEL_100_PCT (0x0 << 4) +#define HK_IBIAS_SEL_80_PCT (0x1 << 4) +#define HK_IBIAS_SEL_66_PCT (0x2 << 4) +#define HK_IBIAS_SEL_36_PCT (0x7 << 4) + +/* AUDIO_ADC_HK1 */ +#define HK_VREF_1P2V_SEL_MSK (0x3 << 0) +#define HK_VREF_1P2V_SEL_NORMAL (0x0 << 0) +#define HK_VREF_1P2V_SEL_P10M (0x1 << 0) +#define HK_VREF_1P2V_SEL_N10M (0x2 << 0) +#define HK_VREF_1P2V_SEL_N20M (0x3 << 0) +#define HL_VAG_CUR_SEL_MSK (0x3 << 2) +#define HL_VAG_CUR_SEL_6UA (0x0 << 2) +#define HL_VAG_CUR_SEL_4UA (0x1 << 2) +#define HL_VAG_CUR_SEL_3UA (0x2 << 2) +#define HL_VAG_CUR_SEL_1UA (0x3 << 2) + +/* AUDIO_ADC_DIGEN_CLKE */ +#define ADCSRT_MSK (0x7 << 0) +#define ADCSRT(x) (x) +#define SRST_MSK (0x1 << 3) +#define SRST_EN (0x1 << 3) +#define SRST_DIS (0x0 << 3) +#define I2STX_MSK (0x1 << 4) +#define I2STX_EN (0x1 << 4) +#define I2STX_DIS (0x0 << 4) +#define ADC_MSK (0x1 << 5) +#define ADC_EN (0x1 << 5) +#define ADC_DIS (0x0 << 5) +#define I2STX_CKE_MSK (0x1 << 6) +#define I2STX_CKE_EN (0x1 << 6) +#define I2STX_CKE_DIS (0x0 << 6) +#define ADC_CKE_MSK (0x1 << 7) +#define ADC_CKE_EN (0x1 << 7) +#define ADC_CKE_DIS (0x0 << 7) + +/* AUDIO_ADC_VOLL */ +#define ADCLV_MSK (0xff << 0) +#define ADCLV_MIN (0x0) +#define ADCLV_MAX (0x7f) +#define ADCLV_SHIFT (0x1) + +/* AUDIO_ADC_AGC0 */ +#define ADC_AGC_MSK (0x1 << 0) +#define ADC_AGC_EN (0x1 << 0) +#define ADC_AGC_DIS (0x0 << 0) +#define ADC_NG_MODE_MSK (0x1 << 1) +#define ADC_NG_MODE_EN (0x1 << 1) +#define ADC_NG_MODE_DIS (0x0 << 1) +#define AGC_ZEROCREN_MSK (0x1 << 2) +#define AGC_ZEROCREN_EN (0x1 << 2) +#define AGC_ZEROCREN_DIS (0x0 << 2) +#define ADC_BYPS_MSK (0x1 << 3) +#define ADC_BYPS_EN (0x1 << 3) +#define ADC_BYPS_DIS (0x0 << 3) +#define ADC_AGC_OFFSET_LOW4_MSK (0xf << 4) + +/* AUDIO_ADC_AGC1 */ +#define ADC_AGC_OFFSET_HIGH4_MSK (0xf << 4) + +/* AUDIO_ADC_AGC2 */ +#define ADC_NG_RSSI_DB_LOW8_MSK (0xff << 0) + +/* AUDIO_ADC_AGC3 */ +#define ADC_NG_RSSI_DB_HIGH3_MSK (0x7 << 0) +#define ADC_NG_PGA_GAIN_MSK (0x1f << 3) + +/* AUDIO_ADC_AGC4 */ +#define ADC_TAR_DB_LOW8_MSK (0xff << 0) + +/* AUDIO_ADC_AGC5 */ +#define ADC_TAR_DB_HIGH3_MSK (0x7 << 0) +#define ADC_INI_PGA_GAIN_MSK (0x1f << 3) + +/* AUDIO_ADC_AGC6 */ +#define ADC_NG_VOL_CTRL_MSK (0xff << 0) + +/* AUDIO_ADC_AGC7 */ +#define ADC_INI_VOL_CTRL_MSK (0xff << 0) + +/* AUDIO_ADC_AGC8 */ +#define ADC_POWDET_WIN_MSK (0xf << 0) +#define ADC_PRATTRATE_WIN_MSK (0xf << 0) + +/* AUDIO_ADC_FILTER */ +#define CICCOMP_EN32_MSK (0x1 << 0) +#define CICCOMP_EN32_EN (0x1 << 0) +#define CICCOMP_EN32_DIS (0x0 << 0) +#define CICCOMP_EN64_MSK (0x1 << 1) +#define CICCOMP_EN64_EN (0x1 << 1) +#define CICCOMP_EN64_DIS (0x0 << 1) +#define CICCOMP_CF_MSK (0x3 << 2) +#define CICCOMP_CF_37_5_PCT (0x0 << 2) +#define CICCOMP_CF_75_PCT (0x1 << 2) +#define CICCOMP_CF_100_PCT (0x2 << 2) +#define HPF_MSK (0x1 << 4) +#define HPF_EN (0x1 << 4) +#define HPF_DIS (0x0 << 4) +#define HPF_CF_MSK (0x3 << 6) +#define HPF_CF_3_79HZ (0x0 << 6) +#define HPF_CF_60HZ (0x1 << 6) +#define HPF_CF_243HZ (0x2 << 6) +#define HPF_CF_493HZ (0x3 << 6) +#define AUDIO_ADC_FILTER_MSK (0xff) +#define AUDIO_ADC_FILTER_MODE1 (HPF_CF_60HZ) +#define AUDIO_ADC_FILTER_MODE2 (HPF_CF_60HZ | CICCOMP_CF_100_PCT | CICCOMP_EN32_EN) +#define AUDIO_ADC_FILTER_MODE3 (HPF_CF_60HZ | CICCOMP_CF_100_PCT | CICCOMP_EN64_EN) + +/* AUDIO_ADC_I2S_CKM */ +#define I2S_MST_MSK (0x1 << 0) +#define I2S_MASTER (0x1 << 0) +#define I2S_SLAVE (0x0 << 0) +#define SCK_P_MSK (0x1 << 1) +#define SCK_P (0x0 << 1) +#define SCK_N (0x1 << 1) +#define SCK_MSK (0x1 << 2) +#define SCK_EN (0x1 << 2) +#define SCK_DIS (0x0 << 2) +#define SCK_DIV_MSK (0xf << 4) +#define SCK_DIV(x) ((x - 1) << 4) + +/* AUDIO_ADC_I2S_TSD */ +#define TXRL_MSK (0x1 << 0) +#define TXRL_P (0x0 << 0) +#define TXRL_N (0x1 << 0) +#define SCKD_TX_MSK (0x3 << 1) +#define SCKD_TX_64 (0x0 << 1) +#define SCKD_TX_128 (0x1 << 1) +#define SCKD_TX_256 (0x2 << 1) +#define VDW_TX_MSK (0x1f << 3) +#define VDW_TX(x) ((x - 1) << 3) + +/* AUDIO_ADC_I2S_TXCR1 */ +#define LSB_TX_MSK (0x1 << 0) +#define LSB_TX_MSB (0x0 << 0) +#define LSB_TX_LSB (0x1 << 0) +#define EXRL_TX_MSK (0x1 << 1) +#define EXRL_TX_LEFT (0x0 << 1) +#define EXRL_TX_RIGHT (0x1 << 1) +#define IBM_TX_MSK (0x3 << 2) +#define IBM_TX_NORMAL (0x0 << 2) +#define IBM_TX_LEFT (0x1 << 2) +#define IBM_TX_RIGHT (0x2 << 2) +#define PDM_TX_MSK (0x3 << 4) +#define PDM_TX_NO_DELAY (0x0 << 4) +#define PDM_TX_1_DELAY (0x1 << 4) +#define PDM_TX_2_DELAY (0x2 << 4) +#define PDM_TX_3_DELAY (0x3 << 4) +#define TFS_TX_MSK (0x1 << 6) +#define TFS_TX_I2S (0x0 << 6) +#define TFS_TX_PCM (0x1 << 6) + +/* AUDIO_ADC_I2S_TXCR2_TXCMD */ +#define RCNT_TX_MSK (0x3f << 0) +#define TXC_MSK (0x1 << 6) +#define TXC_EN (0x1 << 6) +#define TXC_DIS (0x0 << 6) +#define TXS_MSK (0x1 << 7) +#define TXS_START (0x1 << 7) +#define TXS_STOP (0x0 << 7) + +#endif From 6487d8f101ff652b4796a47300dd707a38844a64 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 1 Jul 2024 22:19:31 +0800 Subject: [PATCH 066/191] mfd: rockchip-flexbus: Support RK3506 fspi mode Change-Id: I3ab60263033c0b0a650ac123c958f0665ec3b089 Signed-off-by: Jon Lin --- drivers/mfd/rockchip-flexbus.c | 4 ++-- include/linux/mfd/rockchip-flexbus.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/rockchip-flexbus.c b/drivers/mfd/rockchip-flexbus.c index 26030f8d347f..14c365446b90 100644 --- a/drivers/mfd/rockchip-flexbus.c +++ b/drivers/mfd/rockchip-flexbus.c @@ -95,9 +95,9 @@ static void rk3506_flexbus_grf_config(struct rockchip_flexbus *rkfb, bool slave_ if (slave_mode) { if ((!cpol && cpha) || (cpol && !cpha)) - val |= BIT(1); + val |= BIT(0); } else { - val |= BIT(0); + val |= BIT(1); } regmap_write(rkfb->regmap_grf, RK3506_GRF_SOC_CON1, val); } diff --git a/include/linux/mfd/rockchip-flexbus.h b/include/linux/mfd/rockchip-flexbus.h index 185702a5da41..bf6d10b74158 100644 --- a/include/linux/mfd/rockchip-flexbus.h +++ b/include/linux/mfd/rockchip-flexbus.h @@ -81,9 +81,12 @@ #define FLEXBUS_CPHA BIT(2) /* Bit fields in TX_CTL */ +#define FLEXBUS_TX_CTL_UNIT_BYTE BIT(14) #define FLEXBUS_TX_CTL_MSB BIT(13) /* Bit fields in RX_CTL */ +#define FLEXBUS_RX_CTL_FILL_DUMMY BIT(17) +#define FLEXBUS_RX_CTL_UNIT_BYTE BIT(16) #define FLEXBUS_RX_CTL_MSB BIT(15) #define FLEXBUS_AUTOPAD BIT(14) #define FLEXBUS_RXD_DY BIT(5) From 7dcfe10dc4e0dd43cbb0324eaa040c3256db0e47 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 1 Jul 2024 22:21:49 +0800 Subject: [PATCH 067/191] spi: rockchip-flexbus-fspi: Support FLEXBUS version 0x010D0844 Change-Id: Ibe3f7ce0ac25b207f66ff9712c1e4c96b7687027 Signed-off-by: Jon Lin --- drivers/spi/spi-rockchip-flexbus-fspi.c | 46 +++++++++++++++++++------ 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-rockchip-flexbus-fspi.c b/drivers/spi/spi-rockchip-flexbus-fspi.c index dc22abdba21a..44e24b5b388d 100644 --- a/drivers/spi/spi-rockchip-flexbus-fspi.c +++ b/drivers/spi/spi-rockchip-flexbus-fspi.c @@ -178,6 +178,8 @@ static int rk_flexbus_fspi_init(struct rk_flexbus_fspi *fspi) { u32 ctrl; + fspi->fb->config->grf_config(fspi->fb, false, 0, 0); + fspi->version = rockchip_flexbus_readl(fspi->fb, FLEXBUS_REVISION) >> 16; fspi->max_iosize = FLEXBUS_MAX_IOSIZE; @@ -185,7 +187,10 @@ static int rk_flexbus_fspi_init(struct rk_flexbus_fspi *fspi) rockchip_flexbus_writel(fspi->fb, FLEXBUS_DMA_SRC_LEN0, fspi->max_iosize * FLEXBUS_TX_WIDTH); rockchip_flexbus_writel(fspi->fb, FLEXBUS_DMA_DST_LEN0, fspi->max_iosize * FLEXBUS_TX_WIDTH); - ctrl = FLEXBUS_TX_CTL_MSB | (1 << FLEXBUS_DFS_SHIFT); + if (fspi->version == FLEXBUS_REVISION_V9) + ctrl = FLEXBUS_TX_CTL_MSB | fspi->fb->dfs_reg->dfs_4bit; + else + ctrl = FLEXBUS_TX_CTL_UNIT_BYTE | FLEXBUS_TX_CTL_MSB | fspi->fb->dfs_reg->dfs_1bit; rockchip_flexbus_writel(fspi->fb, FLEXBUS_TX_CTL, ctrl); /* Using internal clk as sample clock */ @@ -262,7 +267,8 @@ static int rk_flexbus_fspi_send(struct rk_flexbus_fspi *fspi, struct rk_flexbus_ } static int rk_flexbus_fspi_send_then_recv_114(struct rk_flexbus_fspi *fspi, - struct rk_flexbus_fspi_xfer *cfg) + struct rk_flexbus_fspi_xfer *cfg, + bool trick) { int ret = 0, timeout_ms = FLEXBUS_DMA_TIMEOUT_MS; u32 ctrl; @@ -279,7 +285,9 @@ static int rk_flexbus_fspi_send_then_recv_114(struct rk_flexbus_fspi *fspi, rockchip_flexbus_writel(fspi->fb, FLEXBUS_TX_CMD1, ((u32 *)fspi->tx_buf)[1]); rockchip_flexbus_writel(fspi->fb, FLEXBUS_TX_NUM, cfg->cmd_cycles); - ctrl = FLEXBUS_RXD_DY | FLEXBUS_AUTOPAD | FLEXBUS_RX_CTL_MSB | 1; + ctrl = FLEXBUS_RXD_DY | FLEXBUS_AUTOPAD | FLEXBUS_RX_CTL_MSB | fspi->fb->dfs_reg->dfs_4bit; + if (!trick) + ctrl |= FLEXBUS_RX_CTL_UNIT_BYTE | FLEXBUS_RX_CTL_FILL_DUMMY; rockchip_flexbus_writel(fspi->fb, FLEXBUS_RX_CTL, ctrl); rockchip_flexbus_writel(fspi->fb, FLEXBUS_RX_NUM, cfg->buf_cycles); @@ -307,6 +315,7 @@ static int rk_flexbus_fspi_exec_mem(struct rk_flexbus_fspi *fspi, const struct s struct rk_flexbus_fspi_xfer cfg = { 0 }; u32 cmd_cycles, data_cycles; int ret; + bool format_trick; /* format cmd_addr_dummy */ switch (op->addr.nbytes) { @@ -340,11 +349,27 @@ static int rk_flexbus_fspi_exec_mem(struct rk_flexbus_fspi *fspi, const struct s dev_err(fspi->fb->dev, "op->addr.nbytes %d not support!\n", op->addr.nbytes); return -EINVAL; } - - /* format data */ data_cycles = op->data.nbytes * 8 / op->data.buswidth; - if (op->data.buf.out) { - if (fspi->version == FLEXBUS_REVISION_V9) { + + /* + * format data: + * V9: + * rx protocol 111 send_then_recv_114(trick!), then re-format data 4-to-1(trick!) + * rx protocol 114 send_then_recv_114, then re-order data 4-to-4(trick!) + * tx protocol 111 re-format data 1-to-4, then send(114 trick!) + * New version: + * rx protocol 111 send_then_recv_114(trick!), then re-format data 4-to-1(trick!) + * rx protocol 114 send_then_recv_114 + * tx protocol 111 send(111) + */ + if ((fspi->version == FLEXBUS_REVISION_V9) || + (op->data.dir == SPI_MEM_DATA_IN && op->data.buswidth == 1)) + format_trick = true; + else + format_trick = false; + + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (format_trick) { flexbus_fspi_data_format(fspi, op->data.buf.out, 1, fspi->temp_buf, 4, data_cycles, fspi->switch_buf); dma_sync_single_for_device(fspi->fb->dev, fspi->dma_temp_buf, @@ -362,7 +387,7 @@ static int rk_flexbus_fspi_exec_mem(struct rk_flexbus_fspi *fspi, const struct s cfg.buf_addr = fspi->dma_temp_buf; if (op->data.dir == SPI_MEM_DATA_IN) - ret = rk_flexbus_fspi_send_then_recv_114(fspi, &cfg); + ret = rk_flexbus_fspi_send_then_recv_114(fspi, &cfg, format_trick); else ret = rk_flexbus_fspi_send(fspi, &cfg); if (ret) { @@ -371,11 +396,11 @@ static int rk_flexbus_fspi_exec_mem(struct rk_flexbus_fspi *fspi, const struct s return ret; } - if (op->data.buf.in) { + if (op->data.dir == SPI_MEM_DATA_IN) { if (op->data.buswidth == 4) { dma_sync_single_for_cpu(fspi->fb->dev, fspi->dma_temp_buf, op->data.nbytes, DMA_FROM_DEVICE); - if (fspi->version == FLEXBUS_REVISION_V9) + if (format_trick) flexbus_data_format_order(fspi, fspi->temp_buf, op->data.buf.in, op->data.nbytes); else @@ -387,6 +412,7 @@ static int rk_flexbus_fspi_exec_mem(struct rk_flexbus_fspi *fspi, const struct s data_cycles, fspi->switch_buf); } } + dev_dbg(fspi->fb->dev, "cmd=%x addr=%llx nbytes=%x\n", op->cmd.opcode, op->addr.val, op->data.nbytes); return ret; } From 92512bbb18f0d63024694666acbba6b060724b10 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Sat, 22 Jun 2024 15:43:08 +0800 Subject: [PATCH 068/191] phy: rockchip: inno-usb2: add usb2 phy support for rk3506 rk3506 SOC has two versions, which are rk3506g and rk3506b. They both have two otg ports and uses one USB PHY with two ports. The OTG0 port support BC1.2 detect. They are different in that rk3506g don't have vbus and id detect pin and use gpio to replace it. We use the extcon-usb-gpio.c driver to manage the interrupts. If we get the EXTCON_USB state, it means that the vbus is high and iddig is high, we enable the bvalid_phy_con to trigger bvalid interrupt. Change-Id: Iac0d0a992ee2d2f9664bea36d06f6b060a5bfb99 Signed-off-by: Jianwei Zheng --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index a2cd50df8859..e929b5a2371d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -247,6 +247,7 @@ struct rockchip_usb2phy_cfg { * @sel_pipe_phystatus: select pipe phystatus from grf. * @suspended: phy suspended flag. * @typec_vbus_det: Type-C otg vbus detect. + * @gpio_vbus_det: gpio otg vbus detect. * @utmi_avalid: utmi avalid status usage flag. * true - use avalid to get vbus status * false - use bvalid to get vbus status @@ -270,6 +271,7 @@ struct rockchip_usb2phy_cfg { * @sw: orientation switch, communicate with TCPM (Type-C Port Manager). * @port_cfg: port register configuration, assigned by driver data. * @event_nb: hold event notification callback. + * @gpio_extcon_nb: hold extcon usb gpio notification callback. * @state: define OTG enumeration states before device reset. * @mode: the dr_mode of the controller. */ @@ -282,6 +284,7 @@ struct rockchip_usb2phy_port { bool sel_pipe_phystatus; bool suspended; bool typec_vbus_det; + bool gpio_vbus_det; bool utmi_avalid; bool vbus_attached; bool vbus_always_on; @@ -302,6 +305,7 @@ struct rockchip_usb2phy_port { struct typec_switch_dev *sw; const struct rockchip_usb2phy_port_cfg *port_cfg; struct notifier_block event_nb; + struct notifier_block gpio_extcon_nb; struct wake_lock wakelock; enum usb_otg_state state; enum usb_dr_mode mode; @@ -1250,6 +1254,9 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) if (rport->port_cfg->bvalid_grf_con.enable && rport->typec_vbus_det) rport->vbus_attached = property_enabled(rphy->grf, &rport->port_cfg->bvalid_grf_con); + else if (rport->gpio_vbus_det) + rport->vbus_attached = + extcon_get_state(rphy->edev, EXTCON_USB); else if (rport->utmi_avalid) rport->vbus_attached = property_enabled(rphy->grf, &rport->port_cfg->utmi_avalid); @@ -2053,6 +2060,34 @@ static void rockchip_usb2phy_usb_bvalid_enable(struct rockchip_usb2phy_port *rpo property_enable(rphy->grf, &cfg->bvalid_grf_con, enable); } +static int rockchip_usb2phy_gpio_extcon_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct rockchip_usb2phy_port *rport = + container_of(nb, struct rockchip_usb2phy_port, gpio_extcon_nb); + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + + rockchip_usb2phy_usb_bvalid_enable(rport, + extcon_get_state(rphy->edev, EXTCON_USB)); + + return NOTIFY_DONE; +} + +static int rockchip_usb2phy_gpio_extcon_register_notifier(struct rockchip_usb2phy *rphy) +{ + struct rockchip_usb2phy_port *rport = &rphy->ports[USB2PHY_PORT_OTG]; + struct extcon_dev *edev = rphy->edev; + int ret; + + rport->gpio_extcon_nb.notifier_call = rockchip_usb2phy_gpio_extcon_notifier; + ret = devm_extcon_register_notifier(rphy->dev, edev, EXTCON_USB, + &rport->gpio_extcon_nb); + if (ret) + return ret; + + return 0; +} + static int rockchip_usb2phy_orien_sw_set(struct typec_switch_dev *sw, enum typec_orientation orien) { @@ -2183,6 +2218,9 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, rport->typec_vbus_det = of_property_read_bool(child_np, "rockchip,typec-vbus-det"); + rport->gpio_vbus_det = + of_property_read_bool(child_np, "rockchip,gpio-vbus-det"); + rport->sel_pipe_phystatus = of_property_read_bool(child_np, "rockchip,sel-pipe-phystatus"); @@ -2196,6 +2234,14 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, } } + if (rport->gpio_vbus_det) { + ret = rockchip_usb2phy_gpio_extcon_register_notifier(rphy); + if (ret) { + dev_err(rphy->dev, "failed to register gpio extcon notifier\n"); + return ret; + } + } + /* Get Vbus regulators */ rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus"); if (IS_ERR(rport->vbus)) { @@ -3838,6 +3884,92 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { + { + .reg = 0xff2b0000, + .num_ports = 2, + .vbus_detect = rockchip_usb2phy_vbus_det_control, + .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0060, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0150, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0154, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0158, 2, 2, 0, 1 }, + .bvalid_grf_sel = { 0x0060, 14, 14, 0, 1 }, + .bvalid_grf_con = { 0x0060, 15, 14, 1, 3 }, + .iddig_output = { 0x0060, 10, 10, 0, 1 }, + .iddig_en = { 0x0060, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0150, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0154, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0158, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0150, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0154, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0158, 4, 4, 0, 1 }, + .ls_det_en = { 0x0150, 0, 0, 0, 1 }, + .ls_det_st = { 0x0154, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0158, 0, 0, 0, 1 }, + .disfall_en = { 0x0150, 7, 7, 0, 1 }, + .disfall_st = { 0x0154, 7, 7, 0, 1 }, + .disfall_clr = { 0x0158, 7, 7, 0, 1 }, + .disrise_en = { 0x0150, 6, 6, 0, 1 }, + .disrise_st = { 0x0154, 6, 6, 0, 1 }, + .disrise_clr = { 0x0158, 6, 6, 0, 1 }, + .utmi_avalid = { 0x0118, 1, 1, 0, 1 }, + .utmi_bvalid = { 0x0118, 0, 0, 0, 1 }, + .utmi_iddig = { 0x0118, 6, 6, 0, 1 }, + .utmi_ls = { 0x0118, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x0118, 7, 7, 0, 1 }, + .vbus_det_en = { 0x003c, 15, 15, 1, 0 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0070, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0170, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0174, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0178, 2, 2, 0, 1 }, + .bvalid_grf_sel = { 0x0070, 14, 14, 0, 1 }, + .bvalid_grf_con = { 0x0070, 15, 14, 1, 3 }, + .iddig_output = { 0x0070, 10, 10, 0, 1 }, + .iddig_en = { 0x0070, 9, 9, 0, 1 }, + .idfall_det_en = { 0x0170, 5, 5, 0, 1 }, + .idfall_det_st = { 0x0174, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x0178, 5, 5, 0, 1 }, + .idrise_det_en = { 0x0170, 4, 4, 0, 1 }, + .idrise_det_st = { 0x0174, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x0178, 4, 4, 0, 1 }, + .ls_det_en = { 0x0170, 0, 0, 0, 1 }, + .ls_det_st = { 0x0174, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0178, 0, 0, 0, 1 }, + .disfall_en = { 0x0170, 7, 7, 0, 1 }, + .disfall_st = { 0x0174, 7, 7, 0, 1 }, + .disfall_clr = { 0x0178, 7, 7, 0, 1 }, + .disrise_en = { 0x0170, 6, 6, 0, 1 }, + .disrise_st = { 0x0174, 6, 6, 0, 1 }, + .disrise_clr = { 0x0178, 6, 6, 0, 1 }, + .utmi_avalid = { 0x0118, 9, 9, 0, 1 }, + .utmi_bvalid = { 0x0118, 8, 8, 0, 1 }, + .utmi_iddig = { 0x0118, 14, 14, 0, 1 }, + .utmi_ls = { 0x0118, 13, 12, 0, 1 }, + .utmi_hstdet = { 0x0118, 15, 15, 0, 1 }, + .vbus_det_en = { 0x043c, 15, 15, 1, 0 }, + } + }, + .chg_det = { + .chg_mode = { 0x0060, 8, 0, 0, 0x1d7 }, + .cp_det = { 0x0118, 19, 19, 0, 1 }, + .dcp_det = { 0x0118, 18, 18, 0, 1 }, + .dp_det = { 0x0118, 20, 20, 0, 1 }, + .idm_sink_en = { 0x006c, 1, 1, 0, 1 }, + .idp_sink_en = { 0x006c, 0, 0, 0, 1 }, + .idp_src_en = { 0x006c, 2, 2, 0, 1 }, + .rdm_pdwn_en = { 0x006c, 3, 3, 0, 1 }, + .vdm_src_en = { 0x006c, 5, 5, 0, 1 }, + .vdp_src_en = { 0x006c, 4, 4, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { { .reg = 0xffdf0000, @@ -4424,6 +4556,9 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { #ifdef CONFIG_CPU_RK3399 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, #endif +#ifdef CONFIG_CPU_RK3506 + { .compatible = "rockchip,rk3506-usb2phy", .data = &rk3506_phy_cfgs }, +#endif #ifdef CONFIG_CPU_RK3528 { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs }, #endif From 28c5eb68a58ca6369babcaaed850a31cb1d8dfcf Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 Jul 2024 16:14:14 +0800 Subject: [PATCH 069/191] drm/rockchip: vop: fix the dsp_h/dsp_sty calculation for rk3506 The dsp_h/dsp_sty calculation for rk3506 is the same as rk3576 vopl. The dsp_h/dest->y1 must be halved to ensure display correctly. Change-Id: Ia041489bd2795325519907b8a07f69fc1b3f0680 Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 48f7f7c43b26..ebf0e924d526 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -2119,7 +2119,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_h = 4; actual_h = dsp_h * actual_h / drm_rect_height(dest); } - if ((vop->version == VOP_VERSION(2, 2) || vop->version == VOP_VERSION(2, 0xd)) && + if ((vop->version == VOP_VERSION(2, 2) || vop->version >= VOP_VERSION(2, 0xd)) && (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)) dsp_h = dsp_h / 2; @@ -2134,7 +2134,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_stx = dest->x1 + mode->crtc_htotal - mode->crtc_hsync_start; dsp_sty = dest->y1 + mode->crtc_vtotal - mode->crtc_vsync_start; - if ((vop->version == VOP_VERSION(2, 2) || vop->version == VOP_VERSION(2, 0xd)) && + if ((vop->version == VOP_VERSION(2, 2) || vop->version >= VOP_VERSION(2, 0xd)) && (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)) dsp_sty = dest->y1 / 2 + mode->crtc_vtotal - mode->crtc_vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); From 773eba05b53c5cbe92d31635a60f46e8e2d61667 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Mon, 24 Jun 2024 09:46:51 +0800 Subject: [PATCH 070/191] mfd: rockchip-flexbus: Adjust register macro Change-Id: I8564dce3566c0afb91d5fbdedafc27468f7d4fce Signed-off-by: Wesley Yao --- include/linux/mfd/rockchip-flexbus.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/linux/mfd/rockchip-flexbus.h b/include/linux/mfd/rockchip-flexbus.h index bf6d10b74158..e2c23c7cbb25 100644 --- a/include/linux/mfd/rockchip-flexbus.h +++ b/include/linux/mfd/rockchip-flexbus.h @@ -17,10 +17,13 @@ #define FLEXBUS_DVP_CROP_SIZE 0x020 #define FLEXBUS_DVP_CROP_START 0x024 #define FLEXBUS_DVP_ORDER 0x028 +#define FLEXBUS_DVP_YUV2RGB 0x02C #define FLEXBUS_TX_CTL 0x040 #define FLEXBUS_TX_NUM 0x044 #define FLEXBUS_TXWAT_START 0x048 #define FLEXBUS_TXFIFO_DNUM 0x04C +#define FLEXBUS_TX_WIDTH 0x050 +#define FLEXBUS_TX_CSN_DUMMY 0x054 #define FLEXBUS_TX_CMD_LEN 0x058 #define FLEXBUS_TX_CMD0 0x05C #define FLEXBUS_TX_CMD1 0x060 @@ -49,8 +52,6 @@ #define FLEXBUS_RISR 0x168 #define FLEXBUS_ISR 0x16C #define FLEXBUS_ICR 0x170 -#define FLEXBUS_TESTCLK 0x190 -#define FLEXBUS_TESTDAT 0x194 #define FLEXBUS_REVISION 0x1F0 /* Bit fields in ENR */ From f32ebe049210ae805e433c8f55a8c9b37fd64a6a Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 5 Jul 2024 11:51:49 +0800 Subject: [PATCH 071/191] media: rockchip: flexbus cif fixes error of memops Signed-off-by: Zefa Chen Change-Id: I27d479a9d80ae2df788e3166d4ac2ed8f71d5fd2 --- drivers/media/platform/rockchip/flexbus_cif/capture.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/media/platform/rockchip/flexbus_cif/capture.c b/drivers/media/platform/rockchip/flexbus_cif/capture.c index 142198cf0962..18b3f7cd23dd 100644 --- a/drivers/media/platform/rockchip/flexbus_cif/capture.c +++ b/drivers/media/platform/rockchip/flexbus_cif/capture.c @@ -1174,10 +1174,7 @@ static int flexbus_cif_init_vb2_queue(struct vb2_queue *q, q->io_modes = VB2_MMAP | VB2_DMABUF; q->drv_priv = stream; q->ops = &flexbus_cif_vb2_ops; - if (stream->cif_dev->is_dma_sg_ops) - q->mem_ops = &vb2_cma_sg_memops; - else - q->mem_ops = &vb2_dma_contig_memops; + q->mem_ops = &vb2_cma_sg_memops; q->buf_struct_size = sizeof(struct flexbus_cif_buffer); q->min_buffers_needed = CIF_REQ_BUFS_MIN; q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; From 66cce2b65910a4399a4bf294a5129b37a35d3b74 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 24 Jun 2024 11:52:55 +0800 Subject: [PATCH 072/191] media: rockchip: flexbus cif add support for rk3506 Signed-off-by: Zefa Chen Change-Id: I2b299246e7392e4b27ddd5aa00d9f49ede3014cb --- .../media/platform/rockchip/flexbus_cif/capture.c | 13 ++++++++++++- drivers/media/platform/rockchip/flexbus_cif/dev.c | 12 ++++++++++-- drivers/media/platform/rockchip/flexbus_cif/dev.h | 1 + 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/rockchip/flexbus_cif/capture.c b/drivers/media/platform/rockchip/flexbus_cif/capture.c index 18b3f7cd23dd..141985f77169 100644 --- a/drivers/media/platform/rockchip/flexbus_cif/capture.c +++ b/drivers/media/platform/rockchip/flexbus_cif/capture.c @@ -1037,7 +1037,7 @@ static int flexbus_cif_stream_start(struct flexbus_cif_stream *stream) flexbus_cif_write_register(dev, FLEXBUS_SLAVE_MODE, BIT(1) | BIT(0)); val = flexbus_cif_read_register(dev, FLEXBUS_RX_CTL); val &= ~FLEXBUS_DST_WAT_LVL_MASK; - val |= FLEXBUS_DFS_8BIT; + val |= dev->fb_dev->dfs_reg->dfs_8bit; val |= FLEXBUS_CONTINUE_MODE; val |= FLEXBUS_AUTOPAD; flexbus_cif_write_register(dev, FLEXBUS_RX_CTL, val); @@ -1048,6 +1048,17 @@ static int flexbus_cif_stream_start(struct flexbus_cif_stream *stream) flexbus_cif_write_register(dev, FLEXBUS_DVP_ORDER, stream->cif_fmt_in->cif_yuv_order | stream->cif_fmt_out->cif_yuv_order); + if (dev->chip_id == RK_FLEXBUS_CIF_RK3506) { + if (stream->cif_fmt_out->fourcc == V4L2_PIX_FMT_RGB24) + flexbus_cif_write_register(dev, FLEXBUS_DVP_YUV2RGB, + CIF_YUV2RGB_ENABLE | CIF_YUV2RGB_B_LSB | CIF_YUV2RGB_BT601_FULL); + else if (stream->cif_fmt_out->fourcc == V4L2_PIX_FMT_BGR24) + flexbus_cif_write_register(dev, FLEXBUS_DVP_YUV2RGB, + CIF_YUV2RGB_ENABLE | CIF_YUV2RGB_BT601_FULL); + else + flexbus_cif_write_register(dev, FLEXBUS_DVP_YUV2RGB, 0); + } + flexbus_cif_write_register_or(dev, FLEXBUS_IMR, CIF_FIFO_OVERFLOW | CIF_BANDWIDTH_LACK | CIF_DMA_END | diff --git a/drivers/media/platform/rockchip/flexbus_cif/dev.c b/drivers/media/platform/rockchip/flexbus_cif/dev.c index bef3d4953e53..9bbd93a6aa66 100644 --- a/drivers/media/platform/rockchip/flexbus_cif/dev.c +++ b/drivers/media/platform/rockchip/flexbus_cif/dev.c @@ -513,14 +513,22 @@ static int flexbus_cif_plat_uninit(struct flexbus_cif_device *cif_dev) return 0; } -static const struct flexbus_cif_match_data cif_match_data = { +static const struct flexbus_cif_match_data rk3576_cif_match_data = { .chip_id = RK_FLEXBUS_CIF_RK3576, }; +static const struct flexbus_cif_match_data rk3506_cif_match_data = { + .chip_id = RK_FLEXBUS_CIF_RK3506, +}; + static const struct of_device_id flexbus_cif_plat_of_match[] = { { .compatible = "rockchip,flexbus-cif-rk3576", - .data = &cif_match_data, + .data = &rk3576_cif_match_data, + }, + { + .compatible = "rockchip,flexbus-cif-rk3506", + .data = &rk3506_cif_match_data, }, {}, }; diff --git a/drivers/media/platform/rockchip/flexbus_cif/dev.h b/drivers/media/platform/rockchip/flexbus_cif/dev.h index 36cffa3d0441..a818b359e4c7 100644 --- a/drivers/media/platform/rockchip/flexbus_cif/dev.h +++ b/drivers/media/platform/rockchip/flexbus_cif/dev.h @@ -82,6 +82,7 @@ enum flexbus_cif_crop_src { enum flexbus_cif_chip_id { RK_FLEXBUS_CIF_RK3576, + RK_FLEXBUS_CIF_RK3506, }; struct flexbus_cif_match_data { From 0f69a9b1be119fe6b865033952ab5ca8cd216bc4 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Fri, 5 Jul 2024 16:28:14 +0800 Subject: [PATCH 073/191] phy: rockchip: inno-usb2: Support GPIO ID detect for USB2PHY This patch register gpio id notifier to support USB2PHY to get extcon message from extcon-usb-gpio.c driver. The extcon-gpio-usb.c driver returns the state based on the ID and Vbus pin values as shown below. State | ID | VBUS ---------------------------------------- [1] USB | H | H [2] none | H | L [3] USB-HOST | L | H [4] USB-HOST | L | L There is no need to control usb bvalid when USB_HOST state is true. When USB_HOST state is true, we need to configure the iddig related registers to trigger the controller's ID interrupt and set the controller to HOST mode. When USB_HOST state is false, we need to restore the register configuration. Change-Id: Ia17fa67f5a26b2e5d989ede23ee6243cdc52f05f Signed-off-by: Jianwei Zheng Signed-off-by: William Wu --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 97 +++++++++++++++---- 1 file changed, 79 insertions(+), 18 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index e929b5a2371d..0516bff40a7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -248,6 +248,7 @@ struct rockchip_usb2phy_cfg { * @suspended: phy suspended flag. * @typec_vbus_det: Type-C otg vbus detect. * @gpio_vbus_det: gpio otg vbus detect. + * @gpio_id_det: gpio otg id detect. * @utmi_avalid: utmi avalid status usage flag. * true - use avalid to get vbus status * false - use bvalid to get vbus status @@ -271,7 +272,8 @@ struct rockchip_usb2phy_cfg { * @sw: orientation switch, communicate with TCPM (Type-C Port Manager). * @port_cfg: port register configuration, assigned by driver data. * @event_nb: hold event notification callback. - * @gpio_extcon_nb: hold extcon usb gpio notification callback. + * @gpio_vbus_nb: hold extcon usb gpio vbus notification callback. + * @gpio_id_nb: hold extcon usb gpio id notification callback. * @state: define OTG enumeration states before device reset. * @mode: the dr_mode of the controller. */ @@ -285,6 +287,7 @@ struct rockchip_usb2phy_port { bool suspended; bool typec_vbus_det; bool gpio_vbus_det; + bool gpio_id_det; bool utmi_avalid; bool vbus_attached; bool vbus_always_on; @@ -305,7 +308,8 @@ struct rockchip_usb2phy_port { struct typec_switch_dev *sw; const struct rockchip_usb2phy_port_cfg *port_cfg; struct notifier_block event_nb; - struct notifier_block gpio_extcon_nb; + struct notifier_block gpio_vbus_nb; + struct notifier_block gpio_id_nb; struct wake_lock wakelock; enum usb_otg_state state; enum usb_dr_mode mode; @@ -2060,30 +2064,84 @@ static void rockchip_usb2phy_usb_bvalid_enable(struct rockchip_usb2phy_port *rpo property_enable(rphy->grf, &cfg->bvalid_grf_con, enable); } -static int rockchip_usb2phy_gpio_extcon_notifier(struct notifier_block *nb, - unsigned long event, void *ptr) +static int rockchip_usb2phy_gpio_vbus_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) { struct rockchip_usb2phy_port *rport = - container_of(nb, struct rockchip_usb2phy_port, gpio_extcon_nb); + container_of(nb, struct rockchip_usb2phy_port, gpio_vbus_nb); struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + /* no need to control bvalid if USB_HOST state is true */ + if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) + return NOTIFY_DONE; + rockchip_usb2phy_usb_bvalid_enable(rport, extcon_get_state(rphy->edev, EXTCON_USB)); return NOTIFY_DONE; } +static int rockchip_usb2phy_gpio_id_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct rockchip_usb2phy_port *rport = + container_of(nb, struct rockchip_usb2phy_port, gpio_id_nb); + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + struct regmap *base = get_reg_base(rphy); + int state = extcon_get_state(rphy->edev, EXTCON_USB_HOST); + bool iddig_output = property_enabled(base, &rport->port_cfg->iddig_output); + bool iddig_en = property_enabled(base, &rport->port_cfg->iddig_en); + + if (state < 0) + state = 0; + + dev_dbg(rphy->dev, "gpio id extcon state: %d\n", state); + + if (iddig_en && ((state && !iddig_output) || (!state && iddig_output))) + goto out; + + if (state) { + rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0); + property_enable(base, &rport->port_cfg->iddig_output, false); + property_enable(base, &rport->port_cfg->iddig_en, true); + } else { + rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0); + property_enable(base, &rport->port_cfg->iddig_output, true); + property_enable(base, &rport->port_cfg->iddig_en, true); + } + +out: + return NOTIFY_DONE; +} + static int rockchip_usb2phy_gpio_extcon_register_notifier(struct rockchip_usb2phy *rphy) { struct rockchip_usb2phy_port *rport = &rphy->ports[USB2PHY_PORT_OTG]; struct extcon_dev *edev = rphy->edev; + struct regmap *base = get_reg_base(rphy); int ret; - rport->gpio_extcon_nb.notifier_call = rockchip_usb2phy_gpio_extcon_notifier; - ret = devm_extcon_register_notifier(rphy->dev, edev, EXTCON_USB, - &rport->gpio_extcon_nb); - if (ret) - return ret; + if (rport->gpio_vbus_det) { + rport->gpio_vbus_nb.notifier_call = rockchip_usb2phy_gpio_vbus_notifier; + ret = devm_extcon_register_notifier(rphy->dev, edev, EXTCON_USB, + &rport->gpio_vbus_nb); + if (ret) + return ret; + } + + if (rport->gpio_id_det) { + rport->gpio_id_nb.notifier_call = rockchip_usb2phy_gpio_id_notifier; + ret = devm_extcon_register_notifier(rphy->dev, edev, EXTCON_USB_HOST, + &rport->gpio_id_nb); + if (ret) + return ret; + + if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) { + rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0); + property_enable(base, &rport->port_cfg->iddig_output, false); + property_enable(base, &rport->port_cfg->iddig_en, true); + } + } return 0; } @@ -2221,6 +2279,9 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, rport->gpio_vbus_det = of_property_read_bool(child_np, "rockchip,gpio-vbus-det"); + rport->gpio_id_det = + of_property_read_bool(child_np, "rockchip,gpio-id-det"); + rport->sel_pipe_phystatus = of_property_read_bool(child_np, "rockchip,sel-pipe-phystatus"); @@ -2234,14 +2295,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, } } - if (rport->gpio_vbus_det) { - ret = rockchip_usb2phy_gpio_extcon_register_notifier(rphy); - if (ret) { - dev_err(rphy->dev, "failed to register gpio extcon notifier\n"); - return ret; - } - } - /* Get Vbus regulators */ rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus"); if (IS_ERR(rport->vbus)) { @@ -2254,6 +2307,14 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, rport->vbus = NULL; } + if (rport->gpio_vbus_det || rport->gpio_id_det) { + ret = rockchip_usb2phy_gpio_extcon_register_notifier(rphy); + if (ret) { + dev_err(rphy->dev, "failed to register gpio extcon notifier\n"); + return ret; + } + } + rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); iddig = property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig); if (rphy->edev_self && (rport->mode == USB_DR_MODE_HOST || From 6d7bf252c8fd73a294310ee4bf5418332f6f0db6 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Wed, 17 Jul 2024 11:31:30 +0800 Subject: [PATCH 074/191] dt-bindings: phy: rockchip-inno-usb2: add gpio-vbus-det and gpio-id-det property This patch adds "rockchip,gpio-vbus-det" and ""rockchip,gpio-id-det" property for otg port when using GPIO for USB vbus and id detection. Change-Id: Id3cb58aea41b6b8807b364db932f42021e2853a8 Signed-off-by: Jianwei Zheng --- .../bindings/phy/phy-rockchip-inno-usb2.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml index 18f9e0ecd9f5..d2f866253f9e 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml @@ -160,6 +160,16 @@ properties: description: when set, check the vbus status from grf con for Type-C interface. It's used when the vbusdet pin is always pulled up. + rockchip,gpio-vbus-det: + $ref: /schemas/types.yaml#/definitions/flag + description: when set, indicates that the otg port will use a gpio + for USB vbus detection. + + rockchip,gpio-id-det: + $ref: /schemas/types.yaml#/definitions/flag + description: when set, indicates that the otg port will use a gpio + for USB id detection. + rockchip,sel-pipe-phystatus: $ref: /schemas/types.yaml#/definitions/flag description: when set, select the pipe phy status from grf for usb From 279bf9a70e5138f4659d84fb01491e654480709d Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Tue, 20 Dec 2022 07:42:01 +0000 Subject: [PATCH 075/191] ARM: configs: rk3506: add rk3506_defconfig Signed-off-by: Huibin Hong Signed-off-by: Damon Ding Signed-off-by: Tao Huang Change-Id: I455bb3d3857b33c3fd35750b15b15c52a3a09130 --- arch/arm/configs/rk3506_defconfig | 226 ++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 arch/arm/configs/rk3506_defconfig diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig new file mode 100644 index 000000000000..af3133562837 --- /dev/null +++ b/arch/arm/configs/rk3506_defconfig @@ -0,0 +1,226 @@ +CONFIG_WERROR=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +CONFIG_DEFAULT_HOSTNAME="localhost" +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +# CONFIG_BASE_FULL is not set +# CONFIG_IO_URING is not set +CONFIG_EMBEDDED=y +CONFIG_ARCH_ROCKCHIP=y +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +# CONFIG_HARDEN_BRANCH_HISTORY is not set +# CONFIG_VDSO is not set +# CONFIG_CACHE_L2X0 is not set +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_SMP=y +CONFIG_VMSPLIT_3G_OPT=y +CONFIG_ARM_PSCI=y +CONFIG_HZ_300=y +CONFIG_THUMB2_KERNEL=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_ARCH_FORCE_MAX_ORDER=9 +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_CMDLINE="user_debug=31" +CONFIG_CMDLINE_EXTEND=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_ROCKCHIP_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_JUMP_LABEL=y +# CONFIG_STACKPROTECTOR_STRONG is not set +# CONFIG_STRICT_KERNEL_RWX is not set +# CONFIG_STRICT_MODULE_RWX is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_IOSCHED_BFQ=y +# CONFIG_SWAP is not set +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_CMA=y +CONFIG_CMA_INACTIVE=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_OF_PARTS is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_CORE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_STMMAC_ETH=y +# CONFIG_DWMAC_GENERIC is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_SERIAL_8250_DW=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_RK3X=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_DRM=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_ROCKCHIP_RGB=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_SII902X=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_ROCKCHIP_MULTI_RGA=m +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_PCM_TIMER is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_PROC_FS is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_ROCKCHIP=y +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y +CONFIG_SND_SIMPLE_CARD=y +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_PL330_DMA=y +CONFIG_DMABUF_HEAPS_ROCKCHIP=y +CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y +CONFIG_DMABUF_RK_HEAPS_DEBUG=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_CPU_RK3506=y +CONFIG_ROCKCHIP_PVTM=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_IIO=y +CONFIG_ROCKCHIP_SARADC=y +CONFIG_PWM=y +CONFIG_PWM_ROCKCHIP=y +# CONFIG_NVMEM_SYSFS is not set +CONFIG_NVMEM_ROCKCHIP_OTP=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_ZLIB is not set +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_MISC is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_FS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SCHED_DEBUG is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set From 3a0515b9afea0c06b8ddd6566cc9c5730b1d9670 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 24 May 2024 15:43:22 +0800 Subject: [PATCH 076/191] ARM: rk3506_defconfig: Enable SPI Nand support Change-Id: Ib75006a6dc1feb8f1c54d08bc4c7e7ab8e931fc4 Signed-off-by: Jon Lin --- arch/arm/configs/rk3506_defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index af3133562837..9eaba1716ec8 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -76,6 +76,12 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_OF_PARTS is not set +CONFIG_MTD_BLOCK=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_MISC=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y CONFIG_NETDEVICES=y # CONFIG_NET_CORE is not set # CONFIG_NET_VENDOR_ALACRITECH is not set @@ -131,6 +137,8 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_RK3X=y +CONFIG_SPI=y +CONFIG_SPI_ROCKCHIP_SFC=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y @@ -203,7 +211,9 @@ CONFIG_NVMEM_ROCKCHIP_OTP=y # CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_DECOMP_MULTI=y # CONFIG_SQUASHFS_ZLIB is not set CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y From d6ca723ac92e95b448fd5d8055daea6b54956813 Mon Sep 17 00:00:00 2001 From: Hans Yang Date: Wed, 26 Jun 2024 16:18:39 +0800 Subject: [PATCH 077/191] ARM: rk3506_defconfig: add configs for drm and adb Change-Id: I7f1f2790e4b9b6b46caf1729f0c660ae57b77752 Signed-off-by: Hans Yang --- arch/arm/configs/rk3506_defconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 9eaba1716ec8..4600f755850f 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -163,6 +163,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_DRM=y +CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_ROCKCHIP=y CONFIG_ROCKCHIP_RGB=y CONFIG_DRM_PANEL_SIMPLE=y @@ -181,7 +182,9 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SIMPLE_CARD=y -# CONFIG_USB_SUPPORT is not set +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_FS=y CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y @@ -218,7 +221,6 @@ CONFIG_SQUASHFS_DECOMP_MULTI=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y # CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set # CONFIG_XZ_DEC_IA64 is not set From 67413649cd4b1565f58a0abef18adba56c320392 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Thu, 27 Jun 2024 16:33:43 +0800 Subject: [PATCH 078/191] ARM: rk3506_defconfig: enable CONFIG_SND_SOC_ROCKCHIP_PDM_V2 Change-Id: Ib19b3af705d025d5a4fd56207f563bd3103345fd Signed-off-by: Jason Zhu --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 4600f755850f..52700bcb86a9 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -181,6 +181,7 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y +CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y From 2266ce5d46c72e76eb1776e48fadea7541749243 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 28 Jun 2024 15:50:56 +0800 Subject: [PATCH 079/191] ARM: rk3506_defconfig: Enable CONFIG_ROCKCHIP_CPUINFO Change-Id: I526f32818e194074aa1dcafb9c42ea3cc5ad8d45 Signed-off-by: Finley Xiao --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 52700bcb86a9..12e1adcd9913 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -198,6 +198,7 @@ CONFIG_STAGING=y # CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_CPU_RK3506=y +CONFIG_ROCKCHIP_CPUINFO=y CONFIG_ROCKCHIP_PVTM=y CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y From 6f3fe0486f25a48e539874a3c75e27c49301846e Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Fri, 28 Jun 2024 14:31:43 +0800 Subject: [PATCH 080/191] ARM: rk3506_defconfig: Enable CONFIG_DEBUG_USER before: text data bss dec hex filename 3605674 1582076 97992 5285742 50a76e vmlinux after: text data bss dec hex filename 3606058 1582340 97992 5286390 50a9f6 vmlinux Change-Id: I34defe68829b16fcce24477137eed6b8bd92b4cc Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 12e1adcd9913..f6214005b281 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -237,4 +237,5 @@ CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From 37df3b45c59dd37df0b7f71f737d7478b951d456 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Fri, 28 Jun 2024 15:40:54 +0800 Subject: [PATCH 081/191] ARM: rk3506_defconfig: Enable Dwc2 Config Change-Id: Ic2b42cccc09781816624e84fffd8266f86cd2dd5 Signed-off-by: Jianwei Zheng --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index f6214005b281..a01188a4021c 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -183,6 +183,8 @@ CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SIMPLE_CARD=y +CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_F_FS=y From ea489c07b847d811b06defba06b1c74dfd8fa050 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 28 Jun 2024 15:57:35 +0800 Subject: [PATCH 082/191] ARM: rk3506_defconfig: Enable CONFIG_NVMEM_SYSFS Change-Id: Id0d8b371f80a054006b7283f24ecd7362bc28b46 Signed-off-by: Finley Xiao --- arch/arm/configs/rk3506_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index a01188a4021c..edb1e3e62844 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -213,7 +213,6 @@ CONFIG_IIO=y CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y -# CONFIG_NVMEM_SYSFS is not set CONFIG_NVMEM_ROCKCHIP_OTP=y # CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set From 74f01566e7de55f2178fb1f28009fb952dded0a6 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 28 Jun 2024 16:20:29 +0800 Subject: [PATCH 083/191] ARM: configs: rk3506: Enable CONFIG_SND_SOC_ROCKCHIP_SAI Signed-off-by: Sugar Zhang Change-Id: I64cb6cf6990bc0c4e2b4dfd67237c4beb5522289 --- arch/arm/configs/rk3506_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index edb1e3e62844..a94a78417775 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -175,13 +175,12 @@ CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_PCM_TIMER is not set # CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_PROC_FS is not set # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y -CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y +CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y CONFIG_USB_DWC2=y From 83e8a1b4520b8fdb23d83432c84457aeee18d4d6 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Fri, 28 Jun 2024 17:26:45 +0800 Subject: [PATCH 084/191] ARM: rk3506_defconfig: Enable CONFIG_ROCKCHIP_OPP and CONFIG_ROCKCHIP_SYSTEM_MONITOR Signed-off-by: Liang Chen Change-Id: I47dfdcd621758fd2fbcc8405428d23efc7d7fc1c --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index a94a78417775..6454c6ddeb1b 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -200,7 +200,9 @@ CONFIG_STAGING=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_CPU_RK3506=y CONFIG_ROCKCHIP_CPUINFO=y +CONFIG_ROCKCHIP_OPP=y CONFIG_ROCKCHIP_PVTM=y +CONFIG_ROCKCHIP_SYSTEM_MONITOR=y CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y From 7f8e70119087d4849a11424f62914f557ad08ee1 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Fri, 28 Jun 2024 20:06:43 +0800 Subject: [PATCH 085/191] ARM: rk3506_defconfig: Enable CONFIG_USB_CONFIGFS_UEVENT Change-Id: Iae360bbda69398bc25420210d4e8ff732f6da713 Signed-off-by: Jianwei Zheng --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 6454c6ddeb1b..47bcea213d04 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -186,6 +186,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y From ee0511654542868cf4cce4e027669d26fecf1f31 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 28 Jun 2024 18:00:17 +0800 Subject: [PATCH 086/191] ARM: configs: rk3506: Enable CONFIG_SND_SOC_ES8323 Support rk3506-evb1. Signed-off-by: Sugar Zhang Change-Id: I1ebf212f696c598c075bc0398762217995ec021d --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 47bcea213d04..d0e1d6a6fe15 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -181,6 +181,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SOC_ROCKCHIP_SAI=y +CONFIG_SND_SOC_ES8323=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y CONFIG_USB_DWC2=y From 303066417a667898b699c833111926daa233f6cb Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 28 Jun 2024 18:49:01 +0800 Subject: [PATCH 087/191] ARM: configs: rk3506: Enable CONFIG_SND_SOC_ROCKCHIP_MULTICODEC Support rk3506-evb1. CONFIG_SND_SOC_ROCKCHIP_MULTICODEC sepends on INPUT and EXTCON. Signed-off-by: Sugar Zhang Change-Id: Id5516a3c5f829d7d443a4642ead95897f3e65f4d --- arch/arm/configs/rk3506_defconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index d0e1d6a6fe15..faa86c1a3526 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -123,7 +123,8 @@ CONFIG_STMMAC_ETH=y # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set # CONFIG_WLAN is not set -# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set @@ -181,8 +182,11 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SOC_ROCKCHIP_SAI=y +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_ES8323=y CONFIG_SND_SIMPLE_CARD=y +# CONFIG_HID is not set +# CONFIG_USB_HID is not set CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y @@ -212,6 +216,7 @@ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_EXTCON=y CONFIG_IIO=y CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y From 731537d01c9895b7fcb0f4dad85936ad583efa0a Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sat, 29 Jun 2024 15:04:01 +0800 Subject: [PATCH 088/191] ARM: rk3506_defconfig: Enable CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER Change-Id: I6456368bce4cb20577499526f216a46065d0bebe Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index faa86c1a3526..af6214bb917b 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -239,6 +239,7 @@ CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=0 CONFIG_PRINTK_TIME=y +CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y # CONFIG_DEBUG_MISC is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_DEBUG_FS=y From 03303807876e02f92f6d4b60a6a5a3a878f01aca Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sat, 29 Jun 2024 15:09:28 +0800 Subject: [PATCH 089/191] ARM: rk3506_defconfig: Enable CONFIG_RK_CONSOLE_THREAD Change-Id: Ic9373ca567ddc67e38717d97eb4391f124904306 Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index af6214bb917b..ee70ae2a9cd0 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -213,6 +213,7 @@ CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_RK_CONSOLE_THREAD=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y From 0a6aeabe92da10adf32558f6c69cfb848c746437 Mon Sep 17 00:00:00 2001 From: David Wu Date: Sat, 29 Jun 2024 15:18:23 +0800 Subject: [PATCH 090/191] ARM: rk3506_defconfig: Enable network configs Enable following network config: - Enable Bridge function - Enable ptp1588 function - Enable motorcomm PHY for Rk3506 Change-Id: I167fd678c23ffef9905c5cb655473056f31b754f Signed-off-by: David Wu --- arch/arm/configs/rk3506_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index ee70ae2a9cd0..17c0d08a151d 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -69,6 +69,8 @@ CONFIG_UNIX=y CONFIG_INET=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -122,6 +124,8 @@ CONFIG_STMMAC_ETH=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set +CONFIG_MOTORCOMM_PHY=y +CONFIG_PPP=y # CONFIG_WLAN is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -140,7 +144,7 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_RK3X=y CONFIG_SPI=y CONFIG_SPI_ROCKCHIP_SFC=y -# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PTP_1588_CLOCK_KVM is not set CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_SYSCON_REBOOT_MODE=y From 57ddc871e37ea33079c3eacb249f2e1f06d39998 Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Fri, 28 Jun 2024 18:20:21 +0800 Subject: [PATCH 091/191] ARM: rk3506_defconfig: enable adc and gpio keys Support rk3506-evb1. Change-Id: I8fdaaad06f2efdfed5477a716c29d962e2b2f088 Signed-off-by: Zain Wang --- arch/arm/configs/rk3506_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 17c0d08a151d..08a4b6cb757a 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -127,7 +127,10 @@ CONFIG_STMMAC_ETH=y CONFIG_MOTORCOMM_PHY=y CONFIG_PPP=y # CONFIG_WLAN is not set -# CONFIG_INPUT_KEYBOARD is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set From b1cb36da7faedc95c4a3e818820ecdeef1f0b9a8 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sat, 29 Jun 2024 17:15:18 +0800 Subject: [PATCH 092/191] ARM: rk3506_defconfig: Enable mipi dsi configs Change-Id: Ia7e2d0d20c2ad5d34efb480d4273c58038dab961 Signed-off-by: Hongming Zou --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 08a4b6cb757a..1ffcba9cf462 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -173,6 +173,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_DRM=y CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_ROCKCHIP=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y CONFIG_ROCKCHIP_RGB=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_SII902X=y @@ -229,6 +230,7 @@ CONFIG_IIO=y CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_NVMEM_ROCKCHIP_OTP=y # CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set From 367eaa8175e4060c820e867fa267e5b574f70d27 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sun, 30 Jun 2024 12:07:11 +0800 Subject: [PATCH 093/191] ARM: rk3506_defconfig: Enable gt1x configs Support rk3506-evb1. Change-Id: I650d9bc78545451323cdfdcc30e8e944aaf47cce Signed-off-by: Hongming Zou --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 1ffcba9cf462..511ce7f11755 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -132,6 +132,8 @@ CONFIG_KEYBOARD_ADC=y # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GT1X=y # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set From 90145d0aae6a75f3c163d60a3a07041cdd290601 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Sat, 29 Jun 2024 14:59:51 +0800 Subject: [PATCH 094/191] ARM: rk3506_defconfig: Enable CONFIG_ROCKCHIP_MULTI_RGA=y Change-Id: I885938901cc3f7d9dfa1c659942273a256939a6d Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 511ce7f11755..04583399aa8e 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -181,7 +181,7 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_SII902X=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y -CONFIG_ROCKCHIP_MULTI_RGA=m +CONFIG_ROCKCHIP_MULTI_RGA=y CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_PCM_TIMER is not set From 3a7d96999d299fd47529257fcc2dd144b5743392 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 1 Jul 2024 10:17:31 +0800 Subject: [PATCH 095/191] ARM: rk3506_defconfig: Enable mmc driver Signed-off-by: Shawn Lin Change-Id: I778399b65f8b107aa464e444451b233a56cf8931 --- arch/arm/configs/rk3506_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 04583399aa8e..f4bc8554d7f6 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -203,6 +203,9 @@ CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_MMC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y From 9128c127db605e2f4b1f18dc6c2461f00b84d77b Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 1 Jul 2024 14:38:45 +0800 Subject: [PATCH 096/191] ARM: rk3506_defconfig: Enable CONFIG_EFI_PARTITION Signed-off-by: Shawn Lin Change-Id: I31679b48be13ab0e4fdbe2d9ca2dd4c0b5846592 --- arch/arm/configs/rk3506_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index f4bc8554d7f6..2a7865ad2e71 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -54,7 +54,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y # CONFIG_MSDOS_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_CMDLINE_PARTITION=y CONFIG_IOSCHED_BFQ=y # CONFIG_SWAP is not set From c0f96c2a0c59bceac252332baa91727ab7186dc6 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Mon, 1 Jul 2024 15:37:59 +0800 Subject: [PATCH 097/191] ARM: rk3506_defconfig: Disable CONFIG_DMABUF_HEAPS_ROCKCHIP Change-Id: I701f49c841b66cdbfb7665c7d50312c288226b5a Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 2a7865ad2e71..9ce6b28b067c 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -208,9 +208,6 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y -CONFIG_DMABUF_HEAPS_ROCKCHIP=y -CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y -CONFIG_DMABUF_RK_HEAPS_DEBUG=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set CONFIG_STAGING=y From 54dd3d03da256a01d44b28c419a3fac364ef5a8b Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sat, 29 Jun 2024 17:19:37 +0800 Subject: [PATCH 098/191] ARM: rk3506_defconfig: enable CONFIG_SND_SOC_DUMMY_CODEC Open it for pdm sound card. Change-Id: Ia414f89ca662df2dda5dfa3bc975c9626e5a7402 Signed-off-by: Jason Zhu --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 9ce6b28b067c..9d95a71a1776 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -192,6 +192,7 @@ CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y +CONFIG_SND_SOC_DUMMY_CODEC=y CONFIG_SND_SOC_ES8323=y CONFIG_SND_SIMPLE_CARD=y # CONFIG_HID is not set From 4ee43166c60d897aa16222494dbaf43ebcc92dff Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Mon, 1 Jul 2024 16:53:42 +0800 Subject: [PATCH 099/191] ARM: rk3506_defconfig: enable CONFIG_SND_SOC_RK_DSM Change-Id: Id3e302ef4572b561798e80decd054b228237dd80 Signed-off-by: Jason Zhu --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 9d95a71a1776..d49dc0d0143e 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -194,6 +194,7 @@ CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_DUMMY_CODEC=y CONFIG_SND_SOC_ES8323=y +CONFIG_SND_SOC_RK_DSM=y CONFIG_SND_SIMPLE_CARD=y # CONFIG_HID is not set # CONFIG_USB_HID is not set From bd875c85073fd747bafa7a7c6a6fc5f0db06017e Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sat, 29 Jun 2024 16:36:41 +0800 Subject: [PATCH 100/191] ARM: rk3506_defconfig: enable rk3506 codec Change-Id: Iad076443dfb50aed211b42b6e731ca87bdc5d3b9 Signed-off-by: Jason Zhu --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index d49dc0d0143e..2d4ec27e269c 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -194,6 +194,7 @@ CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_DUMMY_CODEC=y CONFIG_SND_SOC_ES8323=y +CONFIG_SND_SOC_RK3506=y CONFIG_SND_SOC_RK_DSM=y CONFIG_SND_SIMPLE_CARD=y # CONFIG_HID is not set From fb812d6e92c271e50eda3c397a9bd697d510d37c Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 1 Jul 2024 09:07:18 +0800 Subject: [PATCH 101/191] ARM: configs: rk3506: Enable CONFIG_I2C_GPIO Used for rk3506g-test1 Signed-off-by: Sugar Zhang Change-Id: I15ccd37fb424e863ab5bf352285318bfb3d71f35 --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 2d4ec27e269c..8d29fce4521b 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -145,6 +145,7 @@ CONFIG_SERIAL_8250_DW=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y CONFIG_I2C_RK3X=y CONFIG_SPI=y CONFIG_SPI_ROCKCHIP_SFC=y From 57955fbb7098652cd2f880e7e254ba947e2676aa Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Mon, 1 Jul 2024 19:37:19 +0800 Subject: [PATCH 102/191] ARM: configs: rk3506: Enable CONFIG_SND_SOC_SPDIF Used for rk3506g-test1 Signed-off-by: Sugar Zhang Change-Id: Iaa7cd96447a852666bba166cce744fd2bf2a467d --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 8d29fce4521b..e7d1b07874ca 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -192,6 +192,8 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SOC_ROCKCHIP_SAI=y +CONFIG_SND_SOC_ROCKCHIP_SPDIF=y +CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_DUMMY_CODEC=y CONFIG_SND_SOC_ES8323=y From e1be39630cde2a59a9562a541a5a90ee72e3d406 Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Tue, 2 Jul 2024 15:44:55 +0800 Subject: [PATCH 103/191] ARM: rk3506_defconfig: enable CONFIG_FILE_LOCKING Change-Id: I6918dc1db5eb78d5840f2fcdb390eecd7e7ab727 Signed-off-by: Zain Wang --- arch/arm/configs/rk3506_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index e7d1b07874ca..7455a6bff5b5 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -239,7 +239,6 @@ CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_NVMEM_ROCKCHIP_OTP=y -# CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set CONFIG_TMPFS=y CONFIG_UBIFS_FS=y From 631aa944f6f5a1ba33a2c264d2dac6a867842e86 Mon Sep 17 00:00:00 2001 From: Simon Xue Date: Tue, 2 Jul 2024 16:46:32 +0800 Subject: [PATCH 104/191] ARM: configs: rk3506: enable CONFIG_DMABUF_HEAPS_CMA Change-Id: If504ab434c9304c8562b24c5259aad4279626793 Signed-off-by: Simon Xue --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 7455a6bff5b5..d7616bb74bf0 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -214,6 +214,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set CONFIG_STAGING=y From 77e316580f5995f8207f00d87ee28fd0758a8ddf Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Tue, 2 Jul 2024 16:02:31 +0800 Subject: [PATCH 105/191] ARM: rk3506_defconfig: enable usb storage function Change-Id: I387c287c496ff19ef9143859e5d2a7294c8f1f21 Signed-off-by: Zain Wang --- arch/arm/configs/rk3506_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index d7616bb74bf0..2afa9fcc0fde 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -83,6 +83,11 @@ CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_MISC=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BLOCK=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y # CONFIG_NET_CORE is not set # CONFIG_NET_VENDOR_ALACRITECH is not set @@ -203,6 +208,7 @@ CONFIG_SND_SIMPLE_CARD=y # CONFIG_HID is not set # CONFIG_USB_HID is not set CONFIG_USB=y +CONFIG_USB_STORAGE=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y From 30922213a453dcbac19acc0d0c13114159686642 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Sat, 29 Jun 2024 17:36:20 +0800 Subject: [PATCH 106/191] ARM: rk3506_defconfig: Enable usb extcon and phy configs 1. Enable CONFIG_EXTCON_USB_GPIO 2. Enable CONFIG_PHY_ROCKCHIP_INNO_USB2 Change-Id: I6876fd1a39ec9004db8a4e846d643d5a9329052c Signed-off-by: Jianwei Zheng Signed-off-by: William Wu --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 2afa9fcc0fde..e0bee32b72d3 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -241,10 +241,12 @@ CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y CONFIG_IIO=y CONFIG_ROCKCHIP_SARADC=y CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_NVMEM_ROCKCHIP_OTP=y # CONFIG_DNOTIFY is not set From 48cc1eb96aebf36e23bd73f039c15a6af40c0fbb Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 3 Jul 2024 19:51:33 +0800 Subject: [PATCH 107/191] ARM: configs: rk3506: enable some debug functions Sysrq,hardlock,softlock,hangtask, rockchip debug and so on. Change-Id: I2dae33d74636be660a660eee472717fdd8376cdf Signed-off-by: Huibin Hong --- arch/arm/configs/rk3506_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index e0bee32b72d3..0d9eb728c49f 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -237,6 +237,7 @@ CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y CONFIG_RK_CONSOLE_THREAD=y +CONFIG_ROCKCHIP_DEBUG=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y @@ -268,10 +269,18 @@ CONFIG_PRINTK_TIME=y CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y # CONFIG_DEBUG_MISC is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAGIC_SYSRQ_SERIAL is not set CONFIG_DEBUG_FS=y # CONFIG_SLUB_DEBUG is not set +CONFIG_PANIC_ON_OOPS=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y +# CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_BOOTPARAM_RCU_STALL_PANIC=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y # CONFIG_RUNTIME_TESTING_MENU is not set From c3e90d4479e58f31e84f51614d3b6fccd9932664 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Thu, 4 Jul 2024 11:46:30 +0800 Subject: [PATCH 108/191] ARM: configs: rk3506: enable PSTORE Change-Id: Ice456470a9c54b4182076c01111d2639448ac714 Signed-off-by: Huibin Hong --- arch/arm/configs/rk3506_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 0d9eb728c49f..8f4cc88f48f7 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -258,6 +258,11 @@ CONFIG_SQUASHFS_DECOMP_MULTI=y # CONFIG_SQUASHFS_ZLIB is not set CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_DEFLATE_COMPRESS is not set +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_BOOT_LOG=y # CONFIG_NETWORK_FILESYSTEMS is not set # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set From 35a002e1bafbc2251a86ced8808f7421247a338b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 2 Jul 2024 21:46:49 +0800 Subject: [PATCH 109/191] ARM: configs: rk3506: Enable CONFIGS_SND_SOC_DYNAMIC_DMA_CHAN Use dynamic dma chan request for audio, if prefer static dma chan request, disabled it. Signed-off-by: Sugar Zhang Change-Id: I3f5dc20343a70e771715ad19a348a64b3c7ba68e --- arch/arm/configs/rk3506_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 8f4cc88f48f7..9b8e7d6f9ecd 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -194,6 +194,7 @@ CONFIG_SND=y # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set CONFIG_SND_SOC=y +CONFIG_SND_SOC_DYNAMIC_DMA_CHAN=y CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y CONFIG_SND_SOC_ROCKCHIP_SAI=y From 97d4e5f0ff734764a3ac7b1d4a1031346af67c6c Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Mon, 15 Jul 2024 15:22:52 +0800 Subject: [PATCH 110/191] ARM: rk3506_defconfig: enable es7202 for pdm Used for rk3506g-test1 Change-Id: I2ef5a0dbea485aa0c9734e37b7aaa08588d37b68 Signed-off-by: Jason Zhu --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 9b8e7d6f9ecd..245a3abaff77 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -202,6 +202,8 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y CONFIG_SND_SOC_DUMMY_CODEC=y +CONFIG_SND_SOC_ES7202=y +CONFIG_SND_SOC_ES7202_MIC_MAX_CHANNELS=8 CONFIG_SND_SOC_ES8323=y CONFIG_SND_SOC_RK3506=y CONFIG_SND_SOC_RK_DSM=y From 9a50a94ac5c57b7aea354a12a1efbb1b0cc542c6 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 17 Jul 2024 10:36:16 +0800 Subject: [PATCH 111/191] ARM: rk3506_defconfig: Enable fiq debugger Signed-off-by: Joseph Chen Change-Id: Ie19bfe3e105ea01c87998c0a8fd3e7584e8c0dec --- arch/arm/configs/rk3506_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index 245a3abaff77..b9fc803913c9 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -74,6 +74,7 @@ CONFIG_BRIDGE=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_ROCKCHIP_SIP=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_OF_PARTS is not set @@ -239,6 +240,7 @@ CONFIG_FIQ_DEBUGGER=y CONFIG_FIQ_DEBUGGER_NO_SLEEP=y CONFIG_FIQ_DEBUGGER_CONSOLE=y CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y CONFIG_RK_CONSOLE_THREAD=y CONFIG_ROCKCHIP_DEBUG=y CONFIG_PM_DEVFREQ=y From 52a48c116654cdbaa2f1b1dea9ba4a1761b9363b Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Tue, 20 Dec 2022 07:43:22 +0000 Subject: [PATCH 112/191] ARM: dts: rockchip: Add core dtsi for rk3506 Signed-off-by: Huibin Hong Signed-off-by: Damon Ding Signed-off-by: Finley Xiao Signed-off-by: Tao Huang Change-Id: Ib44908bb445f9365d68f6391fe25f447c0c67cf5 --- arch/arm/boot/dts/rk3506.dtsi | 302 ++++++++++++++++++++++++++++++++++ 1 file changed, 302 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506.dtsi diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi new file mode 100644 index 000000000000..ae5b786f5ddf --- /dev/null +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rk3506"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + clocks { + compatible = "simple-bus"; + + clk_rc: clk-rc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000>; + clock-output-names = "clk_rc"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + uart0: serial@ff0a0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0a0000 0x100>; + interrupts = ; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm1_8ch_0: pwm@ff170000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff170000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_1: pwm@ff171000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff171000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_2: pwm@ff172000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff172000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_3: pwm@ff173000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff173000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_4: pwm@ff174000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff174000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_5: pwm@ff175000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff175000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_6: pwm@ff176000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff176000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_8ch_7: pwm@ff177000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff177000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + grf: syscon@ff288000 { + compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; + reg = <0xff288000 0x4000>; + + rgb: rgb { + compatible = "rockchip,rk3506-rgb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; + }; + }; + }; + + gic: interrupt-controller@ff581000 { + compatible = "arm,gic-400"; + reg = <0xff581000 0x1000>, + <0xff582000 0x2000>, + <0xff584000 0x2000>, + <0xff586000 0x2000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; + }; + + vop: vop@ff600000 { + compatible = "rockchip,rk3506-vop"; + reg = <0xff600000 0x200>; + reg-names = "regs"; + rockchip,grf = <&grf>; + interrupts = ; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vop>; + }; + }; + }; + + arm-debug@ff810000 { + compatible = "rockchip,debug"; + reg = <0xff810000 0x1000>, + <0xff812000 0x1000>, + <0xff814000 0x1000>; + }; + + pwm0_4ch_0: pwm@ff930000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff930000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_1: pwm@ff931000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff931000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_2: pwm@ff932000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff932000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_4ch_3: pwm@ff933000 { + compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; + reg = <0xff933000 0x200>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + #pwm-cells = <3>; + status = "disabled"; + }; + + cru: clock-controller@ff9a0000 { + compatible = "rockchip,rk3506-cru"; + reg = <0xff9a0000 0x20000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; From 140d584900b623c19b6a484ac74e545198bc5fc8 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sat, 11 May 2024 17:56:13 +0800 Subject: [PATCH 113/191] ARM: dts: rockchip: rk3506: Add fspi Change-Id: If3c4e5ffd3a351fe586613b7e4ab08b665025b66 Signed-off-by: Jon Lin Signed-off-by: Finley Xiao --- arch/arm/boot/dts/rk3506.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index ae5b786f5ddf..f4bfc11d3033 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -17,6 +17,7 @@ aliases { serial0 = &uart0; + spi2 = &fspi; }; clocks { @@ -214,6 +215,17 @@ }; }; + fspi: spi@ff488000 { + compatible = "rockchip,fspi"; + reg = <0xff488000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_FSPI>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@ff581000 { compatible = "arm,gic-400"; reg = <0xff581000 0x1000>, From 92c5b13ee20a174871c9e1131f6a6c4cefbf543c Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Tue, 7 May 2024 18:26:21 +0800 Subject: [PATCH 114/191] ARM: dts: rockchip: add rk3506-pinctrl.dtsi Signed-off-by: Ye Zhang Signed-off-by: Finley Xiao Change-Id: I141eef76f7d387be9aacc60065d1ec97a01f3dcd --- arch/arm/boot/dts/rk3506-pinctrl.dtsi | 1448 +++++++++++++++++++++++++ arch/arm/boot/dts/rk3506.dtsi | 98 ++ 2 files changed, 1546 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506-pinctrl.dtsi diff --git a/arch/arm/boot/dts/rk3506-pinctrl.dtsi b/arch/arm/boot/dts/rk3506-pinctrl.dtsi new file mode 100644 index 000000000000..2d14d841cab4 --- /dev/null +++ b/arch/arm/boot/dts/rk3506-pinctrl.dtsi @@ -0,0 +1,1448 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + aupll_clk { + /omit-if-no-ref/ + aupll_clk_pins: aupll-clk-pins { + rockchip,pins = + /* aupll_clk_in */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + dsm_aud { + /omit-if-no-ref/ + dsm_audm0_ln_pins: dsm-audm0-ln-pins { + rockchip,pins = + /* dsm_aud_ln_m0 */ + <1 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm0_lp_pins: dsm-audm0-lp-pins { + rockchip,pins = + /* dsm_aud_lp_m0 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm0_rn_pins: dsm-audm0-rn-pins { + rockchip,pins = + /* dsm_aud_rn_m0 */ + <1 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm0_rp_pins: dsm-audm0-rp-pins { + rockchip,pins = + /* dsm_aud_rp_m0 */ + <1 RK_PC2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm1_ln_pins: dsm-audm1-ln-pins { + rockchip,pins = + /* dsm_aud_ln_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm1_lp_pins: dsm-audm1-lp-pins { + rockchip,pins = + /* dsm_aud_lp_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm1_rn_pins: dsm-audm1-rn-pins { + rockchip,pins = + /* dsm_aud_rn_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dsm_audm1_rp_pins: dsm-audm1-rp-pins { + rockchip,pins = + /* dsm_aud_rp_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + dsmc { + /omit-if-no-ref/ + dsmc_clkn_pins: dsmc-clkn-pins { + rockchip,pins = + /* dsmc_clkn */ + <1 RK_PA1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_clkp_pins: dsmc-clkp-pins { + rockchip,pins = + /* dsmc_clkp */ + <1 RK_PA0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_csn0_pins: dsmc-csn0-pins { + rockchip,pins = + /* dsmc_csn0 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_csn1_pins: dsmc-csn1-pins { + rockchip,pins = + /* dsmc_csn1 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_csn2_pins: dsmc-csn2-pins { + rockchip,pins = + /* dsmc_csn2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_csn3_pins: dsmc-csn3-pins { + rockchip,pins = + /* dsmc_csn3 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d0_pins: dsmc-d0-pins { + rockchip,pins = + /* dsmc_d0 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d1_pins: dsmc-d1-pins { + rockchip,pins = + /* dsmc_d1 */ + <1 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d2_pins: dsmc-d2-pins { + rockchip,pins = + /* dsmc_d2 */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d3_pins: dsmc-d3-pins { + rockchip,pins = + /* dsmc_d3 */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d4_pins: dsmc-d4-pins { + rockchip,pins = + /* dsmc_d4 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d5_pins: dsmc-d5-pins { + rockchip,pins = + /* dsmc_d5 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d6_pins: dsmc-d6-pins { + rockchip,pins = + /* dsmc_d6 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d7_pins: dsmc-d7-pins { + rockchip,pins = + /* dsmc_d7 */ + <1 RK_PB5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d8_pins: dsmc-d8-pins { + rockchip,pins = + /* dsmc_d8 */ + <1 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d9_pins: dsmc-d9-pins { + rockchip,pins = + /* dsmc_d9 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d10_pins: dsmc-d10-pins { + rockchip,pins = + /* dsmc_d10 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d11_pins: dsmc-d11-pins { + rockchip,pins = + /* dsmc_d11 */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d12_pins: dsmc-d12-pins { + rockchip,pins = + /* dsmc_d12 */ + <1 RK_PC5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d13_pins: dsmc-d13-pins { + rockchip,pins = + /* dsmc_d13 */ + <1 RK_PC6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d14_pins: dsmc-d14-pins { + rockchip,pins = + /* dsmc_d14 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_d15_pins: dsmc-d15-pins { + rockchip,pins = + /* dsmc_d15 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_dqs0_pins: dsmc-dqs0-pins { + rockchip,pins = + /* dsmc_dqs0 */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_dqs1_pins: dsmc-dqs1-pins { + rockchip,pins = + /* dsmc_dqs1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_int0_pins: dsmc-int0-pins { + rockchip,pins = + /* dsmc_int0 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_int1_pins: dsmc-int1-pins { + rockchip,pins = + /* dsmc_int1 */ + <1 RK_PC0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_int2_pins: dsmc-int2-pins { + rockchip,pins = + /* dsmc_int2 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_int3_pins: dsmc-int3-pins { + rockchip,pins = + /* dsmc_int3 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_rdyn_pins: dsmc-rdyn-pins { + rockchip,pins = + /* dsmc_rdyn */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_resetn_pins: dsmc-resetn-pins { + rockchip,pins = + /* dsmc_resetn */ + <1 RK_PC0 2 &pcfg_pull_none>; + }; + }; + + dsmc_slv { + /omit-if-no-ref/ + dsmc_slv_clk_pins: dsmc-slv-clk-pins { + rockchip,pins = + /* dsmc_slv_clk */ + <1 RK_PC0 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_csn0_pins: dsmc-slv-csn0-pins { + rockchip,pins = + /* dsmc_slv_csn0 */ + <1 RK_PD2 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d0_pins: dsmc-slv-d0-pins { + rockchip,pins = + /* dsmc_slv_d0 */ + <1 RK_PC2 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d1_pins: dsmc-slv-d1-pins { + rockchip,pins = + /* dsmc_slv_d1 */ + <1 RK_PC3 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d2_pins: dsmc-slv-d2-pins { + rockchip,pins = + /* dsmc_slv_d2 */ + <1 RK_PC4 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d3_pins: dsmc-slv-d3-pins { + rockchip,pins = + /* dsmc_slv_d3 */ + <1 RK_PC5 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d4_pins: dsmc-slv-d4-pins { + rockchip,pins = + /* dsmc_slv_d4 */ + <1 RK_PC6 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d5_pins: dsmc-slv-d5-pins { + rockchip,pins = + /* dsmc_slv_d5 */ + <1 RK_PC7 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d6_pins: dsmc-slv-d6-pins { + rockchip,pins = + /* dsmc_slv_d6 */ + <1 RK_PD0 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_d7_pins: dsmc-slv-d7-pins { + rockchip,pins = + /* dsmc_slv_d7 */ + <1 RK_PD1 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_dqs0_pins: dsmc-slv-dqs0-pins { + rockchip,pins = + /* dsmc_slv_dqs0 */ + <1 RK_PC1 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_int_pins: dsmc-slv-int-pins { + rockchip,pins = + /* dsmc_slv_int */ + <1 RK_PA1 8 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + dsmc_slv_rdyn_pins: dsmc-slv-rdyn-pins { + rockchip,pins = + /* dsmc_slv_rdyn */ + <1 RK_PD3 8 &pcfg_pull_none>; + }; + }; + + eth_clk0_25m { + /omit-if-no-ref/ + eth_clk0_25m_out_pins: eth-clk0-25m-out-pins { + rockchip,pins = + /* eth_clk0_25m_out */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + eth_clk1_25m { + /omit-if-no-ref/ + eth_clk1_25m_out_pins: eth-clk1-25m-out-pins { + rockchip,pins = + /* eth_clk1_25m_out */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + eth_rmii0 { + /omit-if-no-ref/ + eth_rmii0_miim_pins: eth-rmii0-miim-pins { + rockchip,pins = + /* eth_rmii0_mdc */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* eth_rmii0_mdio */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii0_rx_bus2_pins: eth-rmii0-rx-bus2-pins { + rockchip,pins = + /* eth_rmii0_rxd0 */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* eth_rmii0_rxd1 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* eth_rmii0_rxdvcrs */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii0_tx_bus2_pins: eth-rmii0-tx-bus2-pins { + rockchip,pins = + /* eth_rmii0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none>, + /* eth_rmii0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none>, + /* eth_rmii0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii0_clk_pins: eth-rmii0-clk-pins { + rockchip,pins = + /* eth_rmii0_clk */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth_rmii1 { + /omit-if-no-ref/ + eth_rmii1_miim_pins: eth-rmii1-miim-pins { + rockchip,pins = + /* eth_rmii1_mdc */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* eth_rmii1_mdio */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii1_rx_bus2_pins: eth-rmii1-rx-bus2-pins { + rockchip,pins = + /* eth_rmii1_rxd0 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* eth_rmii1_rxd1 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* eth_rmii1_rxdvcrs */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii1_tx_bus2_pins: eth-rmii1-tx-bus2-pins { + rockchip,pins = + /* eth_rmii1_txd0 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* eth_rmii1_txd1 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* eth_rmii1_txen */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth_rmii1_clk_pins: eth-rmii1-clk-pins { + rockchip,pins = + /* eth_rmii1_clk */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + flexbus0 { + /omit-if-no-ref/ + flexbus0m0_pins: flexbus0m0-pins { + rockchip,pins = + /* flexbus0_csn_m0 */ + <1 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0m1_pins: flexbus0m1-pins { + rockchip,pins = + /* flexbus0_csn_m1 */ + <1 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0m2_pins: flexbus0m2-pins { + rockchip,pins = + /* flexbus0_csn_m2 */ + <1 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0m3_pins: flexbus0m3-pins { + rockchip,pins = + /* flexbus0_csn_m3 */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0m4_pins: flexbus0m4-pins { + rockchip,pins = + /* flexbus0_csn_m4 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0m5_pins: flexbus0m5-pins { + rockchip,pins = + /* flexbus0_csn_m5 */ + <1 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus0_clk_pins: flexbus0-clk-pins { + rockchip,pins = + /* flexbus0_clk */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d0_pins: flexbus0-d0-pins { + rockchip,pins = + /* flexbus0_d0 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d1_pins: flexbus0-d1-pins { + rockchip,pins = + /* flexbus0_d1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d2_pins: flexbus0-d2-pins { + rockchip,pins = + /* flexbus0_d2 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d3_pins: flexbus0-d3-pins { + rockchip,pins = + /* flexbus0_d3 */ + <1 RK_PD0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d4_pins: flexbus0-d4-pins { + rockchip,pins = + /* flexbus0_d4 */ + <1 RK_PC7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d5_pins: flexbus0-d5-pins { + rockchip,pins = + /* flexbus0_d5 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d6_pins: flexbus0-d6-pins { + rockchip,pins = + /* flexbus0_d6 */ + <1 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d7_pins: flexbus0-d7-pins { + rockchip,pins = + /* flexbus0_d7 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d8_pins: flexbus0-d8-pins { + rockchip,pins = + /* flexbus0_d8 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d9_pins: flexbus0-d9-pins { + rockchip,pins = + /* flexbus0_d9 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d10_pins: flexbus0-d10-pins { + rockchip,pins = + /* flexbus0_d10 */ + <1 RK_PB7 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d11_pins: flexbus0-d11-pins { + rockchip,pins = + /* flexbus0_d11 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d12_pins: flexbus0-d12-pins { + rockchip,pins = + /* flexbus0_d12 */ + <1 RK_PB5 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d13_pins: flexbus0-d13-pins { + rockchip,pins = + /* flexbus0_d13 */ + <1 RK_PB4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d14_pins: flexbus0-d14-pins { + rockchip,pins = + /* flexbus0_d14 */ + <1 RK_PB3 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus0_d15_pins: flexbus0-d15-pins { + rockchip,pins = + /* flexbus0_d15 */ + <1 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + flexbus1 { + /omit-if-no-ref/ + flexbus1m0_pins: flexbus1m0-pins { + rockchip,pins = + /* flexbus1_csn_m0 */ + <1 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1m1_pins: flexbus1m1-pins { + rockchip,pins = + /* flexbus1_csn_m1 */ + <1 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1m2_pins: flexbus1m2-pins { + rockchip,pins = + /* flexbus1_csn_m2 */ + <1 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1m3_pins: flexbus1m3-pins { + rockchip,pins = + /* flexbus1_csn_m3 */ + <1 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1m4_pins: flexbus1m4-pins { + rockchip,pins = + /* flexbus1_csn_m4 */ + <1 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1m5_pins: flexbus1m5-pins { + rockchip,pins = + /* flexbus1_csn_m5 */ + <1 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + flexbus1_clk_pins: flexbus1-clk-pins { + rockchip,pins = + /* flexbus1_clk */ + <1 RK_PC0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d0_pins: flexbus1-d0-pins { + rockchip,pins = + /* flexbus1_d0 */ + <1 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d1_pins: flexbus1-d1-pins { + rockchip,pins = + /* flexbus1_d1 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d2_pins: flexbus1-d2-pins { + rockchip,pins = + /* flexbus1_d2 */ + <1 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d3_pins: flexbus1-d3-pins { + rockchip,pins = + /* flexbus1_d3 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d4_pins: flexbus1-d4-pins { + rockchip,pins = + /* flexbus1_d4 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d5_pins: flexbus1-d5-pins { + rockchip,pins = + /* flexbus1_d5 */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d6_pins: flexbus1-d6-pins { + rockchip,pins = + /* flexbus1_d6 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d7_pins: flexbus1-d7-pins { + rockchip,pins = + /* flexbus1_d7 */ + <1 RK_PA7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d8_pins: flexbus1-d8-pins { + rockchip,pins = + /* flexbus1_d8 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d9_pins: flexbus1-d9-pins { + rockchip,pins = + /* flexbus1_d9 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d10_pins: flexbus1-d10-pins { + rockchip,pins = + /* flexbus1_d10 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d11_pins: flexbus1-d11-pins { + rockchip,pins = + /* flexbus1_d11 */ + <1 RK_PB3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d12_pins: flexbus1-d12-pins { + rockchip,pins = + /* flexbus1_d12 */ + <1 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d13_pins: flexbus1-d13-pins { + rockchip,pins = + /* flexbus1_d13 */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d14_pins: flexbus1-d14-pins { + rockchip,pins = + /* flexbus1_d14 */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + flexbus1_d15_pins: flexbus1-d15-pins { + rockchip,pins = + /* flexbus1_d15 */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_bus4_pins: fspi-bus4-pins { + rockchip,pins = + /* fspi_d0 */ + <2 RK_PA2 1 &pcfg_pull_none>, + /* fspi_d1 */ + <2 RK_PA3 1 &pcfg_pull_none>, + /* fspi_d2 */ + <2 RK_PA4 1 &pcfg_pull_none>, + /* fspi_d3 */ + <2 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_clk_pins: fspi-clk-pins { + rockchip,pins = + /* fspi_clk */ + <2 RK_PA1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn_pins: fspi-csn-pins { + rockchip,pins = + /* fspi_csn */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <3 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <0 RK_PC6 2 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + ref_clk1 { + /omit-if-no-ref/ + ref_clk1_pins: ref-clk1-pins { + rockchip,pins = + /* ref_clk1_out */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + rm { + /omit-if-no-ref/ + rm_io0_pins: rm-io0-pins { + rockchip,pins = + /* rm_io0 */ + <0 RK_PA0 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pins: rm-io1-pins { + rockchip,pins = + /* rm_io1 */ + <0 RK_PA1 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pins: rm-io2-pins { + rockchip,pins = + /* rm_io2 */ + <0 RK_PA2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pins: rm-io3-pins { + rockchip,pins = + /* rm_io3 */ + <0 RK_PA3 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pins: rm-io4-pins { + rockchip,pins = + /* rm_io4 */ + <0 RK_PA4 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pins: rm-io5-pins { + rockchip,pins = + /* rm_io5 */ + <0 RK_PA5 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pins: rm-io6-pins { + rockchip,pins = + /* rm_io6 */ + <0 RK_PA6 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pins: rm-io7-pins { + rockchip,pins = + /* rm_io7 */ + <0 RK_PA7 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pins: rm-io8-pins { + rockchip,pins = + /* rm_io8 */ + <0 RK_PB0 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pins: rm-io9-pins { + rockchip,pins = + /* rm_io9 */ + <0 RK_PB1 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pins: rm-io10-pins { + rockchip,pins = + /* rm_io10 */ + <0 RK_PB2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pins: rm-io11-pins { + rockchip,pins = + /* rm_io11 */ + <0 RK_PB3 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pins: rm-io12-pins { + rockchip,pins = + /* rm_io12 */ + <0 RK_PB4 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pins: rm-io13-pins { + rockchip,pins = + /* rm_io13 */ + <0 RK_PB5 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pins: rm-io14-pins { + rockchip,pins = + /* rm_io14 */ + <0 RK_PB6 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pins: rm-io15-pins { + rockchip,pins = + /* rm_io15 */ + <0 RK_PB7 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pins: rm-io16-pins { + rockchip,pins = + /* rm_io16 */ + <0 RK_PC0 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pins: rm-io17-pins { + rockchip,pins = + /* rm_io17 */ + <0 RK_PC1 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pins: rm-io18-pins { + rockchip,pins = + /* rm_io18 */ + <0 RK_PC2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pins: rm-io19-pins { + rockchip,pins = + /* rm_io19 */ + <0 RK_PC3 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pins: rm-io20-pins { + rockchip,pins = + /* rm_io20 */ + <0 RK_PC4 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pins: rm-io21-pins { + rockchip,pins = + /* rm_io21 */ + <0 RK_PC5 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pins: rm-io22-pins { + rockchip,pins = + /* rm_io22 */ + <0 RK_PC6 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pins: rm-io23-pins { + rockchip,pins = + /* rm_io23 */ + <0 RK_PC7 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pins: rm-io24-pins { + rockchip,pins = + /* rm_io24 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pins: rm-io25-pins { + rockchip,pins = + /* rm_io25 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pins: rm-io26-pins { + rockchip,pins = + /* rm_io26 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pins: rm-io27-pins { + rockchip,pins = + /* rm_io27 */ + <1 RK_PC2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pins: rm-io28-pins { + rockchip,pins = + /* rm_io28 */ + <1 RK_PC3 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pins: rm-io29-pins { + rockchip,pins = + /* rm_io29 */ + <1 RK_PD1 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pins: rm-io30-pins { + rockchip,pins = + /* rm_io30 */ + <1 RK_PD2 7 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pins: rm-io31-pins { + rockchip,pins = + /* rm_io31 */ + <1 RK_PD3 7 &pcfg_pull_none>; + }; + }; + + sai0 { + /omit-if-no-ref/ + sai0_lrck_pins: sai0-lrck-pins { + rockchip,pins = + /* sai0_lrck */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_mclk_pins: sai0-mclk-pins { + rockchip,pins = + /* sai0_mclk */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sclk_pins: sai0-sclk-pins { + rockchip,pins = + /* sai0_sclk */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sdi0_pins: sai0-sdi0-pins { + rockchip,pins = + /* sai0_sdi0 */ + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sdi1_pins: sai0-sdi1-pins { + rockchip,pins = + /* sai0_sdi1 */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sdi2_pins: sai0-sdi2-pins { + rockchip,pins = + /* sai0_sdi2 */ + <0 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sdi3_pins: sai0-sdi3-pins { + rockchip,pins = + /* sai0_sdi3 */ + <0 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai0_sdo_pins: sai0-sdo-pins { + rockchip,pins = + /* sai0_sdo */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + sai1 { + /omit-if-no-ref/ + sai1_lrck_pins: sai1-lrck-pins { + rockchip,pins = + /* sai1_lrck */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_mclk_pins: sai1-mclk-pins { + rockchip,pins = + /* sai1_mclk */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sclk_pins: sai1-sclk-pins { + rockchip,pins = + /* sai1_sclk */ + <0 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sdo0_pins: sai1-sdo0-pins { + rockchip,pins = + /* sai1_sdo0 */ + <0 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sdo1_pins: sai1-sdo1-pins { + rockchip,pins = + /* sai1_sdo1 */ + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sdo2_pins: sai1-sdo2-pins { + rockchip,pins = + /* sai1_sdo2 */ + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sdo3_pins: sai1-sdo3-pins { + rockchip,pins = + /* sai1_sdo3 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai1_sdi_pins: sai1-sdi-pins { + rockchip,pins = + /* sai1_sdi */ + <0 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + sai2 { + /omit-if-no-ref/ + sai2m0_lrck_pins: sai2m0-lrck-pins { + rockchip,pins = + /* sai2_lrck_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m0_mclk_pins: sai2m0-mclk-pins { + rockchip,pins = + /* sai2_mclk_m0 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m0_sclk_pins: sai2m0-sclk-pins { + rockchip,pins = + /* sai2_sclk_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m0_sdi_pins: sai2m0-sdi-pins { + rockchip,pins = + /* sai2m0_sdi */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sai2m0_sdo_pins: sai2m0-sdo-pins { + rockchip,pins = + /* sai2m0_sdo */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m1_lrck_pins: sai2m1-lrck-pins { + rockchip,pins = + /* sai2_lrck_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m1_mclk_pins: sai2m1-mclk-pins { + rockchip,pins = + /* sai2_mclk_m1 */ + <1 RK_PC1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m1_sclk_pins: sai2m1-sclk-pins { + rockchip,pins = + /* sai2_sclk_m1 */ + <1 RK_PB2 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai2m1_sdi_pins: sai2m1-sdi-pins { + rockchip,pins = + /* sai2m1_sdi */ + <1 RK_PC2 6 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sai2m1_sdo_pins: sai2m1-sdo-pins { + rockchip,pins = + /* sai2m1_sdo */ + <1 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + sai3 { + /omit-if-no-ref/ + sai3_lrck_pins: sai3-lrck-pins { + rockchip,pins = + /* sai3_lrck */ + <2 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai3_mclk_pins: sai3-mclk-pins { + rockchip,pins = + /* sai3_mclk */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai3_sclk_pins: sai3-sclk-pins { + rockchip,pins = + /* sai3_sclk */ + <2 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sai3_sdi_pins: sai3-sdi-pins { + rockchip,pins = + /* sai3_sdi */ + <2 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sai3_sdo_pins: sai3-sdo-pins { + rockchip,pins = + /* sai3_sdo */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4_pins: sdmmc-bus4-pins { + rockchip,pins = + /* sdmmc_d0 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* sdmmc_d1 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* sdmmc_d2 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* sdmmc_d3 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc_clk_pins: sdmmc-clk-pins { + rockchip,pins = + /* sdmmc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc_cmd_pins: sdmmc-cmd-pins { + rockchip,pins = + /* sdmmc_cmd */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_clk_pins: spi0-clk-pins { + rockchip,pins = + /* spi0_clk */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* spi0_miso */ + <0 RK_PC2 2 &pcfg_pull_none>, + /* spi0_mosi */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0_csn0_pins: spi0-csn0-pins { + rockchip,pins = + /* spi0_csn0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi0_csn1_pins: spi0-csn1-pins { + rockchip,pins = + /* spi0_csn1 */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_clk_pins: spi1-clk-pins { + rockchip,pins = + /* spi1_clk */ + <0 RK_PB0 2 &pcfg_pull_none>, + /* spi1_miso */ + <0 RK_PB2 2 &pcfg_pull_none>, + /* spi1_mosi */ + <0 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1_csn0_pins: spi1-csn0-pins { + rockchip,pins = + /* spi1_csn0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + spi1_csn1_pins: spi1-csn1-pins { + rockchip,pins = + /* spi1_csn1 */ + <0 RK_PA7 2 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2_clk_pins: spi2-clk-pins { + rockchip,pins = + /* spi2_clk */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* spi2_miso */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* spi2_mosi */ + <2 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2_csn_pins: spi2-csn-pins { + rockchip,pins = + /* spi2_csn */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + test_clk { + /omit-if-no-ref/ + test_clk_pins: test-clk-pins { + rockchip,pins = + /* test_clk_out */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer_pins: uart0-xfer-pins { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer_pins: uart5m0-xfer-pins { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PB3 1 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PB4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn_pins: uart5m0-ctsn-pins { + rockchip,pins = + /* uart5m0_ctsn */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn_pins: uart5m0-rtsn-pins { + rockchip,pins = + /* uart5m0_rtsn */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer_pins: uart5m1-xfer-pins { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD3 6 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD2 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn_pins: uart5m1-ctsn-pins { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PB1 6 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn_pins: uart5m1-rtsn-pins { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD1 6 &pcfg_pull_none>; + }; + }; + + vo_lcdc { + /omit-if-no-ref/ + vo_lcdc_pins: vo-lcdc-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <1 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <1 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <1 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <1 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <1 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index f4bfc11d3033..4d8514b8c65c 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -16,6 +17,11 @@ interrupt-parent = <&gic>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; serial0 = &uart0; spi2 = &fspi; }; @@ -226,6 +232,11 @@ status = "disabled"; }; + ioc_grf: syscon@ff4d8000 { + compatible = "rockchip,rk3506-ioc-grf", "syscon"; + reg = <0xff4d8000 0x8000>; + }; + gic: interrupt-controller@ff581000 { compatible = "arm,gic-400"; reg = <0xff581000 0x1000>, @@ -257,6 +268,11 @@ }; }; + ioc1: syscon@ff660000 { + compatible = "rockchip,rk3506-ioc1", "syscon"; + reg = <0xff660000 0x10000>; + }; + arm-debug@ff810000 { compatible = "rockchip,debug"; reg = <0xff810000 0x1000>, @@ -304,6 +320,11 @@ status = "disabled"; }; + ioc_pmu: syscon@ff950000 { + compatible = "rockchip,rk3506-ioc-pmu", "syscon"; + reg = <0xff950000 0x10000>; + }; + cru: clock-controller@ff9a0000 { compatible = "rockchip,rk3506-cru"; reg = <0xff9a0000 0x20000>; @@ -311,4 +332,81 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3506-pinctrl"; + rockchip,grf = <&ioc_grf>; + rockchip,ioc1 = <&ioc1>; + rockchip,pmu = <&ioc_pmu>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff940000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff940000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff870000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff870000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff1c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1c0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff1d0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1d0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff1e0000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff1e0000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; + +#include "rk3506-pinctrl.dtsi" From 495dd09aeeaf55ffee3709d1f7a49a4817ef3507 Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Mon, 13 May 2024 15:30:37 +0800 Subject: [PATCH 115/191] ARM: dts: rockchip: add rmio support in rk3506.dtsi Signed-off-by: Ye Zhang Change-Id: I130486752667da07c9528c651684455df91e7228 --- arch/arm/boot/dts/rk3506-pinctrl-rmio.dtsi | 15787 +++++++++++++++++++ arch/arm/boot/dts/rk3506.dtsi | 7 + 2 files changed, 15794 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506-pinctrl-rmio.dtsi diff --git a/arch/arm/boot/dts/rk3506-pinctrl-rmio.dtsi b/arch/arm/boot/dts/rk3506-pinctrl-rmio.dtsi new file mode 100644 index 000000000000..566162b2c5d9 --- /dev/null +++ b/arch/arm/boot/dts/rk3506-pinctrl-rmio.dtsi @@ -0,0 +1,15787 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + rm_io0 { + /omit-if-no-ref/ + rm_io0_uart1_tx: rm-io0-uart1-tx { + rockchip,pins = + <0 RK_PA0 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart1_rx: rm-io0-uart1-rx { + rockchip,pins = + <0 RK_PA0 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io0_uart2_tx: rm-io0-uart2-tx { + rockchip,pins = + <0 RK_PA0 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart2_rx: rm-io0-uart2-rx { + rockchip,pins = + <0 RK_PA0 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io0_uart3_tx: rm-io0-uart3-tx { + rockchip,pins = + <0 RK_PA0 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart3_rx: rm-io0-uart3-rx { + rockchip,pins = + <0 RK_PA0 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io0_uart3_ctsn: rm-io0-uart3-ctsn { + rockchip,pins = + <0 RK_PA0 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart3_rtsn: rm-io0-uart3-rtsn { + rockchip,pins = + <0 RK_PA0 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart4_tx: rm-io0-uart4-tx { + rockchip,pins = + <0 RK_PA0 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart4_rx: rm-io0-uart4-rx { + rockchip,pins = + <0 RK_PA0 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io0_uart4_ctsn: rm-io0-uart4-ctsn { + rockchip,pins = + <0 RK_PA0 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_uart4_rtsn: rm-io0-uart4-rtsn { + rockchip,pins = + <0 RK_PA0 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_mipite: rm-io0-mipite { + rockchip,pins = + <0 RK_PA0 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_clk_32k: rm-io0-clk-32k { + rockchip,pins = + <0 RK_PA0 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c0_scl: rm-io0-i2c0-scl { + rockchip,pins = + <0 RK_PA0 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c0_sda: rm-io0-i2c0-sda { + rockchip,pins = + <0 RK_PA0 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c1_scl: rm-io0-i2c1-scl { + rockchip,pins = + <0 RK_PA0 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c1_sda: rm-io0-i2c1-sda { + rockchip,pins = + <0 RK_PA0 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c2_scl: rm-io0-i2c2-scl { + rockchip,pins = + <0 RK_PA0 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_i2c2_sda: rm-io0-i2c2-sda { + rockchip,pins = + <0 RK_PA0 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_clk0: rm-io0-pdm-clk0 { + rockchip,pins = + <0 RK_PA0 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_sdi0: rm-io0-pdm-sdi0 { + rockchip,pins = + <0 RK_PA0 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_sdi1: rm-io0-pdm-sdi1 { + rockchip,pins = + <0 RK_PA0 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_sdi2: rm-io0-pdm-sdi2 { + rockchip,pins = + <0 RK_PA0 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_sdi3: rm-io0-pdm-sdi3 { + rockchip,pins = + <0 RK_PA0 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_can1_tx: rm-io0-can1-tx { + rockchip,pins = + <0 RK_PA0 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_can1_rx: rm-io0-can1-rx { + rockchip,pins = + <0 RK_PA0 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_can0_tx: rm-io0-can0-tx { + rockchip,pins = + <0 RK_PA0 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_can0_rx: rm-io0-can0-rx { + rockchip,pins = + <0 RK_PA0 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm0_ch0: rm-io0-pwm0-ch0 { + rockchip,pins = + <0 RK_PA0 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm0_ch1: rm-io0-pwm0-ch1 { + rockchip,pins = + <0 RK_PA0 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm0_ch2: rm-io0-pwm0-ch2 { + rockchip,pins = + <0 RK_PA0 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm0_ch3: rm-io0-pwm0-ch3 { + rockchip,pins = + <0 RK_PA0 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch0: rm-io0-pwm1-ch0 { + rockchip,pins = + <0 RK_PA0 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch1: rm-io0-pwm1-ch1 { + rockchip,pins = + <0 RK_PA0 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch2: rm-io0-pwm1-ch2 { + rockchip,pins = + <0 RK_PA0 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch3: rm-io0-pwm1-ch3 { + rockchip,pins = + <0 RK_PA0 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch4: rm-io0-pwm1-ch4 { + rockchip,pins = + <0 RK_PA0 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch5: rm-io0-pwm1-ch5 { + rockchip,pins = + <0 RK_PA0 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch6: rm-io0-pwm1-ch6 { + rockchip,pins = + <0 RK_PA0 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_ch7: rm-io0-pwm1-ch7 { + rockchip,pins = + <0 RK_PA0 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_drive: rm-io0-touch-key-drive { + rockchip,pins = + <0 RK_PA0 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in0: rm-io0-touch-key-in0 { + rockchip,pins = + <0 RK_PA0 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in1: rm-io0-touch-key-in1 { + rockchip,pins = + <0 RK_PA0 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in2: rm-io0-touch-key-in2 { + rockchip,pins = + <0 RK_PA0 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in3: rm-io0-touch-key-in3 { + rockchip,pins = + <0 RK_PA0 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in4: rm-io0-touch-key-in4 { + rockchip,pins = + <0 RK_PA0 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in5: rm-io0-touch-key-in5 { + rockchip,pins = + <0 RK_PA0 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in6: rm-io0-touch-key-in6 { + rockchip,pins = + <0 RK_PA0 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_touch_key_in7: rm-io0-touch-key-in7 { + rockchip,pins = + <0 RK_PA0 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_mclk: rm-io0-sai0-mclk { + rockchip,pins = + <0 RK_PA0 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sclk: rm-io0-sai0-sclk { + rockchip,pins = + <0 RK_PA0 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_lrck: rm-io0-sai0-lrck { + rockchip,pins = + <0 RK_PA0 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sdi0: rm-io0-sai0-sdi0 { + rockchip,pins = + <0 RK_PA0 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sdi1: rm-io0-sai0-sdi1 { + rockchip,pins = + <0 RK_PA0 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sdi2: rm-io0-sai0-sdi2 { + rockchip,pins = + <0 RK_PA0 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sdi3: rm-io0-sai0-sdi3 { + rockchip,pins = + <0 RK_PA0 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai0_sdo: rm-io0-sai0-sdo { + rockchip,pins = + <0 RK_PA0 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_mclk: rm-io0-sai1-mclk { + rockchip,pins = + <0 RK_PA0 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sclk: rm-io0-sai1-sclk { + rockchip,pins = + <0 RK_PA0 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_lrck: rm-io0-sai1-lrck { + rockchip,pins = + <0 RK_PA0 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sdi: rm-io0-sai1-sdi { + rockchip,pins = + <0 RK_PA0 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sdo0: rm-io0-sai1-sdo0 { + rockchip,pins = + <0 RK_PA0 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sdo1: rm-io0-sai1-sdo1 { + rockchip,pins = + <0 RK_PA0 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sdo2: rm-io0-sai1-sdo2 { + rockchip,pins = + <0 RK_PA0 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_sai1_sdo3: rm-io0-sai1-sdo3 { + rockchip,pins = + <0 RK_PA0 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi0_clk: rm-io0-spi0-clk { + rockchip,pins = + <0 RK_PA0 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi0_mosi: rm-io0-spi0-mosi { + rockchip,pins = + <0 RK_PA0 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi0_miso: rm-io0-spi0-miso { + rockchip,pins = + <0 RK_PA0 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi0_csn0: rm-io0-spi0-csn0 { + rockchip,pins = + <0 RK_PA0 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi0_csn1: rm-io0-spi0-csn1 { + rockchip,pins = + <0 RK_PA0 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi1_clk: rm-io0-spi1-clk { + rockchip,pins = + <0 RK_PA0 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi1_mosi: rm-io0-spi1-mosi { + rockchip,pins = + <0 RK_PA0 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi1_miso: rm-io0-spi1-miso { + rockchip,pins = + <0 RK_PA0 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi1_csn0: rm-io0-spi1-csn0 { + rockchip,pins = + <0 RK_PA0 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spi1_csn1: rm-io0-spi1-csn1 { + rockchip,pins = + <0 RK_PA0 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_wdt_tsadc_shut: rm-io0-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA0 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pmu_sleep: rm-io0-pmu-sleep { + rockchip,pins = + <0 RK_PA0 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_core_power_off: rm-io0-core-power-off { + rockchip,pins = + <0 RK_PA0 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spdif_tx: rm-io0-spdif-tx { + rockchip,pins = + <0 RK_PA0 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_spdif_rx: rm-io0-spdif-rx { + rockchip,pins = + <0 RK_PA0 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a0: rm-io0-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA0 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a1: rm-io0-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA0 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a2: rm-io0-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA0 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a3: rm-io0-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA0 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a4: rm-io0-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA0 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_a5: rm-io0-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA0 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b0: rm-io0-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA0 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b1: rm-io0-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA0 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b2: rm-io0-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA0 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b3: rm-io0-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA0 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b4: rm-io0-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA0 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pwm1_bip_cntr_b5: rm-io0-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA0 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_pdm_clk1: rm-io0-pdm-clk1 { + rockchip,pins = + <0 RK_PA0 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_eth_rmii0_ppsclk: rm-io0-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA0 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_eth_rmii0_ppstrig: rm-io0-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA0 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_eth_rmii1_ppsclk: rm-io0-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA0 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io0_eth_rmii1_ppstrig: rm-io0-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA0 113 &pcfg_pull_none>; + }; + }; + + rm_io1 { + /omit-if-no-ref/ + rm_io1_uart1_tx: rm-io1-uart1-tx { + rockchip,pins = + <0 RK_PA1 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart1_rx: rm-io1-uart1-rx { + rockchip,pins = + <0 RK_PA1 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io1_uart2_tx: rm-io1-uart2-tx { + rockchip,pins = + <0 RK_PA1 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart2_rx: rm-io1-uart2-rx { + rockchip,pins = + <0 RK_PA1 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io1_uart3_tx: rm-io1-uart3-tx { + rockchip,pins = + <0 RK_PA1 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart3_rx: rm-io1-uart3-rx { + rockchip,pins = + <0 RK_PA1 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io1_uart3_ctsn: rm-io1-uart3-ctsn { + rockchip,pins = + <0 RK_PA1 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart3_rtsn: rm-io1-uart3-rtsn { + rockchip,pins = + <0 RK_PA1 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart4_tx: rm-io1-uart4-tx { + rockchip,pins = + <0 RK_PA1 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart4_rx: rm-io1-uart4-rx { + rockchip,pins = + <0 RK_PA1 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io1_uart4_ctsn: rm-io1-uart4-ctsn { + rockchip,pins = + <0 RK_PA1 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_uart4_rtsn: rm-io1-uart4-rtsn { + rockchip,pins = + <0 RK_PA1 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_mipite: rm-io1-mipite { + rockchip,pins = + <0 RK_PA1 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_clk_32k: rm-io1-clk-32k { + rockchip,pins = + <0 RK_PA1 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c0_scl: rm-io1-i2c0-scl { + rockchip,pins = + <0 RK_PA1 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c0_sda: rm-io1-i2c0-sda { + rockchip,pins = + <0 RK_PA1 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c1_scl: rm-io1-i2c1-scl { + rockchip,pins = + <0 RK_PA1 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c1_sda: rm-io1-i2c1-sda { + rockchip,pins = + <0 RK_PA1 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c2_scl: rm-io1-i2c2-scl { + rockchip,pins = + <0 RK_PA1 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_i2c2_sda: rm-io1-i2c2-sda { + rockchip,pins = + <0 RK_PA1 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_clk0: rm-io1-pdm-clk0 { + rockchip,pins = + <0 RK_PA1 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_sdi0: rm-io1-pdm-sdi0 { + rockchip,pins = + <0 RK_PA1 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_sdi1: rm-io1-pdm-sdi1 { + rockchip,pins = + <0 RK_PA1 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_sdi2: rm-io1-pdm-sdi2 { + rockchip,pins = + <0 RK_PA1 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_sdi3: rm-io1-pdm-sdi3 { + rockchip,pins = + <0 RK_PA1 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_can1_tx: rm-io1-can1-tx { + rockchip,pins = + <0 RK_PA1 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_can1_rx: rm-io1-can1-rx { + rockchip,pins = + <0 RK_PA1 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_can0_tx: rm-io1-can0-tx { + rockchip,pins = + <0 RK_PA1 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_can0_rx: rm-io1-can0-rx { + rockchip,pins = + <0 RK_PA1 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm0_ch0: rm-io1-pwm0-ch0 { + rockchip,pins = + <0 RK_PA1 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm0_ch1: rm-io1-pwm0-ch1 { + rockchip,pins = + <0 RK_PA1 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm0_ch2: rm-io1-pwm0-ch2 { + rockchip,pins = + <0 RK_PA1 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm0_ch3: rm-io1-pwm0-ch3 { + rockchip,pins = + <0 RK_PA1 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch0: rm-io1-pwm1-ch0 { + rockchip,pins = + <0 RK_PA1 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch1: rm-io1-pwm1-ch1 { + rockchip,pins = + <0 RK_PA1 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch2: rm-io1-pwm1-ch2 { + rockchip,pins = + <0 RK_PA1 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch3: rm-io1-pwm1-ch3 { + rockchip,pins = + <0 RK_PA1 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch4: rm-io1-pwm1-ch4 { + rockchip,pins = + <0 RK_PA1 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch5: rm-io1-pwm1-ch5 { + rockchip,pins = + <0 RK_PA1 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch6: rm-io1-pwm1-ch6 { + rockchip,pins = + <0 RK_PA1 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_ch7: rm-io1-pwm1-ch7 { + rockchip,pins = + <0 RK_PA1 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_drive: rm-io1-touch-key-drive { + rockchip,pins = + <0 RK_PA1 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in0: rm-io1-touch-key-in0 { + rockchip,pins = + <0 RK_PA1 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in1: rm-io1-touch-key-in1 { + rockchip,pins = + <0 RK_PA1 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in2: rm-io1-touch-key-in2 { + rockchip,pins = + <0 RK_PA1 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in3: rm-io1-touch-key-in3 { + rockchip,pins = + <0 RK_PA1 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in4: rm-io1-touch-key-in4 { + rockchip,pins = + <0 RK_PA1 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in5: rm-io1-touch-key-in5 { + rockchip,pins = + <0 RK_PA1 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in6: rm-io1-touch-key-in6 { + rockchip,pins = + <0 RK_PA1 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_touch_key_in7: rm-io1-touch-key-in7 { + rockchip,pins = + <0 RK_PA1 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_mclk: rm-io1-sai0-mclk { + rockchip,pins = + <0 RK_PA1 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sclk: rm-io1-sai0-sclk { + rockchip,pins = + <0 RK_PA1 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_lrck: rm-io1-sai0-lrck { + rockchip,pins = + <0 RK_PA1 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sdi0: rm-io1-sai0-sdi0 { + rockchip,pins = + <0 RK_PA1 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sdi1: rm-io1-sai0-sdi1 { + rockchip,pins = + <0 RK_PA1 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sdi2: rm-io1-sai0-sdi2 { + rockchip,pins = + <0 RK_PA1 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sdi3: rm-io1-sai0-sdi3 { + rockchip,pins = + <0 RK_PA1 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai0_sdo: rm-io1-sai0-sdo { + rockchip,pins = + <0 RK_PA1 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_mclk: rm-io1-sai1-mclk { + rockchip,pins = + <0 RK_PA1 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sclk: rm-io1-sai1-sclk { + rockchip,pins = + <0 RK_PA1 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_lrck: rm-io1-sai1-lrck { + rockchip,pins = + <0 RK_PA1 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sdi: rm-io1-sai1-sdi { + rockchip,pins = + <0 RK_PA1 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sdo0: rm-io1-sai1-sdo0 { + rockchip,pins = + <0 RK_PA1 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sdo1: rm-io1-sai1-sdo1 { + rockchip,pins = + <0 RK_PA1 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sdo2: rm-io1-sai1-sdo2 { + rockchip,pins = + <0 RK_PA1 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_sai1_sdo3: rm-io1-sai1-sdo3 { + rockchip,pins = + <0 RK_PA1 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi0_clk: rm-io1-spi0-clk { + rockchip,pins = + <0 RK_PA1 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi0_mosi: rm-io1-spi0-mosi { + rockchip,pins = + <0 RK_PA1 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi0_miso: rm-io1-spi0-miso { + rockchip,pins = + <0 RK_PA1 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi0_csn0: rm-io1-spi0-csn0 { + rockchip,pins = + <0 RK_PA1 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi0_csn1: rm-io1-spi0-csn1 { + rockchip,pins = + <0 RK_PA1 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi1_clk: rm-io1-spi1-clk { + rockchip,pins = + <0 RK_PA1 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi1_mosi: rm-io1-spi1-mosi { + rockchip,pins = + <0 RK_PA1 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi1_miso: rm-io1-spi1-miso { + rockchip,pins = + <0 RK_PA1 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi1_csn0: rm-io1-spi1-csn0 { + rockchip,pins = + <0 RK_PA1 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spi1_csn1: rm-io1-spi1-csn1 { + rockchip,pins = + <0 RK_PA1 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_wdt_tsadc_shut: rm-io1-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA1 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pmu_sleep: rm-io1-pmu-sleep { + rockchip,pins = + <0 RK_PA1 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_core_power_off: rm-io1-core-power-off { + rockchip,pins = + <0 RK_PA1 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spdif_tx: rm-io1-spdif-tx { + rockchip,pins = + <0 RK_PA1 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_spdif_rx: rm-io1-spdif-rx { + rockchip,pins = + <0 RK_PA1 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a0: rm-io1-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA1 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a1: rm-io1-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA1 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a2: rm-io1-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA1 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a3: rm-io1-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA1 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a4: rm-io1-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA1 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_a5: rm-io1-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA1 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b0: rm-io1-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA1 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b1: rm-io1-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA1 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b2: rm-io1-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA1 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b3: rm-io1-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA1 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b4: rm-io1-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA1 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pwm1_bip_cntr_b5: rm-io1-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA1 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_pdm_clk1: rm-io1-pdm-clk1 { + rockchip,pins = + <0 RK_PA1 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_eth_rmii0_ppsclk: rm-io1-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA1 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_eth_rmii0_ppstrig: rm-io1-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA1 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_eth_rmii1_ppsclk: rm-io1-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA1 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io1_eth_rmii1_ppstrig: rm-io1-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA1 113 &pcfg_pull_none>; + }; + }; + + rm_io2 { + /omit-if-no-ref/ + rm_io2_uart1_tx: rm-io2-uart1-tx { + rockchip,pins = + <0 RK_PA2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart1_rx: rm-io2-uart1-rx { + rockchip,pins = + <0 RK_PA2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io2_uart2_tx: rm-io2-uart2-tx { + rockchip,pins = + <0 RK_PA2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart2_rx: rm-io2-uart2-rx { + rockchip,pins = + <0 RK_PA2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io2_uart3_tx: rm-io2-uart3-tx { + rockchip,pins = + <0 RK_PA2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart3_rx: rm-io2-uart3-rx { + rockchip,pins = + <0 RK_PA2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io2_uart3_ctsn: rm-io2-uart3-ctsn { + rockchip,pins = + <0 RK_PA2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart3_rtsn: rm-io2-uart3-rtsn { + rockchip,pins = + <0 RK_PA2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart4_tx: rm-io2-uart4-tx { + rockchip,pins = + <0 RK_PA2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart4_rx: rm-io2-uart4-rx { + rockchip,pins = + <0 RK_PA2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io2_uart4_ctsn: rm-io2-uart4-ctsn { + rockchip,pins = + <0 RK_PA2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_uart4_rtsn: rm-io2-uart4-rtsn { + rockchip,pins = + <0 RK_PA2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_mipite: rm-io2-mipite { + rockchip,pins = + <0 RK_PA2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_clk_32k: rm-io2-clk-32k { + rockchip,pins = + <0 RK_PA2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c0_scl: rm-io2-i2c0-scl { + rockchip,pins = + <0 RK_PA2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c0_sda: rm-io2-i2c0-sda { + rockchip,pins = + <0 RK_PA2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c1_scl: rm-io2-i2c1-scl { + rockchip,pins = + <0 RK_PA2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c1_sda: rm-io2-i2c1-sda { + rockchip,pins = + <0 RK_PA2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c2_scl: rm-io2-i2c2-scl { + rockchip,pins = + <0 RK_PA2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_i2c2_sda: rm-io2-i2c2-sda { + rockchip,pins = + <0 RK_PA2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_clk0: rm-io2-pdm-clk0 { + rockchip,pins = + <0 RK_PA2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_sdi0: rm-io2-pdm-sdi0 { + rockchip,pins = + <0 RK_PA2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_sdi1: rm-io2-pdm-sdi1 { + rockchip,pins = + <0 RK_PA2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_sdi2: rm-io2-pdm-sdi2 { + rockchip,pins = + <0 RK_PA2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_sdi3: rm-io2-pdm-sdi3 { + rockchip,pins = + <0 RK_PA2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_can1_tx: rm-io2-can1-tx { + rockchip,pins = + <0 RK_PA2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_can1_rx: rm-io2-can1-rx { + rockchip,pins = + <0 RK_PA2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_can0_tx: rm-io2-can0-tx { + rockchip,pins = + <0 RK_PA2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_can0_rx: rm-io2-can0-rx { + rockchip,pins = + <0 RK_PA2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm0_ch0: rm-io2-pwm0-ch0 { + rockchip,pins = + <0 RK_PA2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm0_ch1: rm-io2-pwm0-ch1 { + rockchip,pins = + <0 RK_PA2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm0_ch2: rm-io2-pwm0-ch2 { + rockchip,pins = + <0 RK_PA2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm0_ch3: rm-io2-pwm0-ch3 { + rockchip,pins = + <0 RK_PA2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch0: rm-io2-pwm1-ch0 { + rockchip,pins = + <0 RK_PA2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch1: rm-io2-pwm1-ch1 { + rockchip,pins = + <0 RK_PA2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch2: rm-io2-pwm1-ch2 { + rockchip,pins = + <0 RK_PA2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch3: rm-io2-pwm1-ch3 { + rockchip,pins = + <0 RK_PA2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch4: rm-io2-pwm1-ch4 { + rockchip,pins = + <0 RK_PA2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch5: rm-io2-pwm1-ch5 { + rockchip,pins = + <0 RK_PA2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch6: rm-io2-pwm1-ch6 { + rockchip,pins = + <0 RK_PA2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_ch7: rm-io2-pwm1-ch7 { + rockchip,pins = + <0 RK_PA2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_drive: rm-io2-touch-key-drive { + rockchip,pins = + <0 RK_PA2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in0: rm-io2-touch-key-in0 { + rockchip,pins = + <0 RK_PA2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in1: rm-io2-touch-key-in1 { + rockchip,pins = + <0 RK_PA2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in2: rm-io2-touch-key-in2 { + rockchip,pins = + <0 RK_PA2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in3: rm-io2-touch-key-in3 { + rockchip,pins = + <0 RK_PA2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in4: rm-io2-touch-key-in4 { + rockchip,pins = + <0 RK_PA2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in5: rm-io2-touch-key-in5 { + rockchip,pins = + <0 RK_PA2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in6: rm-io2-touch-key-in6 { + rockchip,pins = + <0 RK_PA2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_touch_key_in7: rm-io2-touch-key-in7 { + rockchip,pins = + <0 RK_PA2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_mclk: rm-io2-sai0-mclk { + rockchip,pins = + <0 RK_PA2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sclk: rm-io2-sai0-sclk { + rockchip,pins = + <0 RK_PA2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_lrck: rm-io2-sai0-lrck { + rockchip,pins = + <0 RK_PA2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sdi0: rm-io2-sai0-sdi0 { + rockchip,pins = + <0 RK_PA2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sdi1: rm-io2-sai0-sdi1 { + rockchip,pins = + <0 RK_PA2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sdi2: rm-io2-sai0-sdi2 { + rockchip,pins = + <0 RK_PA2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sdi3: rm-io2-sai0-sdi3 { + rockchip,pins = + <0 RK_PA2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai0_sdo: rm-io2-sai0-sdo { + rockchip,pins = + <0 RK_PA2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_mclk: rm-io2-sai1-mclk { + rockchip,pins = + <0 RK_PA2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sclk: rm-io2-sai1-sclk { + rockchip,pins = + <0 RK_PA2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_lrck: rm-io2-sai1-lrck { + rockchip,pins = + <0 RK_PA2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sdi: rm-io2-sai1-sdi { + rockchip,pins = + <0 RK_PA2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sdo0: rm-io2-sai1-sdo0 { + rockchip,pins = + <0 RK_PA2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sdo1: rm-io2-sai1-sdo1 { + rockchip,pins = + <0 RK_PA2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sdo2: rm-io2-sai1-sdo2 { + rockchip,pins = + <0 RK_PA2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_sai1_sdo3: rm-io2-sai1-sdo3 { + rockchip,pins = + <0 RK_PA2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi0_clk: rm-io2-spi0-clk { + rockchip,pins = + <0 RK_PA2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi0_mosi: rm-io2-spi0-mosi { + rockchip,pins = + <0 RK_PA2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi0_miso: rm-io2-spi0-miso { + rockchip,pins = + <0 RK_PA2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi0_csn0: rm-io2-spi0-csn0 { + rockchip,pins = + <0 RK_PA2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi0_csn1: rm-io2-spi0-csn1 { + rockchip,pins = + <0 RK_PA2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi1_clk: rm-io2-spi1-clk { + rockchip,pins = + <0 RK_PA2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi1_mosi: rm-io2-spi1-mosi { + rockchip,pins = + <0 RK_PA2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi1_miso: rm-io2-spi1-miso { + rockchip,pins = + <0 RK_PA2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi1_csn0: rm-io2-spi1-csn0 { + rockchip,pins = + <0 RK_PA2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spi1_csn1: rm-io2-spi1-csn1 { + rockchip,pins = + <0 RK_PA2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_wdt_tsadc_shut: rm-io2-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pmu_sleep: rm-io2-pmu-sleep { + rockchip,pins = + <0 RK_PA2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_core_power_off: rm-io2-core-power-off { + rockchip,pins = + <0 RK_PA2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spdif_tx: rm-io2-spdif-tx { + rockchip,pins = + <0 RK_PA2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_spdif_rx: rm-io2-spdif-rx { + rockchip,pins = + <0 RK_PA2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a0: rm-io2-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a1: rm-io2-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a2: rm-io2-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a3: rm-io2-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a4: rm-io2-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_a5: rm-io2-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b0: rm-io2-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b1: rm-io2-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b2: rm-io2-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b3: rm-io2-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b4: rm-io2-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pwm1_bip_cntr_b5: rm-io2-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_pdm_clk1: rm-io2-pdm-clk1 { + rockchip,pins = + <0 RK_PA2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_eth_rmii0_ppsclk: rm-io2-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_eth_rmii0_ppstrig: rm-io2-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_eth_rmii1_ppsclk: rm-io2-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io2_eth_rmii1_ppstrig: rm-io2-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA2 113 &pcfg_pull_none>; + }; + }; + + rm_io3 { + /omit-if-no-ref/ + rm_io3_uart1_tx: rm-io3-uart1-tx { + rockchip,pins = + <0 RK_PA3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart1_rx: rm-io3-uart1-rx { + rockchip,pins = + <0 RK_PA3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io3_uart2_tx: rm-io3-uart2-tx { + rockchip,pins = + <0 RK_PA3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart2_rx: rm-io3-uart2-rx { + rockchip,pins = + <0 RK_PA3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io3_uart3_tx: rm-io3-uart3-tx { + rockchip,pins = + <0 RK_PA3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart3_rx: rm-io3-uart3-rx { + rockchip,pins = + <0 RK_PA3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io3_uart3_ctsn: rm-io3-uart3-ctsn { + rockchip,pins = + <0 RK_PA3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart3_rtsn: rm-io3-uart3-rtsn { + rockchip,pins = + <0 RK_PA3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart4_tx: rm-io3-uart4-tx { + rockchip,pins = + <0 RK_PA3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart4_rx: rm-io3-uart4-rx { + rockchip,pins = + <0 RK_PA3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io3_uart4_ctsn: rm-io3-uart4-ctsn { + rockchip,pins = + <0 RK_PA3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_uart4_rtsn: rm-io3-uart4-rtsn { + rockchip,pins = + <0 RK_PA3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_mipite: rm-io3-mipite { + rockchip,pins = + <0 RK_PA3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_clk_32k: rm-io3-clk-32k { + rockchip,pins = + <0 RK_PA3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c0_scl: rm-io3-i2c0-scl { + rockchip,pins = + <0 RK_PA3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c0_sda: rm-io3-i2c0-sda { + rockchip,pins = + <0 RK_PA3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c1_scl: rm-io3-i2c1-scl { + rockchip,pins = + <0 RK_PA3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c1_sda: rm-io3-i2c1-sda { + rockchip,pins = + <0 RK_PA3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c2_scl: rm-io3-i2c2-scl { + rockchip,pins = + <0 RK_PA3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_i2c2_sda: rm-io3-i2c2-sda { + rockchip,pins = + <0 RK_PA3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_clk0: rm-io3-pdm-clk0 { + rockchip,pins = + <0 RK_PA3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_sdi0: rm-io3-pdm-sdi0 { + rockchip,pins = + <0 RK_PA3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_sdi1: rm-io3-pdm-sdi1 { + rockchip,pins = + <0 RK_PA3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_sdi2: rm-io3-pdm-sdi2 { + rockchip,pins = + <0 RK_PA3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_sdi3: rm-io3-pdm-sdi3 { + rockchip,pins = + <0 RK_PA3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_can1_tx: rm-io3-can1-tx { + rockchip,pins = + <0 RK_PA3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_can1_rx: rm-io3-can1-rx { + rockchip,pins = + <0 RK_PA3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_can0_tx: rm-io3-can0-tx { + rockchip,pins = + <0 RK_PA3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_can0_rx: rm-io3-can0-rx { + rockchip,pins = + <0 RK_PA3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm0_ch0: rm-io3-pwm0-ch0 { + rockchip,pins = + <0 RK_PA3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm0_ch1: rm-io3-pwm0-ch1 { + rockchip,pins = + <0 RK_PA3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm0_ch2: rm-io3-pwm0-ch2 { + rockchip,pins = + <0 RK_PA3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm0_ch3: rm-io3-pwm0-ch3 { + rockchip,pins = + <0 RK_PA3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch0: rm-io3-pwm1-ch0 { + rockchip,pins = + <0 RK_PA3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch1: rm-io3-pwm1-ch1 { + rockchip,pins = + <0 RK_PA3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch2: rm-io3-pwm1-ch2 { + rockchip,pins = + <0 RK_PA3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch3: rm-io3-pwm1-ch3 { + rockchip,pins = + <0 RK_PA3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch4: rm-io3-pwm1-ch4 { + rockchip,pins = + <0 RK_PA3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch5: rm-io3-pwm1-ch5 { + rockchip,pins = + <0 RK_PA3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch6: rm-io3-pwm1-ch6 { + rockchip,pins = + <0 RK_PA3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_ch7: rm-io3-pwm1-ch7 { + rockchip,pins = + <0 RK_PA3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_drive: rm-io3-touch-key-drive { + rockchip,pins = + <0 RK_PA3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in0: rm-io3-touch-key-in0 { + rockchip,pins = + <0 RK_PA3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in1: rm-io3-touch-key-in1 { + rockchip,pins = + <0 RK_PA3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in2: rm-io3-touch-key-in2 { + rockchip,pins = + <0 RK_PA3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in3: rm-io3-touch-key-in3 { + rockchip,pins = + <0 RK_PA3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in4: rm-io3-touch-key-in4 { + rockchip,pins = + <0 RK_PA3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in5: rm-io3-touch-key-in5 { + rockchip,pins = + <0 RK_PA3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in6: rm-io3-touch-key-in6 { + rockchip,pins = + <0 RK_PA3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_touch_key_in7: rm-io3-touch-key-in7 { + rockchip,pins = + <0 RK_PA3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_mclk: rm-io3-sai0-mclk { + rockchip,pins = + <0 RK_PA3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sclk: rm-io3-sai0-sclk { + rockchip,pins = + <0 RK_PA3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_lrck: rm-io3-sai0-lrck { + rockchip,pins = + <0 RK_PA3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sdi0: rm-io3-sai0-sdi0 { + rockchip,pins = + <0 RK_PA3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sdi1: rm-io3-sai0-sdi1 { + rockchip,pins = + <0 RK_PA3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sdi2: rm-io3-sai0-sdi2 { + rockchip,pins = + <0 RK_PA3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sdi3: rm-io3-sai0-sdi3 { + rockchip,pins = + <0 RK_PA3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai0_sdo: rm-io3-sai0-sdo { + rockchip,pins = + <0 RK_PA3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_mclk: rm-io3-sai1-mclk { + rockchip,pins = + <0 RK_PA3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sclk: rm-io3-sai1-sclk { + rockchip,pins = + <0 RK_PA3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_lrck: rm-io3-sai1-lrck { + rockchip,pins = + <0 RK_PA3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sdi: rm-io3-sai1-sdi { + rockchip,pins = + <0 RK_PA3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sdo0: rm-io3-sai1-sdo0 { + rockchip,pins = + <0 RK_PA3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sdo1: rm-io3-sai1-sdo1 { + rockchip,pins = + <0 RK_PA3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sdo2: rm-io3-sai1-sdo2 { + rockchip,pins = + <0 RK_PA3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_sai1_sdo3: rm-io3-sai1-sdo3 { + rockchip,pins = + <0 RK_PA3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi0_clk: rm-io3-spi0-clk { + rockchip,pins = + <0 RK_PA3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi0_mosi: rm-io3-spi0-mosi { + rockchip,pins = + <0 RK_PA3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi0_miso: rm-io3-spi0-miso { + rockchip,pins = + <0 RK_PA3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi0_csn0: rm-io3-spi0-csn0 { + rockchip,pins = + <0 RK_PA3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi0_csn1: rm-io3-spi0-csn1 { + rockchip,pins = + <0 RK_PA3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi1_clk: rm-io3-spi1-clk { + rockchip,pins = + <0 RK_PA3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi1_mosi: rm-io3-spi1-mosi { + rockchip,pins = + <0 RK_PA3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi1_miso: rm-io3-spi1-miso { + rockchip,pins = + <0 RK_PA3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi1_csn0: rm-io3-spi1-csn0 { + rockchip,pins = + <0 RK_PA3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spi1_csn1: rm-io3-spi1-csn1 { + rockchip,pins = + <0 RK_PA3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_wdt_tsadc_shut: rm-io3-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pmu_sleep: rm-io3-pmu-sleep { + rockchip,pins = + <0 RK_PA3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_core_power_off: rm-io3-core-power-off { + rockchip,pins = + <0 RK_PA3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spdif_tx: rm-io3-spdif-tx { + rockchip,pins = + <0 RK_PA3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_spdif_rx: rm-io3-spdif-rx { + rockchip,pins = + <0 RK_PA3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a0: rm-io3-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a1: rm-io3-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a2: rm-io3-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a3: rm-io3-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a4: rm-io3-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_a5: rm-io3-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b0: rm-io3-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b1: rm-io3-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b2: rm-io3-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b3: rm-io3-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b4: rm-io3-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pwm1_bip_cntr_b5: rm-io3-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_pdm_clk1: rm-io3-pdm-clk1 { + rockchip,pins = + <0 RK_PA3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_eth_rmii0_ppsclk: rm-io3-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_eth_rmii0_ppstrig: rm-io3-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_eth_rmii1_ppsclk: rm-io3-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io3_eth_rmii1_ppstrig: rm-io3-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA3 113 &pcfg_pull_none>; + }; + }; + + rm_io4 { + /omit-if-no-ref/ + rm_io4_uart1_tx: rm-io4-uart1-tx { + rockchip,pins = + <0 RK_PA4 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart1_rx: rm-io4-uart1-rx { + rockchip,pins = + <0 RK_PA4 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io4_uart2_tx: rm-io4-uart2-tx { + rockchip,pins = + <0 RK_PA4 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart2_rx: rm-io4-uart2-rx { + rockchip,pins = + <0 RK_PA4 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io4_uart3_tx: rm-io4-uart3-tx { + rockchip,pins = + <0 RK_PA4 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart3_rx: rm-io4-uart3-rx { + rockchip,pins = + <0 RK_PA4 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io4_uart3_ctsn: rm-io4-uart3-ctsn { + rockchip,pins = + <0 RK_PA4 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart3_rtsn: rm-io4-uart3-rtsn { + rockchip,pins = + <0 RK_PA4 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart4_tx: rm-io4-uart4-tx { + rockchip,pins = + <0 RK_PA4 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart4_rx: rm-io4-uart4-rx { + rockchip,pins = + <0 RK_PA4 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io4_uart4_ctsn: rm-io4-uart4-ctsn { + rockchip,pins = + <0 RK_PA4 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_uart4_rtsn: rm-io4-uart4-rtsn { + rockchip,pins = + <0 RK_PA4 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_mipite: rm-io4-mipite { + rockchip,pins = + <0 RK_PA4 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_clk_32k: rm-io4-clk-32k { + rockchip,pins = + <0 RK_PA4 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c0_scl: rm-io4-i2c0-scl { + rockchip,pins = + <0 RK_PA4 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c0_sda: rm-io4-i2c0-sda { + rockchip,pins = + <0 RK_PA4 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c1_scl: rm-io4-i2c1-scl { + rockchip,pins = + <0 RK_PA4 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c1_sda: rm-io4-i2c1-sda { + rockchip,pins = + <0 RK_PA4 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c2_scl: rm-io4-i2c2-scl { + rockchip,pins = + <0 RK_PA4 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_i2c2_sda: rm-io4-i2c2-sda { + rockchip,pins = + <0 RK_PA4 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_clk0: rm-io4-pdm-clk0 { + rockchip,pins = + <0 RK_PA4 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_sdi0: rm-io4-pdm-sdi0 { + rockchip,pins = + <0 RK_PA4 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_sdi1: rm-io4-pdm-sdi1 { + rockchip,pins = + <0 RK_PA4 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_sdi2: rm-io4-pdm-sdi2 { + rockchip,pins = + <0 RK_PA4 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_sdi3: rm-io4-pdm-sdi3 { + rockchip,pins = + <0 RK_PA4 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_can1_tx: rm-io4-can1-tx { + rockchip,pins = + <0 RK_PA4 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_can1_rx: rm-io4-can1-rx { + rockchip,pins = + <0 RK_PA4 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_can0_tx: rm-io4-can0-tx { + rockchip,pins = + <0 RK_PA4 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_can0_rx: rm-io4-can0-rx { + rockchip,pins = + <0 RK_PA4 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm0_ch0: rm-io4-pwm0-ch0 { + rockchip,pins = + <0 RK_PA4 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm0_ch1: rm-io4-pwm0-ch1 { + rockchip,pins = + <0 RK_PA4 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm0_ch2: rm-io4-pwm0-ch2 { + rockchip,pins = + <0 RK_PA4 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm0_ch3: rm-io4-pwm0-ch3 { + rockchip,pins = + <0 RK_PA4 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch0: rm-io4-pwm1-ch0 { + rockchip,pins = + <0 RK_PA4 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch1: rm-io4-pwm1-ch1 { + rockchip,pins = + <0 RK_PA4 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch2: rm-io4-pwm1-ch2 { + rockchip,pins = + <0 RK_PA4 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch3: rm-io4-pwm1-ch3 { + rockchip,pins = + <0 RK_PA4 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch4: rm-io4-pwm1-ch4 { + rockchip,pins = + <0 RK_PA4 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch5: rm-io4-pwm1-ch5 { + rockchip,pins = + <0 RK_PA4 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch6: rm-io4-pwm1-ch6 { + rockchip,pins = + <0 RK_PA4 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_ch7: rm-io4-pwm1-ch7 { + rockchip,pins = + <0 RK_PA4 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_drive: rm-io4-touch-key-drive { + rockchip,pins = + <0 RK_PA4 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in0: rm-io4-touch-key-in0 { + rockchip,pins = + <0 RK_PA4 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in1: rm-io4-touch-key-in1 { + rockchip,pins = + <0 RK_PA4 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in2: rm-io4-touch-key-in2 { + rockchip,pins = + <0 RK_PA4 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in3: rm-io4-touch-key-in3 { + rockchip,pins = + <0 RK_PA4 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in4: rm-io4-touch-key-in4 { + rockchip,pins = + <0 RK_PA4 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in5: rm-io4-touch-key-in5 { + rockchip,pins = + <0 RK_PA4 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in6: rm-io4-touch-key-in6 { + rockchip,pins = + <0 RK_PA4 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_touch_key_in7: rm-io4-touch-key-in7 { + rockchip,pins = + <0 RK_PA4 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_mclk: rm-io4-sai0-mclk { + rockchip,pins = + <0 RK_PA4 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sclk: rm-io4-sai0-sclk { + rockchip,pins = + <0 RK_PA4 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_lrck: rm-io4-sai0-lrck { + rockchip,pins = + <0 RK_PA4 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sdi0: rm-io4-sai0-sdi0 { + rockchip,pins = + <0 RK_PA4 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sdi1: rm-io4-sai0-sdi1 { + rockchip,pins = + <0 RK_PA4 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sdi2: rm-io4-sai0-sdi2 { + rockchip,pins = + <0 RK_PA4 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sdi3: rm-io4-sai0-sdi3 { + rockchip,pins = + <0 RK_PA4 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai0_sdo: rm-io4-sai0-sdo { + rockchip,pins = + <0 RK_PA4 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_mclk: rm-io4-sai1-mclk { + rockchip,pins = + <0 RK_PA4 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sclk: rm-io4-sai1-sclk { + rockchip,pins = + <0 RK_PA4 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_lrck: rm-io4-sai1-lrck { + rockchip,pins = + <0 RK_PA4 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sdi: rm-io4-sai1-sdi { + rockchip,pins = + <0 RK_PA4 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sdo0: rm-io4-sai1-sdo0 { + rockchip,pins = + <0 RK_PA4 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sdo1: rm-io4-sai1-sdo1 { + rockchip,pins = + <0 RK_PA4 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sdo2: rm-io4-sai1-sdo2 { + rockchip,pins = + <0 RK_PA4 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_sai1_sdo3: rm-io4-sai1-sdo3 { + rockchip,pins = + <0 RK_PA4 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi0_clk: rm-io4-spi0-clk { + rockchip,pins = + <0 RK_PA4 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi0_mosi: rm-io4-spi0-mosi { + rockchip,pins = + <0 RK_PA4 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi0_miso: rm-io4-spi0-miso { + rockchip,pins = + <0 RK_PA4 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi0_csn0: rm-io4-spi0-csn0 { + rockchip,pins = + <0 RK_PA4 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi0_csn1: rm-io4-spi0-csn1 { + rockchip,pins = + <0 RK_PA4 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi1_clk: rm-io4-spi1-clk { + rockchip,pins = + <0 RK_PA4 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi1_mosi: rm-io4-spi1-mosi { + rockchip,pins = + <0 RK_PA4 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi1_miso: rm-io4-spi1-miso { + rockchip,pins = + <0 RK_PA4 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi1_csn0: rm-io4-spi1-csn0 { + rockchip,pins = + <0 RK_PA4 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spi1_csn1: rm-io4-spi1-csn1 { + rockchip,pins = + <0 RK_PA4 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_wdt_tsadc_shut: rm-io4-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA4 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pmu_sleep: rm-io4-pmu-sleep { + rockchip,pins = + <0 RK_PA4 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_core_power_off: rm-io4-core-power-off { + rockchip,pins = + <0 RK_PA4 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spdif_tx: rm-io4-spdif-tx { + rockchip,pins = + <0 RK_PA4 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_spdif_rx: rm-io4-spdif-rx { + rockchip,pins = + <0 RK_PA4 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a0: rm-io4-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA4 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a1: rm-io4-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA4 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a2: rm-io4-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA4 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a3: rm-io4-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA4 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a4: rm-io4-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA4 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_a5: rm-io4-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA4 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b0: rm-io4-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA4 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b1: rm-io4-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA4 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b2: rm-io4-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA4 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b3: rm-io4-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA4 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b4: rm-io4-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA4 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pwm1_bip_cntr_b5: rm-io4-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA4 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_pdm_clk1: rm-io4-pdm-clk1 { + rockchip,pins = + <0 RK_PA4 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_eth_rmii0_ppsclk: rm-io4-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA4 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_eth_rmii0_ppstrig: rm-io4-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA4 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_eth_rmii1_ppsclk: rm-io4-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA4 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io4_eth_rmii1_ppstrig: rm-io4-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA4 113 &pcfg_pull_none>; + }; + }; + + rm_io5 { + /omit-if-no-ref/ + rm_io5_uart1_tx: rm-io5-uart1-tx { + rockchip,pins = + <0 RK_PA5 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart1_rx: rm-io5-uart1-rx { + rockchip,pins = + <0 RK_PA5 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io5_uart2_tx: rm-io5-uart2-tx { + rockchip,pins = + <0 RK_PA5 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart2_rx: rm-io5-uart2-rx { + rockchip,pins = + <0 RK_PA5 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io5_uart3_tx: rm-io5-uart3-tx { + rockchip,pins = + <0 RK_PA5 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart3_rx: rm-io5-uart3-rx { + rockchip,pins = + <0 RK_PA5 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io5_uart3_ctsn: rm-io5-uart3-ctsn { + rockchip,pins = + <0 RK_PA5 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart3_rtsn: rm-io5-uart3-rtsn { + rockchip,pins = + <0 RK_PA5 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart4_tx: rm-io5-uart4-tx { + rockchip,pins = + <0 RK_PA5 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart4_rx: rm-io5-uart4-rx { + rockchip,pins = + <0 RK_PA5 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io5_uart4_ctsn: rm-io5-uart4-ctsn { + rockchip,pins = + <0 RK_PA5 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_uart4_rtsn: rm-io5-uart4-rtsn { + rockchip,pins = + <0 RK_PA5 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_mipite: rm-io5-mipite { + rockchip,pins = + <0 RK_PA5 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_clk_32k: rm-io5-clk-32k { + rockchip,pins = + <0 RK_PA5 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c0_scl: rm-io5-i2c0-scl { + rockchip,pins = + <0 RK_PA5 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c0_sda: rm-io5-i2c0-sda { + rockchip,pins = + <0 RK_PA5 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c1_scl: rm-io5-i2c1-scl { + rockchip,pins = + <0 RK_PA5 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c1_sda: rm-io5-i2c1-sda { + rockchip,pins = + <0 RK_PA5 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c2_scl: rm-io5-i2c2-scl { + rockchip,pins = + <0 RK_PA5 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_i2c2_sda: rm-io5-i2c2-sda { + rockchip,pins = + <0 RK_PA5 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_clk0: rm-io5-pdm-clk0 { + rockchip,pins = + <0 RK_PA5 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_sdi0: rm-io5-pdm-sdi0 { + rockchip,pins = + <0 RK_PA5 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_sdi1: rm-io5-pdm-sdi1 { + rockchip,pins = + <0 RK_PA5 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_sdi2: rm-io5-pdm-sdi2 { + rockchip,pins = + <0 RK_PA5 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_sdi3: rm-io5-pdm-sdi3 { + rockchip,pins = + <0 RK_PA5 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_can1_tx: rm-io5-can1-tx { + rockchip,pins = + <0 RK_PA5 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_can1_rx: rm-io5-can1-rx { + rockchip,pins = + <0 RK_PA5 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_can0_tx: rm-io5-can0-tx { + rockchip,pins = + <0 RK_PA5 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_can0_rx: rm-io5-can0-rx { + rockchip,pins = + <0 RK_PA5 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm0_ch0: rm-io5-pwm0-ch0 { + rockchip,pins = + <0 RK_PA5 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm0_ch1: rm-io5-pwm0-ch1 { + rockchip,pins = + <0 RK_PA5 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm0_ch2: rm-io5-pwm0-ch2 { + rockchip,pins = + <0 RK_PA5 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm0_ch3: rm-io5-pwm0-ch3 { + rockchip,pins = + <0 RK_PA5 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch0: rm-io5-pwm1-ch0 { + rockchip,pins = + <0 RK_PA5 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch1: rm-io5-pwm1-ch1 { + rockchip,pins = + <0 RK_PA5 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch2: rm-io5-pwm1-ch2 { + rockchip,pins = + <0 RK_PA5 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch3: rm-io5-pwm1-ch3 { + rockchip,pins = + <0 RK_PA5 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch4: rm-io5-pwm1-ch4 { + rockchip,pins = + <0 RK_PA5 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch5: rm-io5-pwm1-ch5 { + rockchip,pins = + <0 RK_PA5 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch6: rm-io5-pwm1-ch6 { + rockchip,pins = + <0 RK_PA5 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_ch7: rm-io5-pwm1-ch7 { + rockchip,pins = + <0 RK_PA5 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_drive: rm-io5-touch-key-drive { + rockchip,pins = + <0 RK_PA5 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in0: rm-io5-touch-key-in0 { + rockchip,pins = + <0 RK_PA5 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in1: rm-io5-touch-key-in1 { + rockchip,pins = + <0 RK_PA5 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in2: rm-io5-touch-key-in2 { + rockchip,pins = + <0 RK_PA5 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in3: rm-io5-touch-key-in3 { + rockchip,pins = + <0 RK_PA5 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in4: rm-io5-touch-key-in4 { + rockchip,pins = + <0 RK_PA5 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in5: rm-io5-touch-key-in5 { + rockchip,pins = + <0 RK_PA5 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in6: rm-io5-touch-key-in6 { + rockchip,pins = + <0 RK_PA5 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_touch_key_in7: rm-io5-touch-key-in7 { + rockchip,pins = + <0 RK_PA5 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_mclk: rm-io5-sai0-mclk { + rockchip,pins = + <0 RK_PA5 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sclk: rm-io5-sai0-sclk { + rockchip,pins = + <0 RK_PA5 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_lrck: rm-io5-sai0-lrck { + rockchip,pins = + <0 RK_PA5 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sdi0: rm-io5-sai0-sdi0 { + rockchip,pins = + <0 RK_PA5 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sdi1: rm-io5-sai0-sdi1 { + rockchip,pins = + <0 RK_PA5 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sdi2: rm-io5-sai0-sdi2 { + rockchip,pins = + <0 RK_PA5 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sdi3: rm-io5-sai0-sdi3 { + rockchip,pins = + <0 RK_PA5 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai0_sdo: rm-io5-sai0-sdo { + rockchip,pins = + <0 RK_PA5 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_mclk: rm-io5-sai1-mclk { + rockchip,pins = + <0 RK_PA5 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sclk: rm-io5-sai1-sclk { + rockchip,pins = + <0 RK_PA5 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_lrck: rm-io5-sai1-lrck { + rockchip,pins = + <0 RK_PA5 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sdi: rm-io5-sai1-sdi { + rockchip,pins = + <0 RK_PA5 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sdo0: rm-io5-sai1-sdo0 { + rockchip,pins = + <0 RK_PA5 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sdo1: rm-io5-sai1-sdo1 { + rockchip,pins = + <0 RK_PA5 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sdo2: rm-io5-sai1-sdo2 { + rockchip,pins = + <0 RK_PA5 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_sai1_sdo3: rm-io5-sai1-sdo3 { + rockchip,pins = + <0 RK_PA5 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi0_clk: rm-io5-spi0-clk { + rockchip,pins = + <0 RK_PA5 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi0_mosi: rm-io5-spi0-mosi { + rockchip,pins = + <0 RK_PA5 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi0_miso: rm-io5-spi0-miso { + rockchip,pins = + <0 RK_PA5 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi0_csn0: rm-io5-spi0-csn0 { + rockchip,pins = + <0 RK_PA5 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi0_csn1: rm-io5-spi0-csn1 { + rockchip,pins = + <0 RK_PA5 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi1_clk: rm-io5-spi1-clk { + rockchip,pins = + <0 RK_PA5 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi1_mosi: rm-io5-spi1-mosi { + rockchip,pins = + <0 RK_PA5 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi1_miso: rm-io5-spi1-miso { + rockchip,pins = + <0 RK_PA5 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi1_csn0: rm-io5-spi1-csn0 { + rockchip,pins = + <0 RK_PA5 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spi1_csn1: rm-io5-spi1-csn1 { + rockchip,pins = + <0 RK_PA5 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_wdt_tsadc_shut: rm-io5-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA5 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pmu_sleep: rm-io5-pmu-sleep { + rockchip,pins = + <0 RK_PA5 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_core_power_off: rm-io5-core-power-off { + rockchip,pins = + <0 RK_PA5 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spdif_tx: rm-io5-spdif-tx { + rockchip,pins = + <0 RK_PA5 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_spdif_rx: rm-io5-spdif-rx { + rockchip,pins = + <0 RK_PA5 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a0: rm-io5-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA5 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a1: rm-io5-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA5 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a2: rm-io5-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA5 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a3: rm-io5-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA5 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a4: rm-io5-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA5 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_a5: rm-io5-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA5 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b0: rm-io5-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA5 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b1: rm-io5-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA5 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b2: rm-io5-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA5 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b3: rm-io5-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA5 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b4: rm-io5-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA5 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pwm1_bip_cntr_b5: rm-io5-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA5 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_pdm_clk1: rm-io5-pdm-clk1 { + rockchip,pins = + <0 RK_PA5 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_eth_rmii0_ppsclk: rm-io5-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA5 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_eth_rmii0_ppstrig: rm-io5-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA5 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_eth_rmii1_ppsclk: rm-io5-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA5 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io5_eth_rmii1_ppstrig: rm-io5-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA5 113 &pcfg_pull_none>; + }; + }; + + rm_io6 { + /omit-if-no-ref/ + rm_io6_uart1_tx: rm-io6-uart1-tx { + rockchip,pins = + <0 RK_PA6 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart1_rx: rm-io6-uart1-rx { + rockchip,pins = + <0 RK_PA6 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io6_uart2_tx: rm-io6-uart2-tx { + rockchip,pins = + <0 RK_PA6 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart2_rx: rm-io6-uart2-rx { + rockchip,pins = + <0 RK_PA6 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io6_uart3_tx: rm-io6-uart3-tx { + rockchip,pins = + <0 RK_PA6 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart3_rx: rm-io6-uart3-rx { + rockchip,pins = + <0 RK_PA6 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io6_uart3_ctsn: rm-io6-uart3-ctsn { + rockchip,pins = + <0 RK_PA6 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart3_rtsn: rm-io6-uart3-rtsn { + rockchip,pins = + <0 RK_PA6 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart4_tx: rm-io6-uart4-tx { + rockchip,pins = + <0 RK_PA6 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart4_rx: rm-io6-uart4-rx { + rockchip,pins = + <0 RK_PA6 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io6_uart4_ctsn: rm-io6-uart4-ctsn { + rockchip,pins = + <0 RK_PA6 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_uart4_rtsn: rm-io6-uart4-rtsn { + rockchip,pins = + <0 RK_PA6 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_mipite: rm-io6-mipite { + rockchip,pins = + <0 RK_PA6 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_clk_32k: rm-io6-clk-32k { + rockchip,pins = + <0 RK_PA6 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c0_scl: rm-io6-i2c0-scl { + rockchip,pins = + <0 RK_PA6 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c0_sda: rm-io6-i2c0-sda { + rockchip,pins = + <0 RK_PA6 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c1_scl: rm-io6-i2c1-scl { + rockchip,pins = + <0 RK_PA6 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c1_sda: rm-io6-i2c1-sda { + rockchip,pins = + <0 RK_PA6 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c2_scl: rm-io6-i2c2-scl { + rockchip,pins = + <0 RK_PA6 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_i2c2_sda: rm-io6-i2c2-sda { + rockchip,pins = + <0 RK_PA6 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_clk0: rm-io6-pdm-clk0 { + rockchip,pins = + <0 RK_PA6 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_sdi0: rm-io6-pdm-sdi0 { + rockchip,pins = + <0 RK_PA6 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_sdi1: rm-io6-pdm-sdi1 { + rockchip,pins = + <0 RK_PA6 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_sdi2: rm-io6-pdm-sdi2 { + rockchip,pins = + <0 RK_PA6 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_sdi3: rm-io6-pdm-sdi3 { + rockchip,pins = + <0 RK_PA6 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_can1_tx: rm-io6-can1-tx { + rockchip,pins = + <0 RK_PA6 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_can1_rx: rm-io6-can1-rx { + rockchip,pins = + <0 RK_PA6 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_can0_tx: rm-io6-can0-tx { + rockchip,pins = + <0 RK_PA6 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_can0_rx: rm-io6-can0-rx { + rockchip,pins = + <0 RK_PA6 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm0_ch0: rm-io6-pwm0-ch0 { + rockchip,pins = + <0 RK_PA6 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm0_ch1: rm-io6-pwm0-ch1 { + rockchip,pins = + <0 RK_PA6 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm0_ch2: rm-io6-pwm0-ch2 { + rockchip,pins = + <0 RK_PA6 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm0_ch3: rm-io6-pwm0-ch3 { + rockchip,pins = + <0 RK_PA6 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch0: rm-io6-pwm1-ch0 { + rockchip,pins = + <0 RK_PA6 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch1: rm-io6-pwm1-ch1 { + rockchip,pins = + <0 RK_PA6 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch2: rm-io6-pwm1-ch2 { + rockchip,pins = + <0 RK_PA6 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch3: rm-io6-pwm1-ch3 { + rockchip,pins = + <0 RK_PA6 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch4: rm-io6-pwm1-ch4 { + rockchip,pins = + <0 RK_PA6 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch5: rm-io6-pwm1-ch5 { + rockchip,pins = + <0 RK_PA6 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch6: rm-io6-pwm1-ch6 { + rockchip,pins = + <0 RK_PA6 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_ch7: rm-io6-pwm1-ch7 { + rockchip,pins = + <0 RK_PA6 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_drive: rm-io6-touch-key-drive { + rockchip,pins = + <0 RK_PA6 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in0: rm-io6-touch-key-in0 { + rockchip,pins = + <0 RK_PA6 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in1: rm-io6-touch-key-in1 { + rockchip,pins = + <0 RK_PA6 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in2: rm-io6-touch-key-in2 { + rockchip,pins = + <0 RK_PA6 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in3: rm-io6-touch-key-in3 { + rockchip,pins = + <0 RK_PA6 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in4: rm-io6-touch-key-in4 { + rockchip,pins = + <0 RK_PA6 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in5: rm-io6-touch-key-in5 { + rockchip,pins = + <0 RK_PA6 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in6: rm-io6-touch-key-in6 { + rockchip,pins = + <0 RK_PA6 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_touch_key_in7: rm-io6-touch-key-in7 { + rockchip,pins = + <0 RK_PA6 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_mclk: rm-io6-sai0-mclk { + rockchip,pins = + <0 RK_PA6 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sclk: rm-io6-sai0-sclk { + rockchip,pins = + <0 RK_PA6 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_lrck: rm-io6-sai0-lrck { + rockchip,pins = + <0 RK_PA6 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sdi0: rm-io6-sai0-sdi0 { + rockchip,pins = + <0 RK_PA6 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sdi1: rm-io6-sai0-sdi1 { + rockchip,pins = + <0 RK_PA6 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sdi2: rm-io6-sai0-sdi2 { + rockchip,pins = + <0 RK_PA6 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sdi3: rm-io6-sai0-sdi3 { + rockchip,pins = + <0 RK_PA6 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai0_sdo: rm-io6-sai0-sdo { + rockchip,pins = + <0 RK_PA6 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_mclk: rm-io6-sai1-mclk { + rockchip,pins = + <0 RK_PA6 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sclk: rm-io6-sai1-sclk { + rockchip,pins = + <0 RK_PA6 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_lrck: rm-io6-sai1-lrck { + rockchip,pins = + <0 RK_PA6 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sdi: rm-io6-sai1-sdi { + rockchip,pins = + <0 RK_PA6 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sdo0: rm-io6-sai1-sdo0 { + rockchip,pins = + <0 RK_PA6 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sdo1: rm-io6-sai1-sdo1 { + rockchip,pins = + <0 RK_PA6 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sdo2: rm-io6-sai1-sdo2 { + rockchip,pins = + <0 RK_PA6 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_sai1_sdo3: rm-io6-sai1-sdo3 { + rockchip,pins = + <0 RK_PA6 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi0_clk: rm-io6-spi0-clk { + rockchip,pins = + <0 RK_PA6 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi0_mosi: rm-io6-spi0-mosi { + rockchip,pins = + <0 RK_PA6 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi0_miso: rm-io6-spi0-miso { + rockchip,pins = + <0 RK_PA6 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi0_csn0: rm-io6-spi0-csn0 { + rockchip,pins = + <0 RK_PA6 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi0_csn1: rm-io6-spi0-csn1 { + rockchip,pins = + <0 RK_PA6 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi1_clk: rm-io6-spi1-clk { + rockchip,pins = + <0 RK_PA6 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi1_mosi: rm-io6-spi1-mosi { + rockchip,pins = + <0 RK_PA6 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi1_miso: rm-io6-spi1-miso { + rockchip,pins = + <0 RK_PA6 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi1_csn0: rm-io6-spi1-csn0 { + rockchip,pins = + <0 RK_PA6 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spi1_csn1: rm-io6-spi1-csn1 { + rockchip,pins = + <0 RK_PA6 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_wdt_tsadc_shut: rm-io6-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA6 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pmu_sleep: rm-io6-pmu-sleep { + rockchip,pins = + <0 RK_PA6 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_core_power_off: rm-io6-core-power-off { + rockchip,pins = + <0 RK_PA6 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spdif_tx: rm-io6-spdif-tx { + rockchip,pins = + <0 RK_PA6 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_spdif_rx: rm-io6-spdif-rx { + rockchip,pins = + <0 RK_PA6 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a0: rm-io6-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA6 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a1: rm-io6-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA6 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a2: rm-io6-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA6 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a3: rm-io6-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA6 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a4: rm-io6-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA6 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_a5: rm-io6-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA6 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b0: rm-io6-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA6 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b1: rm-io6-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA6 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b2: rm-io6-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA6 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b3: rm-io6-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA6 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b4: rm-io6-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA6 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pwm1_bip_cntr_b5: rm-io6-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA6 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_pdm_clk1: rm-io6-pdm-clk1 { + rockchip,pins = + <0 RK_PA6 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_eth_rmii0_ppsclk: rm-io6-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA6 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_eth_rmii0_ppstrig: rm-io6-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA6 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_eth_rmii1_ppsclk: rm-io6-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA6 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io6_eth_rmii1_ppstrig: rm-io6-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA6 113 &pcfg_pull_none>; + }; + }; + + rm_io7 { + /omit-if-no-ref/ + rm_io7_uart1_tx: rm-io7-uart1-tx { + rockchip,pins = + <0 RK_PA7 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart1_rx: rm-io7-uart1-rx { + rockchip,pins = + <0 RK_PA7 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io7_uart2_tx: rm-io7-uart2-tx { + rockchip,pins = + <0 RK_PA7 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart2_rx: rm-io7-uart2-rx { + rockchip,pins = + <0 RK_PA7 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io7_uart3_tx: rm-io7-uart3-tx { + rockchip,pins = + <0 RK_PA7 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart3_rx: rm-io7-uart3-rx { + rockchip,pins = + <0 RK_PA7 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io7_uart3_ctsn: rm-io7-uart3-ctsn { + rockchip,pins = + <0 RK_PA7 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart3_rtsn: rm-io7-uart3-rtsn { + rockchip,pins = + <0 RK_PA7 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart4_tx: rm-io7-uart4-tx { + rockchip,pins = + <0 RK_PA7 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart4_rx: rm-io7-uart4-rx { + rockchip,pins = + <0 RK_PA7 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io7_uart4_ctsn: rm-io7-uart4-ctsn { + rockchip,pins = + <0 RK_PA7 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_uart4_rtsn: rm-io7-uart4-rtsn { + rockchip,pins = + <0 RK_PA7 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_mipite: rm-io7-mipite { + rockchip,pins = + <0 RK_PA7 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_clk_32k: rm-io7-clk-32k { + rockchip,pins = + <0 RK_PA7 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c0_scl: rm-io7-i2c0-scl { + rockchip,pins = + <0 RK_PA7 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c0_sda: rm-io7-i2c0-sda { + rockchip,pins = + <0 RK_PA7 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c1_scl: rm-io7-i2c1-scl { + rockchip,pins = + <0 RK_PA7 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c1_sda: rm-io7-i2c1-sda { + rockchip,pins = + <0 RK_PA7 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c2_scl: rm-io7-i2c2-scl { + rockchip,pins = + <0 RK_PA7 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_i2c2_sda: rm-io7-i2c2-sda { + rockchip,pins = + <0 RK_PA7 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_clk0: rm-io7-pdm-clk0 { + rockchip,pins = + <0 RK_PA7 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_sdi0: rm-io7-pdm-sdi0 { + rockchip,pins = + <0 RK_PA7 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_sdi1: rm-io7-pdm-sdi1 { + rockchip,pins = + <0 RK_PA7 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_sdi2: rm-io7-pdm-sdi2 { + rockchip,pins = + <0 RK_PA7 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_sdi3: rm-io7-pdm-sdi3 { + rockchip,pins = + <0 RK_PA7 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_can1_tx: rm-io7-can1-tx { + rockchip,pins = + <0 RK_PA7 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_can1_rx: rm-io7-can1-rx { + rockchip,pins = + <0 RK_PA7 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_can0_tx: rm-io7-can0-tx { + rockchip,pins = + <0 RK_PA7 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_can0_rx: rm-io7-can0-rx { + rockchip,pins = + <0 RK_PA7 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm0_ch0: rm-io7-pwm0-ch0 { + rockchip,pins = + <0 RK_PA7 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm0_ch1: rm-io7-pwm0-ch1 { + rockchip,pins = + <0 RK_PA7 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm0_ch2: rm-io7-pwm0-ch2 { + rockchip,pins = + <0 RK_PA7 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm0_ch3: rm-io7-pwm0-ch3 { + rockchip,pins = + <0 RK_PA7 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch0: rm-io7-pwm1-ch0 { + rockchip,pins = + <0 RK_PA7 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch1: rm-io7-pwm1-ch1 { + rockchip,pins = + <0 RK_PA7 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch2: rm-io7-pwm1-ch2 { + rockchip,pins = + <0 RK_PA7 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch3: rm-io7-pwm1-ch3 { + rockchip,pins = + <0 RK_PA7 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch4: rm-io7-pwm1-ch4 { + rockchip,pins = + <0 RK_PA7 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch5: rm-io7-pwm1-ch5 { + rockchip,pins = + <0 RK_PA7 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch6: rm-io7-pwm1-ch6 { + rockchip,pins = + <0 RK_PA7 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_ch7: rm-io7-pwm1-ch7 { + rockchip,pins = + <0 RK_PA7 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_drive: rm-io7-touch-key-drive { + rockchip,pins = + <0 RK_PA7 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in0: rm-io7-touch-key-in0 { + rockchip,pins = + <0 RK_PA7 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in1: rm-io7-touch-key-in1 { + rockchip,pins = + <0 RK_PA7 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in2: rm-io7-touch-key-in2 { + rockchip,pins = + <0 RK_PA7 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in3: rm-io7-touch-key-in3 { + rockchip,pins = + <0 RK_PA7 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in4: rm-io7-touch-key-in4 { + rockchip,pins = + <0 RK_PA7 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in5: rm-io7-touch-key-in5 { + rockchip,pins = + <0 RK_PA7 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in6: rm-io7-touch-key-in6 { + rockchip,pins = + <0 RK_PA7 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_touch_key_in7: rm-io7-touch-key-in7 { + rockchip,pins = + <0 RK_PA7 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_mclk: rm-io7-sai0-mclk { + rockchip,pins = + <0 RK_PA7 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sclk: rm-io7-sai0-sclk { + rockchip,pins = + <0 RK_PA7 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_lrck: rm-io7-sai0-lrck { + rockchip,pins = + <0 RK_PA7 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sdi0: rm-io7-sai0-sdi0 { + rockchip,pins = + <0 RK_PA7 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sdi1: rm-io7-sai0-sdi1 { + rockchip,pins = + <0 RK_PA7 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sdi2: rm-io7-sai0-sdi2 { + rockchip,pins = + <0 RK_PA7 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sdi3: rm-io7-sai0-sdi3 { + rockchip,pins = + <0 RK_PA7 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai0_sdo: rm-io7-sai0-sdo { + rockchip,pins = + <0 RK_PA7 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_mclk: rm-io7-sai1-mclk { + rockchip,pins = + <0 RK_PA7 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sclk: rm-io7-sai1-sclk { + rockchip,pins = + <0 RK_PA7 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_lrck: rm-io7-sai1-lrck { + rockchip,pins = + <0 RK_PA7 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sdi: rm-io7-sai1-sdi { + rockchip,pins = + <0 RK_PA7 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sdo0: rm-io7-sai1-sdo0 { + rockchip,pins = + <0 RK_PA7 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sdo1: rm-io7-sai1-sdo1 { + rockchip,pins = + <0 RK_PA7 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sdo2: rm-io7-sai1-sdo2 { + rockchip,pins = + <0 RK_PA7 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_sai1_sdo3: rm-io7-sai1-sdo3 { + rockchip,pins = + <0 RK_PA7 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi0_clk: rm-io7-spi0-clk { + rockchip,pins = + <0 RK_PA7 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi0_mosi: rm-io7-spi0-mosi { + rockchip,pins = + <0 RK_PA7 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi0_miso: rm-io7-spi0-miso { + rockchip,pins = + <0 RK_PA7 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi0_csn0: rm-io7-spi0-csn0 { + rockchip,pins = + <0 RK_PA7 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi0_csn1: rm-io7-spi0-csn1 { + rockchip,pins = + <0 RK_PA7 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi1_clk: rm-io7-spi1-clk { + rockchip,pins = + <0 RK_PA7 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi1_mosi: rm-io7-spi1-mosi { + rockchip,pins = + <0 RK_PA7 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi1_miso: rm-io7-spi1-miso { + rockchip,pins = + <0 RK_PA7 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi1_csn0: rm-io7-spi1-csn0 { + rockchip,pins = + <0 RK_PA7 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spi1_csn1: rm-io7-spi1-csn1 { + rockchip,pins = + <0 RK_PA7 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_wdt_tsadc_shut: rm-io7-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PA7 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pmu_sleep: rm-io7-pmu-sleep { + rockchip,pins = + <0 RK_PA7 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_core_power_off: rm-io7-core-power-off { + rockchip,pins = + <0 RK_PA7 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spdif_tx: rm-io7-spdif-tx { + rockchip,pins = + <0 RK_PA7 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_spdif_rx: rm-io7-spdif-rx { + rockchip,pins = + <0 RK_PA7 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a0: rm-io7-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PA7 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a1: rm-io7-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PA7 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a2: rm-io7-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PA7 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a3: rm-io7-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PA7 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a4: rm-io7-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PA7 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_a5: rm-io7-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PA7 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b0: rm-io7-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PA7 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b1: rm-io7-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PA7 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b2: rm-io7-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PA7 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b3: rm-io7-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PA7 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b4: rm-io7-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PA7 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pwm1_bip_cntr_b5: rm-io7-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PA7 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_pdm_clk1: rm-io7-pdm-clk1 { + rockchip,pins = + <0 RK_PA7 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_eth_rmii0_ppsclk: rm-io7-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PA7 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_eth_rmii0_ppstrig: rm-io7-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PA7 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_eth_rmii1_ppsclk: rm-io7-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PA7 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io7_eth_rmii1_ppstrig: rm-io7-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PA7 113 &pcfg_pull_none>; + }; + }; + + rm_io8 { + /omit-if-no-ref/ + rm_io8_uart1_tx: rm-io8-uart1-tx { + rockchip,pins = + <0 RK_PB0 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart1_rx: rm-io8-uart1-rx { + rockchip,pins = + <0 RK_PB0 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io8_uart2_tx: rm-io8-uart2-tx { + rockchip,pins = + <0 RK_PB0 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart2_rx: rm-io8-uart2-rx { + rockchip,pins = + <0 RK_PB0 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io8_uart3_tx: rm-io8-uart3-tx { + rockchip,pins = + <0 RK_PB0 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart3_rx: rm-io8-uart3-rx { + rockchip,pins = + <0 RK_PB0 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io8_uart3_ctsn: rm-io8-uart3-ctsn { + rockchip,pins = + <0 RK_PB0 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart3_rtsn: rm-io8-uart3-rtsn { + rockchip,pins = + <0 RK_PB0 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart4_tx: rm-io8-uart4-tx { + rockchip,pins = + <0 RK_PB0 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart4_rx: rm-io8-uart4-rx { + rockchip,pins = + <0 RK_PB0 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io8_uart4_ctsn: rm-io8-uart4-ctsn { + rockchip,pins = + <0 RK_PB0 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_uart4_rtsn: rm-io8-uart4-rtsn { + rockchip,pins = + <0 RK_PB0 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_mipite: rm-io8-mipite { + rockchip,pins = + <0 RK_PB0 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_clk_32k: rm-io8-clk-32k { + rockchip,pins = + <0 RK_PB0 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c0_scl: rm-io8-i2c0-scl { + rockchip,pins = + <0 RK_PB0 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c0_sda: rm-io8-i2c0-sda { + rockchip,pins = + <0 RK_PB0 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c1_scl: rm-io8-i2c1-scl { + rockchip,pins = + <0 RK_PB0 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c1_sda: rm-io8-i2c1-sda { + rockchip,pins = + <0 RK_PB0 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c2_scl: rm-io8-i2c2-scl { + rockchip,pins = + <0 RK_PB0 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_i2c2_sda: rm-io8-i2c2-sda { + rockchip,pins = + <0 RK_PB0 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_clk0: rm-io8-pdm-clk0 { + rockchip,pins = + <0 RK_PB0 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_sdi0: rm-io8-pdm-sdi0 { + rockchip,pins = + <0 RK_PB0 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_sdi1: rm-io8-pdm-sdi1 { + rockchip,pins = + <0 RK_PB0 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_sdi2: rm-io8-pdm-sdi2 { + rockchip,pins = + <0 RK_PB0 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_sdi3: rm-io8-pdm-sdi3 { + rockchip,pins = + <0 RK_PB0 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_can1_tx: rm-io8-can1-tx { + rockchip,pins = + <0 RK_PB0 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_can1_rx: rm-io8-can1-rx { + rockchip,pins = + <0 RK_PB0 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_can0_tx: rm-io8-can0-tx { + rockchip,pins = + <0 RK_PB0 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_can0_rx: rm-io8-can0-rx { + rockchip,pins = + <0 RK_PB0 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm0_ch0: rm-io8-pwm0-ch0 { + rockchip,pins = + <0 RK_PB0 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm0_ch1: rm-io8-pwm0-ch1 { + rockchip,pins = + <0 RK_PB0 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm0_ch2: rm-io8-pwm0-ch2 { + rockchip,pins = + <0 RK_PB0 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm0_ch3: rm-io8-pwm0-ch3 { + rockchip,pins = + <0 RK_PB0 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch0: rm-io8-pwm1-ch0 { + rockchip,pins = + <0 RK_PB0 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch1: rm-io8-pwm1-ch1 { + rockchip,pins = + <0 RK_PB0 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch2: rm-io8-pwm1-ch2 { + rockchip,pins = + <0 RK_PB0 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch3: rm-io8-pwm1-ch3 { + rockchip,pins = + <0 RK_PB0 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch4: rm-io8-pwm1-ch4 { + rockchip,pins = + <0 RK_PB0 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch5: rm-io8-pwm1-ch5 { + rockchip,pins = + <0 RK_PB0 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch6: rm-io8-pwm1-ch6 { + rockchip,pins = + <0 RK_PB0 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_ch7: rm-io8-pwm1-ch7 { + rockchip,pins = + <0 RK_PB0 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_drive: rm-io8-touch-key-drive { + rockchip,pins = + <0 RK_PB0 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in0: rm-io8-touch-key-in0 { + rockchip,pins = + <0 RK_PB0 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in1: rm-io8-touch-key-in1 { + rockchip,pins = + <0 RK_PB0 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in2: rm-io8-touch-key-in2 { + rockchip,pins = + <0 RK_PB0 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in3: rm-io8-touch-key-in3 { + rockchip,pins = + <0 RK_PB0 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in4: rm-io8-touch-key-in4 { + rockchip,pins = + <0 RK_PB0 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in5: rm-io8-touch-key-in5 { + rockchip,pins = + <0 RK_PB0 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in6: rm-io8-touch-key-in6 { + rockchip,pins = + <0 RK_PB0 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_touch_key_in7: rm-io8-touch-key-in7 { + rockchip,pins = + <0 RK_PB0 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_mclk: rm-io8-sai0-mclk { + rockchip,pins = + <0 RK_PB0 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sclk: rm-io8-sai0-sclk { + rockchip,pins = + <0 RK_PB0 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_lrck: rm-io8-sai0-lrck { + rockchip,pins = + <0 RK_PB0 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sdi0: rm-io8-sai0-sdi0 { + rockchip,pins = + <0 RK_PB0 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sdi1: rm-io8-sai0-sdi1 { + rockchip,pins = + <0 RK_PB0 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sdi2: rm-io8-sai0-sdi2 { + rockchip,pins = + <0 RK_PB0 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sdi3: rm-io8-sai0-sdi3 { + rockchip,pins = + <0 RK_PB0 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai0_sdo: rm-io8-sai0-sdo { + rockchip,pins = + <0 RK_PB0 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_mclk: rm-io8-sai1-mclk { + rockchip,pins = + <0 RK_PB0 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sclk: rm-io8-sai1-sclk { + rockchip,pins = + <0 RK_PB0 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_lrck: rm-io8-sai1-lrck { + rockchip,pins = + <0 RK_PB0 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sdi: rm-io8-sai1-sdi { + rockchip,pins = + <0 RK_PB0 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sdo0: rm-io8-sai1-sdo0 { + rockchip,pins = + <0 RK_PB0 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sdo1: rm-io8-sai1-sdo1 { + rockchip,pins = + <0 RK_PB0 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sdo2: rm-io8-sai1-sdo2 { + rockchip,pins = + <0 RK_PB0 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_sai1_sdo3: rm-io8-sai1-sdo3 { + rockchip,pins = + <0 RK_PB0 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi0_clk: rm-io8-spi0-clk { + rockchip,pins = + <0 RK_PB0 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi0_mosi: rm-io8-spi0-mosi { + rockchip,pins = + <0 RK_PB0 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi0_miso: rm-io8-spi0-miso { + rockchip,pins = + <0 RK_PB0 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi0_csn0: rm-io8-spi0-csn0 { + rockchip,pins = + <0 RK_PB0 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi0_csn1: rm-io8-spi0-csn1 { + rockchip,pins = + <0 RK_PB0 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi1_clk: rm-io8-spi1-clk { + rockchip,pins = + <0 RK_PB0 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi1_mosi: rm-io8-spi1-mosi { + rockchip,pins = + <0 RK_PB0 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi1_miso: rm-io8-spi1-miso { + rockchip,pins = + <0 RK_PB0 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi1_csn0: rm-io8-spi1-csn0 { + rockchip,pins = + <0 RK_PB0 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spi1_csn1: rm-io8-spi1-csn1 { + rockchip,pins = + <0 RK_PB0 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_wdt_tsadc_shut: rm-io8-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB0 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pmu_sleep: rm-io8-pmu-sleep { + rockchip,pins = + <0 RK_PB0 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_core_power_off: rm-io8-core-power-off { + rockchip,pins = + <0 RK_PB0 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spdif_tx: rm-io8-spdif-tx { + rockchip,pins = + <0 RK_PB0 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_spdif_rx: rm-io8-spdif-rx { + rockchip,pins = + <0 RK_PB0 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a0: rm-io8-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB0 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a1: rm-io8-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB0 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a2: rm-io8-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB0 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a3: rm-io8-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB0 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a4: rm-io8-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB0 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_a5: rm-io8-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB0 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b0: rm-io8-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB0 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b1: rm-io8-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB0 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b2: rm-io8-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB0 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b3: rm-io8-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB0 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b4: rm-io8-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB0 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pwm1_bip_cntr_b5: rm-io8-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB0 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_pdm_clk1: rm-io8-pdm-clk1 { + rockchip,pins = + <0 RK_PB0 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_eth_rmii0_ppsclk: rm-io8-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB0 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_eth_rmii0_ppstrig: rm-io8-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB0 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_eth_rmii1_ppsclk: rm-io8-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB0 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io8_eth_rmii1_ppstrig: rm-io8-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB0 113 &pcfg_pull_none>; + }; + }; + + rm_io9 { + /omit-if-no-ref/ + rm_io9_uart1_tx: rm-io9-uart1-tx { + rockchip,pins = + <0 RK_PB1 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart1_rx: rm-io9-uart1-rx { + rockchip,pins = + <0 RK_PB1 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io9_uart2_tx: rm-io9-uart2-tx { + rockchip,pins = + <0 RK_PB1 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart2_rx: rm-io9-uart2-rx { + rockchip,pins = + <0 RK_PB1 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io9_uart3_tx: rm-io9-uart3-tx { + rockchip,pins = + <0 RK_PB1 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart3_rx: rm-io9-uart3-rx { + rockchip,pins = + <0 RK_PB1 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io9_uart3_ctsn: rm-io9-uart3-ctsn { + rockchip,pins = + <0 RK_PB1 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart3_rtsn: rm-io9-uart3-rtsn { + rockchip,pins = + <0 RK_PB1 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart4_tx: rm-io9-uart4-tx { + rockchip,pins = + <0 RK_PB1 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart4_rx: rm-io9-uart4-rx { + rockchip,pins = + <0 RK_PB1 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io9_uart4_ctsn: rm-io9-uart4-ctsn { + rockchip,pins = + <0 RK_PB1 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_uart4_rtsn: rm-io9-uart4-rtsn { + rockchip,pins = + <0 RK_PB1 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_mipite: rm-io9-mipite { + rockchip,pins = + <0 RK_PB1 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_clk_32k: rm-io9-clk-32k { + rockchip,pins = + <0 RK_PB1 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c0_scl: rm-io9-i2c0-scl { + rockchip,pins = + <0 RK_PB1 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c0_sda: rm-io9-i2c0-sda { + rockchip,pins = + <0 RK_PB1 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c1_scl: rm-io9-i2c1-scl { + rockchip,pins = + <0 RK_PB1 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c1_sda: rm-io9-i2c1-sda { + rockchip,pins = + <0 RK_PB1 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c2_scl: rm-io9-i2c2-scl { + rockchip,pins = + <0 RK_PB1 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_i2c2_sda: rm-io9-i2c2-sda { + rockchip,pins = + <0 RK_PB1 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_clk0: rm-io9-pdm-clk0 { + rockchip,pins = + <0 RK_PB1 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_sdi0: rm-io9-pdm-sdi0 { + rockchip,pins = + <0 RK_PB1 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_sdi1: rm-io9-pdm-sdi1 { + rockchip,pins = + <0 RK_PB1 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_sdi2: rm-io9-pdm-sdi2 { + rockchip,pins = + <0 RK_PB1 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_sdi3: rm-io9-pdm-sdi3 { + rockchip,pins = + <0 RK_PB1 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_can1_tx: rm-io9-can1-tx { + rockchip,pins = + <0 RK_PB1 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_can1_rx: rm-io9-can1-rx { + rockchip,pins = + <0 RK_PB1 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_can0_tx: rm-io9-can0-tx { + rockchip,pins = + <0 RK_PB1 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_can0_rx: rm-io9-can0-rx { + rockchip,pins = + <0 RK_PB1 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm0_ch0: rm-io9-pwm0-ch0 { + rockchip,pins = + <0 RK_PB1 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm0_ch1: rm-io9-pwm0-ch1 { + rockchip,pins = + <0 RK_PB1 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm0_ch2: rm-io9-pwm0-ch2 { + rockchip,pins = + <0 RK_PB1 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm0_ch3: rm-io9-pwm0-ch3 { + rockchip,pins = + <0 RK_PB1 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch0: rm-io9-pwm1-ch0 { + rockchip,pins = + <0 RK_PB1 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch1: rm-io9-pwm1-ch1 { + rockchip,pins = + <0 RK_PB1 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch2: rm-io9-pwm1-ch2 { + rockchip,pins = + <0 RK_PB1 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch3: rm-io9-pwm1-ch3 { + rockchip,pins = + <0 RK_PB1 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch4: rm-io9-pwm1-ch4 { + rockchip,pins = + <0 RK_PB1 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch5: rm-io9-pwm1-ch5 { + rockchip,pins = + <0 RK_PB1 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch6: rm-io9-pwm1-ch6 { + rockchip,pins = + <0 RK_PB1 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_ch7: rm-io9-pwm1-ch7 { + rockchip,pins = + <0 RK_PB1 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_drive: rm-io9-touch-key-drive { + rockchip,pins = + <0 RK_PB1 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in0: rm-io9-touch-key-in0 { + rockchip,pins = + <0 RK_PB1 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in1: rm-io9-touch-key-in1 { + rockchip,pins = + <0 RK_PB1 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in2: rm-io9-touch-key-in2 { + rockchip,pins = + <0 RK_PB1 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in3: rm-io9-touch-key-in3 { + rockchip,pins = + <0 RK_PB1 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in4: rm-io9-touch-key-in4 { + rockchip,pins = + <0 RK_PB1 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in5: rm-io9-touch-key-in5 { + rockchip,pins = + <0 RK_PB1 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in6: rm-io9-touch-key-in6 { + rockchip,pins = + <0 RK_PB1 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_touch_key_in7: rm-io9-touch-key-in7 { + rockchip,pins = + <0 RK_PB1 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_mclk: rm-io9-sai0-mclk { + rockchip,pins = + <0 RK_PB1 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sclk: rm-io9-sai0-sclk { + rockchip,pins = + <0 RK_PB1 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_lrck: rm-io9-sai0-lrck { + rockchip,pins = + <0 RK_PB1 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sdi0: rm-io9-sai0-sdi0 { + rockchip,pins = + <0 RK_PB1 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sdi1: rm-io9-sai0-sdi1 { + rockchip,pins = + <0 RK_PB1 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sdi2: rm-io9-sai0-sdi2 { + rockchip,pins = + <0 RK_PB1 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sdi3: rm-io9-sai0-sdi3 { + rockchip,pins = + <0 RK_PB1 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai0_sdo: rm-io9-sai0-sdo { + rockchip,pins = + <0 RK_PB1 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_mclk: rm-io9-sai1-mclk { + rockchip,pins = + <0 RK_PB1 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sclk: rm-io9-sai1-sclk { + rockchip,pins = + <0 RK_PB1 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_lrck: rm-io9-sai1-lrck { + rockchip,pins = + <0 RK_PB1 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sdi: rm-io9-sai1-sdi { + rockchip,pins = + <0 RK_PB1 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sdo0: rm-io9-sai1-sdo0 { + rockchip,pins = + <0 RK_PB1 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sdo1: rm-io9-sai1-sdo1 { + rockchip,pins = + <0 RK_PB1 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sdo2: rm-io9-sai1-sdo2 { + rockchip,pins = + <0 RK_PB1 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_sai1_sdo3: rm-io9-sai1-sdo3 { + rockchip,pins = + <0 RK_PB1 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi0_clk: rm-io9-spi0-clk { + rockchip,pins = + <0 RK_PB1 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi0_mosi: rm-io9-spi0-mosi { + rockchip,pins = + <0 RK_PB1 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi0_miso: rm-io9-spi0-miso { + rockchip,pins = + <0 RK_PB1 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi0_csn0: rm-io9-spi0-csn0 { + rockchip,pins = + <0 RK_PB1 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi0_csn1: rm-io9-spi0-csn1 { + rockchip,pins = + <0 RK_PB1 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi1_clk: rm-io9-spi1-clk { + rockchip,pins = + <0 RK_PB1 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi1_mosi: rm-io9-spi1-mosi { + rockchip,pins = + <0 RK_PB1 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi1_miso: rm-io9-spi1-miso { + rockchip,pins = + <0 RK_PB1 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi1_csn0: rm-io9-spi1-csn0 { + rockchip,pins = + <0 RK_PB1 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spi1_csn1: rm-io9-spi1-csn1 { + rockchip,pins = + <0 RK_PB1 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_wdt_tsadc_shut: rm-io9-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB1 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pmu_sleep: rm-io9-pmu-sleep { + rockchip,pins = + <0 RK_PB1 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_core_power_off: rm-io9-core-power-off { + rockchip,pins = + <0 RK_PB1 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spdif_tx: rm-io9-spdif-tx { + rockchip,pins = + <0 RK_PB1 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_spdif_rx: rm-io9-spdif-rx { + rockchip,pins = + <0 RK_PB1 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a0: rm-io9-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB1 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a1: rm-io9-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB1 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a2: rm-io9-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB1 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a3: rm-io9-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB1 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a4: rm-io9-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB1 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_a5: rm-io9-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB1 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b0: rm-io9-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB1 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b1: rm-io9-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB1 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b2: rm-io9-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB1 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b3: rm-io9-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB1 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b4: rm-io9-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB1 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pwm1_bip_cntr_b5: rm-io9-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB1 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_pdm_clk1: rm-io9-pdm-clk1 { + rockchip,pins = + <0 RK_PB1 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_eth_rmii0_ppsclk: rm-io9-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB1 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_eth_rmii0_ppstrig: rm-io9-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB1 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_eth_rmii1_ppsclk: rm-io9-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB1 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io9_eth_rmii1_ppstrig: rm-io9-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB1 113 &pcfg_pull_none>; + }; + }; + + rm_io10 { + /omit-if-no-ref/ + rm_io10_uart1_tx: rm-io10-uart1-tx { + rockchip,pins = + <0 RK_PB2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart1_rx: rm-io10-uart1-rx { + rockchip,pins = + <0 RK_PB2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io10_uart2_tx: rm-io10-uart2-tx { + rockchip,pins = + <0 RK_PB2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart2_rx: rm-io10-uart2-rx { + rockchip,pins = + <0 RK_PB2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io10_uart3_tx: rm-io10-uart3-tx { + rockchip,pins = + <0 RK_PB2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart3_rx: rm-io10-uart3-rx { + rockchip,pins = + <0 RK_PB2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io10_uart3_ctsn: rm-io10-uart3-ctsn { + rockchip,pins = + <0 RK_PB2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart3_rtsn: rm-io10-uart3-rtsn { + rockchip,pins = + <0 RK_PB2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart4_tx: rm-io10-uart4-tx { + rockchip,pins = + <0 RK_PB2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart4_rx: rm-io10-uart4-rx { + rockchip,pins = + <0 RK_PB2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io10_uart4_ctsn: rm-io10-uart4-ctsn { + rockchip,pins = + <0 RK_PB2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_uart4_rtsn: rm-io10-uart4-rtsn { + rockchip,pins = + <0 RK_PB2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_mipite: rm-io10-mipite { + rockchip,pins = + <0 RK_PB2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_clk_32k: rm-io10-clk-32k { + rockchip,pins = + <0 RK_PB2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c0_scl: rm-io10-i2c0-scl { + rockchip,pins = + <0 RK_PB2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c0_sda: rm-io10-i2c0-sda { + rockchip,pins = + <0 RK_PB2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c1_scl: rm-io10-i2c1-scl { + rockchip,pins = + <0 RK_PB2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c1_sda: rm-io10-i2c1-sda { + rockchip,pins = + <0 RK_PB2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c2_scl: rm-io10-i2c2-scl { + rockchip,pins = + <0 RK_PB2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_i2c2_sda: rm-io10-i2c2-sda { + rockchip,pins = + <0 RK_PB2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_clk0: rm-io10-pdm-clk0 { + rockchip,pins = + <0 RK_PB2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_sdi0: rm-io10-pdm-sdi0 { + rockchip,pins = + <0 RK_PB2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_sdi1: rm-io10-pdm-sdi1 { + rockchip,pins = + <0 RK_PB2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_sdi2: rm-io10-pdm-sdi2 { + rockchip,pins = + <0 RK_PB2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_sdi3: rm-io10-pdm-sdi3 { + rockchip,pins = + <0 RK_PB2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_can1_tx: rm-io10-can1-tx { + rockchip,pins = + <0 RK_PB2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_can1_rx: rm-io10-can1-rx { + rockchip,pins = + <0 RK_PB2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_can0_tx: rm-io10-can0-tx { + rockchip,pins = + <0 RK_PB2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_can0_rx: rm-io10-can0-rx { + rockchip,pins = + <0 RK_PB2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm0_ch0: rm-io10-pwm0-ch0 { + rockchip,pins = + <0 RK_PB2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm0_ch1: rm-io10-pwm0-ch1 { + rockchip,pins = + <0 RK_PB2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm0_ch2: rm-io10-pwm0-ch2 { + rockchip,pins = + <0 RK_PB2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm0_ch3: rm-io10-pwm0-ch3 { + rockchip,pins = + <0 RK_PB2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch0: rm-io10-pwm1-ch0 { + rockchip,pins = + <0 RK_PB2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch1: rm-io10-pwm1-ch1 { + rockchip,pins = + <0 RK_PB2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch2: rm-io10-pwm1-ch2 { + rockchip,pins = + <0 RK_PB2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch3: rm-io10-pwm1-ch3 { + rockchip,pins = + <0 RK_PB2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch4: rm-io10-pwm1-ch4 { + rockchip,pins = + <0 RK_PB2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch5: rm-io10-pwm1-ch5 { + rockchip,pins = + <0 RK_PB2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch6: rm-io10-pwm1-ch6 { + rockchip,pins = + <0 RK_PB2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_ch7: rm-io10-pwm1-ch7 { + rockchip,pins = + <0 RK_PB2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_drive: rm-io10-touch-key-drive { + rockchip,pins = + <0 RK_PB2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in0: rm-io10-touch-key-in0 { + rockchip,pins = + <0 RK_PB2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in1: rm-io10-touch-key-in1 { + rockchip,pins = + <0 RK_PB2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in2: rm-io10-touch-key-in2 { + rockchip,pins = + <0 RK_PB2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in3: rm-io10-touch-key-in3 { + rockchip,pins = + <0 RK_PB2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in4: rm-io10-touch-key-in4 { + rockchip,pins = + <0 RK_PB2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in5: rm-io10-touch-key-in5 { + rockchip,pins = + <0 RK_PB2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in6: rm-io10-touch-key-in6 { + rockchip,pins = + <0 RK_PB2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_touch_key_in7: rm-io10-touch-key-in7 { + rockchip,pins = + <0 RK_PB2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_mclk: rm-io10-sai0-mclk { + rockchip,pins = + <0 RK_PB2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sclk: rm-io10-sai0-sclk { + rockchip,pins = + <0 RK_PB2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_lrck: rm-io10-sai0-lrck { + rockchip,pins = + <0 RK_PB2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sdi0: rm-io10-sai0-sdi0 { + rockchip,pins = + <0 RK_PB2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sdi1: rm-io10-sai0-sdi1 { + rockchip,pins = + <0 RK_PB2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sdi2: rm-io10-sai0-sdi2 { + rockchip,pins = + <0 RK_PB2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sdi3: rm-io10-sai0-sdi3 { + rockchip,pins = + <0 RK_PB2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai0_sdo: rm-io10-sai0-sdo { + rockchip,pins = + <0 RK_PB2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_mclk: rm-io10-sai1-mclk { + rockchip,pins = + <0 RK_PB2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sclk: rm-io10-sai1-sclk { + rockchip,pins = + <0 RK_PB2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_lrck: rm-io10-sai1-lrck { + rockchip,pins = + <0 RK_PB2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sdi: rm-io10-sai1-sdi { + rockchip,pins = + <0 RK_PB2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sdo0: rm-io10-sai1-sdo0 { + rockchip,pins = + <0 RK_PB2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sdo1: rm-io10-sai1-sdo1 { + rockchip,pins = + <0 RK_PB2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sdo2: rm-io10-sai1-sdo2 { + rockchip,pins = + <0 RK_PB2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_sai1_sdo3: rm-io10-sai1-sdo3 { + rockchip,pins = + <0 RK_PB2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi0_clk: rm-io10-spi0-clk { + rockchip,pins = + <0 RK_PB2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi0_mosi: rm-io10-spi0-mosi { + rockchip,pins = + <0 RK_PB2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi0_miso: rm-io10-spi0-miso { + rockchip,pins = + <0 RK_PB2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi0_csn0: rm-io10-spi0-csn0 { + rockchip,pins = + <0 RK_PB2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi0_csn1: rm-io10-spi0-csn1 { + rockchip,pins = + <0 RK_PB2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi1_clk: rm-io10-spi1-clk { + rockchip,pins = + <0 RK_PB2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi1_mosi: rm-io10-spi1-mosi { + rockchip,pins = + <0 RK_PB2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi1_miso: rm-io10-spi1-miso { + rockchip,pins = + <0 RK_PB2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi1_csn0: rm-io10-spi1-csn0 { + rockchip,pins = + <0 RK_PB2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spi1_csn1: rm-io10-spi1-csn1 { + rockchip,pins = + <0 RK_PB2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_wdt_tsadc_shut: rm-io10-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pmu_sleep: rm-io10-pmu-sleep { + rockchip,pins = + <0 RK_PB2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_core_power_off: rm-io10-core-power-off { + rockchip,pins = + <0 RK_PB2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spdif_tx: rm-io10-spdif-tx { + rockchip,pins = + <0 RK_PB2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_spdif_rx: rm-io10-spdif-rx { + rockchip,pins = + <0 RK_PB2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a0: rm-io10-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a1: rm-io10-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a2: rm-io10-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a3: rm-io10-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a4: rm-io10-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_a5: rm-io10-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b0: rm-io10-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b1: rm-io10-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b2: rm-io10-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b3: rm-io10-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b4: rm-io10-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pwm1_bip_cntr_b5: rm-io10-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_pdm_clk1: rm-io10-pdm-clk1 { + rockchip,pins = + <0 RK_PB2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_eth_rmii0_ppsclk: rm-io10-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_eth_rmii0_ppstrig: rm-io10-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_eth_rmii1_ppsclk: rm-io10-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io10_eth_rmii1_ppstrig: rm-io10-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB2 113 &pcfg_pull_none>; + }; + }; + + rm_io11 { + /omit-if-no-ref/ + rm_io11_uart1_tx: rm-io11-uart1-tx { + rockchip,pins = + <0 RK_PB3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart1_rx: rm-io11-uart1-rx { + rockchip,pins = + <0 RK_PB3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io11_uart2_tx: rm-io11-uart2-tx { + rockchip,pins = + <0 RK_PB3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart2_rx: rm-io11-uart2-rx { + rockchip,pins = + <0 RK_PB3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io11_uart3_tx: rm-io11-uart3-tx { + rockchip,pins = + <0 RK_PB3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart3_rx: rm-io11-uart3-rx { + rockchip,pins = + <0 RK_PB3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io11_uart3_ctsn: rm-io11-uart3-ctsn { + rockchip,pins = + <0 RK_PB3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart3_rtsn: rm-io11-uart3-rtsn { + rockchip,pins = + <0 RK_PB3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart4_tx: rm-io11-uart4-tx { + rockchip,pins = + <0 RK_PB3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart4_rx: rm-io11-uart4-rx { + rockchip,pins = + <0 RK_PB3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io11_uart4_ctsn: rm-io11-uart4-ctsn { + rockchip,pins = + <0 RK_PB3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_uart4_rtsn: rm-io11-uart4-rtsn { + rockchip,pins = + <0 RK_PB3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_mipite: rm-io11-mipite { + rockchip,pins = + <0 RK_PB3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_clk_32k: rm-io11-clk-32k { + rockchip,pins = + <0 RK_PB3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c0_scl: rm-io11-i2c0-scl { + rockchip,pins = + <0 RK_PB3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c0_sda: rm-io11-i2c0-sda { + rockchip,pins = + <0 RK_PB3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c1_scl: rm-io11-i2c1-scl { + rockchip,pins = + <0 RK_PB3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c1_sda: rm-io11-i2c1-sda { + rockchip,pins = + <0 RK_PB3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c2_scl: rm-io11-i2c2-scl { + rockchip,pins = + <0 RK_PB3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_i2c2_sda: rm-io11-i2c2-sda { + rockchip,pins = + <0 RK_PB3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_clk0: rm-io11-pdm-clk0 { + rockchip,pins = + <0 RK_PB3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_sdi0: rm-io11-pdm-sdi0 { + rockchip,pins = + <0 RK_PB3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_sdi1: rm-io11-pdm-sdi1 { + rockchip,pins = + <0 RK_PB3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_sdi2: rm-io11-pdm-sdi2 { + rockchip,pins = + <0 RK_PB3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_sdi3: rm-io11-pdm-sdi3 { + rockchip,pins = + <0 RK_PB3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_can1_tx: rm-io11-can1-tx { + rockchip,pins = + <0 RK_PB3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_can1_rx: rm-io11-can1-rx { + rockchip,pins = + <0 RK_PB3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_can0_tx: rm-io11-can0-tx { + rockchip,pins = + <0 RK_PB3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_can0_rx: rm-io11-can0-rx { + rockchip,pins = + <0 RK_PB3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm0_ch0: rm-io11-pwm0-ch0 { + rockchip,pins = + <0 RK_PB3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm0_ch1: rm-io11-pwm0-ch1 { + rockchip,pins = + <0 RK_PB3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm0_ch2: rm-io11-pwm0-ch2 { + rockchip,pins = + <0 RK_PB3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm0_ch3: rm-io11-pwm0-ch3 { + rockchip,pins = + <0 RK_PB3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch0: rm-io11-pwm1-ch0 { + rockchip,pins = + <0 RK_PB3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch1: rm-io11-pwm1-ch1 { + rockchip,pins = + <0 RK_PB3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch2: rm-io11-pwm1-ch2 { + rockchip,pins = + <0 RK_PB3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch3: rm-io11-pwm1-ch3 { + rockchip,pins = + <0 RK_PB3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch4: rm-io11-pwm1-ch4 { + rockchip,pins = + <0 RK_PB3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch5: rm-io11-pwm1-ch5 { + rockchip,pins = + <0 RK_PB3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch6: rm-io11-pwm1-ch6 { + rockchip,pins = + <0 RK_PB3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_ch7: rm-io11-pwm1-ch7 { + rockchip,pins = + <0 RK_PB3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_drive: rm-io11-touch-key-drive { + rockchip,pins = + <0 RK_PB3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in0: rm-io11-touch-key-in0 { + rockchip,pins = + <0 RK_PB3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in1: rm-io11-touch-key-in1 { + rockchip,pins = + <0 RK_PB3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in2: rm-io11-touch-key-in2 { + rockchip,pins = + <0 RK_PB3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in3: rm-io11-touch-key-in3 { + rockchip,pins = + <0 RK_PB3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in4: rm-io11-touch-key-in4 { + rockchip,pins = + <0 RK_PB3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in5: rm-io11-touch-key-in5 { + rockchip,pins = + <0 RK_PB3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in6: rm-io11-touch-key-in6 { + rockchip,pins = + <0 RK_PB3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_touch_key_in7: rm-io11-touch-key-in7 { + rockchip,pins = + <0 RK_PB3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_mclk: rm-io11-sai0-mclk { + rockchip,pins = + <0 RK_PB3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sclk: rm-io11-sai0-sclk { + rockchip,pins = + <0 RK_PB3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_lrck: rm-io11-sai0-lrck { + rockchip,pins = + <0 RK_PB3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sdi0: rm-io11-sai0-sdi0 { + rockchip,pins = + <0 RK_PB3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sdi1: rm-io11-sai0-sdi1 { + rockchip,pins = + <0 RK_PB3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sdi2: rm-io11-sai0-sdi2 { + rockchip,pins = + <0 RK_PB3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sdi3: rm-io11-sai0-sdi3 { + rockchip,pins = + <0 RK_PB3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai0_sdo: rm-io11-sai0-sdo { + rockchip,pins = + <0 RK_PB3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_mclk: rm-io11-sai1-mclk { + rockchip,pins = + <0 RK_PB3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sclk: rm-io11-sai1-sclk { + rockchip,pins = + <0 RK_PB3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_lrck: rm-io11-sai1-lrck { + rockchip,pins = + <0 RK_PB3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sdi: rm-io11-sai1-sdi { + rockchip,pins = + <0 RK_PB3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sdo0: rm-io11-sai1-sdo0 { + rockchip,pins = + <0 RK_PB3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sdo1: rm-io11-sai1-sdo1 { + rockchip,pins = + <0 RK_PB3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sdo2: rm-io11-sai1-sdo2 { + rockchip,pins = + <0 RK_PB3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_sai1_sdo3: rm-io11-sai1-sdo3 { + rockchip,pins = + <0 RK_PB3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi0_clk: rm-io11-spi0-clk { + rockchip,pins = + <0 RK_PB3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi0_mosi: rm-io11-spi0-mosi { + rockchip,pins = + <0 RK_PB3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi0_miso: rm-io11-spi0-miso { + rockchip,pins = + <0 RK_PB3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi0_csn0: rm-io11-spi0-csn0 { + rockchip,pins = + <0 RK_PB3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi0_csn1: rm-io11-spi0-csn1 { + rockchip,pins = + <0 RK_PB3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi1_clk: rm-io11-spi1-clk { + rockchip,pins = + <0 RK_PB3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi1_mosi: rm-io11-spi1-mosi { + rockchip,pins = + <0 RK_PB3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi1_miso: rm-io11-spi1-miso { + rockchip,pins = + <0 RK_PB3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi1_csn0: rm-io11-spi1-csn0 { + rockchip,pins = + <0 RK_PB3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spi1_csn1: rm-io11-spi1-csn1 { + rockchip,pins = + <0 RK_PB3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_wdt_tsadc_shut: rm-io11-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pmu_sleep: rm-io11-pmu-sleep { + rockchip,pins = + <0 RK_PB3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_core_power_off: rm-io11-core-power-off { + rockchip,pins = + <0 RK_PB3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spdif_tx: rm-io11-spdif-tx { + rockchip,pins = + <0 RK_PB3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_spdif_rx: rm-io11-spdif-rx { + rockchip,pins = + <0 RK_PB3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a0: rm-io11-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a1: rm-io11-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a2: rm-io11-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a3: rm-io11-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a4: rm-io11-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_a5: rm-io11-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b0: rm-io11-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b1: rm-io11-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b2: rm-io11-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b3: rm-io11-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b4: rm-io11-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pwm1_bip_cntr_b5: rm-io11-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_pdm_clk1: rm-io11-pdm-clk1 { + rockchip,pins = + <0 RK_PB3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_eth_rmii0_ppsclk: rm-io11-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_eth_rmii0_ppstrig: rm-io11-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_eth_rmii1_ppsclk: rm-io11-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io11_eth_rmii1_ppstrig: rm-io11-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB3 113 &pcfg_pull_none>; + }; + }; + + rm_io12 { + /omit-if-no-ref/ + rm_io12_uart1_tx: rm-io12-uart1-tx { + rockchip,pins = + <0 RK_PB4 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart1_rx: rm-io12-uart1-rx { + rockchip,pins = + <0 RK_PB4 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io12_uart2_tx: rm-io12-uart2-tx { + rockchip,pins = + <0 RK_PB4 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart2_rx: rm-io12-uart2-rx { + rockchip,pins = + <0 RK_PB4 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io12_uart3_tx: rm-io12-uart3-tx { + rockchip,pins = + <0 RK_PB4 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart3_rx: rm-io12-uart3-rx { + rockchip,pins = + <0 RK_PB4 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io12_uart3_ctsn: rm-io12-uart3-ctsn { + rockchip,pins = + <0 RK_PB4 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart3_rtsn: rm-io12-uart3-rtsn { + rockchip,pins = + <0 RK_PB4 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart4_tx: rm-io12-uart4-tx { + rockchip,pins = + <0 RK_PB4 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart4_rx: rm-io12-uart4-rx { + rockchip,pins = + <0 RK_PB4 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io12_uart4_ctsn: rm-io12-uart4-ctsn { + rockchip,pins = + <0 RK_PB4 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_uart4_rtsn: rm-io12-uart4-rtsn { + rockchip,pins = + <0 RK_PB4 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_mipite: rm-io12-mipite { + rockchip,pins = + <0 RK_PB4 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_clk_32k: rm-io12-clk-32k { + rockchip,pins = + <0 RK_PB4 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c0_scl: rm-io12-i2c0-scl { + rockchip,pins = + <0 RK_PB4 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c0_sda: rm-io12-i2c0-sda { + rockchip,pins = + <0 RK_PB4 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c1_scl: rm-io12-i2c1-scl { + rockchip,pins = + <0 RK_PB4 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c1_sda: rm-io12-i2c1-sda { + rockchip,pins = + <0 RK_PB4 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c2_scl: rm-io12-i2c2-scl { + rockchip,pins = + <0 RK_PB4 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_i2c2_sda: rm-io12-i2c2-sda { + rockchip,pins = + <0 RK_PB4 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_clk0: rm-io12-pdm-clk0 { + rockchip,pins = + <0 RK_PB4 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_sdi0: rm-io12-pdm-sdi0 { + rockchip,pins = + <0 RK_PB4 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_sdi1: rm-io12-pdm-sdi1 { + rockchip,pins = + <0 RK_PB4 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_sdi2: rm-io12-pdm-sdi2 { + rockchip,pins = + <0 RK_PB4 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_sdi3: rm-io12-pdm-sdi3 { + rockchip,pins = + <0 RK_PB4 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_can1_tx: rm-io12-can1-tx { + rockchip,pins = + <0 RK_PB4 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_can1_rx: rm-io12-can1-rx { + rockchip,pins = + <0 RK_PB4 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_can0_tx: rm-io12-can0-tx { + rockchip,pins = + <0 RK_PB4 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_can0_rx: rm-io12-can0-rx { + rockchip,pins = + <0 RK_PB4 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm0_ch0: rm-io12-pwm0-ch0 { + rockchip,pins = + <0 RK_PB4 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm0_ch1: rm-io12-pwm0-ch1 { + rockchip,pins = + <0 RK_PB4 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm0_ch2: rm-io12-pwm0-ch2 { + rockchip,pins = + <0 RK_PB4 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm0_ch3: rm-io12-pwm0-ch3 { + rockchip,pins = + <0 RK_PB4 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch0: rm-io12-pwm1-ch0 { + rockchip,pins = + <0 RK_PB4 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch1: rm-io12-pwm1-ch1 { + rockchip,pins = + <0 RK_PB4 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch2: rm-io12-pwm1-ch2 { + rockchip,pins = + <0 RK_PB4 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch3: rm-io12-pwm1-ch3 { + rockchip,pins = + <0 RK_PB4 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch4: rm-io12-pwm1-ch4 { + rockchip,pins = + <0 RK_PB4 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch5: rm-io12-pwm1-ch5 { + rockchip,pins = + <0 RK_PB4 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch6: rm-io12-pwm1-ch6 { + rockchip,pins = + <0 RK_PB4 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_ch7: rm-io12-pwm1-ch7 { + rockchip,pins = + <0 RK_PB4 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_drive: rm-io12-touch-key-drive { + rockchip,pins = + <0 RK_PB4 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in0: rm-io12-touch-key-in0 { + rockchip,pins = + <0 RK_PB4 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in1: rm-io12-touch-key-in1 { + rockchip,pins = + <0 RK_PB4 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in2: rm-io12-touch-key-in2 { + rockchip,pins = + <0 RK_PB4 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in3: rm-io12-touch-key-in3 { + rockchip,pins = + <0 RK_PB4 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in4: rm-io12-touch-key-in4 { + rockchip,pins = + <0 RK_PB4 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in5: rm-io12-touch-key-in5 { + rockchip,pins = + <0 RK_PB4 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in6: rm-io12-touch-key-in6 { + rockchip,pins = + <0 RK_PB4 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_touch_key_in7: rm-io12-touch-key-in7 { + rockchip,pins = + <0 RK_PB4 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_mclk: rm-io12-sai0-mclk { + rockchip,pins = + <0 RK_PB4 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sclk: rm-io12-sai0-sclk { + rockchip,pins = + <0 RK_PB4 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_lrck: rm-io12-sai0-lrck { + rockchip,pins = + <0 RK_PB4 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sdi0: rm-io12-sai0-sdi0 { + rockchip,pins = + <0 RK_PB4 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sdi1: rm-io12-sai0-sdi1 { + rockchip,pins = + <0 RK_PB4 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sdi2: rm-io12-sai0-sdi2 { + rockchip,pins = + <0 RK_PB4 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sdi3: rm-io12-sai0-sdi3 { + rockchip,pins = + <0 RK_PB4 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai0_sdo: rm-io12-sai0-sdo { + rockchip,pins = + <0 RK_PB4 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_mclk: rm-io12-sai1-mclk { + rockchip,pins = + <0 RK_PB4 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sclk: rm-io12-sai1-sclk { + rockchip,pins = + <0 RK_PB4 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_lrck: rm-io12-sai1-lrck { + rockchip,pins = + <0 RK_PB4 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sdi: rm-io12-sai1-sdi { + rockchip,pins = + <0 RK_PB4 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sdo0: rm-io12-sai1-sdo0 { + rockchip,pins = + <0 RK_PB4 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sdo1: rm-io12-sai1-sdo1 { + rockchip,pins = + <0 RK_PB4 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sdo2: rm-io12-sai1-sdo2 { + rockchip,pins = + <0 RK_PB4 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_sai1_sdo3: rm-io12-sai1-sdo3 { + rockchip,pins = + <0 RK_PB4 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi0_clk: rm-io12-spi0-clk { + rockchip,pins = + <0 RK_PB4 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi0_mosi: rm-io12-spi0-mosi { + rockchip,pins = + <0 RK_PB4 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi0_miso: rm-io12-spi0-miso { + rockchip,pins = + <0 RK_PB4 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi0_csn0: rm-io12-spi0-csn0 { + rockchip,pins = + <0 RK_PB4 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi0_csn1: rm-io12-spi0-csn1 { + rockchip,pins = + <0 RK_PB4 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi1_clk: rm-io12-spi1-clk { + rockchip,pins = + <0 RK_PB4 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi1_mosi: rm-io12-spi1-mosi { + rockchip,pins = + <0 RK_PB4 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi1_miso: rm-io12-spi1-miso { + rockchip,pins = + <0 RK_PB4 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi1_csn0: rm-io12-spi1-csn0 { + rockchip,pins = + <0 RK_PB4 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spi1_csn1: rm-io12-spi1-csn1 { + rockchip,pins = + <0 RK_PB4 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_wdt_tsadc_shut: rm-io12-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB4 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pmu_sleep: rm-io12-pmu-sleep { + rockchip,pins = + <0 RK_PB4 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_core_power_off: rm-io12-core-power-off { + rockchip,pins = + <0 RK_PB4 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spdif_tx: rm-io12-spdif-tx { + rockchip,pins = + <0 RK_PB4 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_spdif_rx: rm-io12-spdif-rx { + rockchip,pins = + <0 RK_PB4 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a0: rm-io12-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB4 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a1: rm-io12-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB4 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a2: rm-io12-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB4 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a3: rm-io12-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB4 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a4: rm-io12-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB4 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_a5: rm-io12-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB4 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b0: rm-io12-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB4 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b1: rm-io12-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB4 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b2: rm-io12-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB4 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b3: rm-io12-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB4 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b4: rm-io12-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB4 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pwm1_bip_cntr_b5: rm-io12-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB4 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_pdm_clk1: rm-io12-pdm-clk1 { + rockchip,pins = + <0 RK_PB4 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_eth_rmii0_ppsclk: rm-io12-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB4 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_eth_rmii0_ppstrig: rm-io12-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB4 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_eth_rmii1_ppsclk: rm-io12-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB4 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io12_eth_rmii1_ppstrig: rm-io12-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB4 113 &pcfg_pull_none>; + }; + }; + + rm_io13 { + /omit-if-no-ref/ + rm_io13_uart1_tx: rm-io13-uart1-tx { + rockchip,pins = + <0 RK_PB5 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart1_rx: rm-io13-uart1-rx { + rockchip,pins = + <0 RK_PB5 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io13_uart2_tx: rm-io13-uart2-tx { + rockchip,pins = + <0 RK_PB5 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart2_rx: rm-io13-uart2-rx { + rockchip,pins = + <0 RK_PB5 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io13_uart3_tx: rm-io13-uart3-tx { + rockchip,pins = + <0 RK_PB5 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart3_rx: rm-io13-uart3-rx { + rockchip,pins = + <0 RK_PB5 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io13_uart3_ctsn: rm-io13-uart3-ctsn { + rockchip,pins = + <0 RK_PB5 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart3_rtsn: rm-io13-uart3-rtsn { + rockchip,pins = + <0 RK_PB5 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart4_tx: rm-io13-uart4-tx { + rockchip,pins = + <0 RK_PB5 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart4_rx: rm-io13-uart4-rx { + rockchip,pins = + <0 RK_PB5 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io13_uart4_ctsn: rm-io13-uart4-ctsn { + rockchip,pins = + <0 RK_PB5 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_uart4_rtsn: rm-io13-uart4-rtsn { + rockchip,pins = + <0 RK_PB5 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_mipite: rm-io13-mipite { + rockchip,pins = + <0 RK_PB5 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_clk_32k: rm-io13-clk-32k { + rockchip,pins = + <0 RK_PB5 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c0_scl: rm-io13-i2c0-scl { + rockchip,pins = + <0 RK_PB5 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c0_sda: rm-io13-i2c0-sda { + rockchip,pins = + <0 RK_PB5 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c1_scl: rm-io13-i2c1-scl { + rockchip,pins = + <0 RK_PB5 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c1_sda: rm-io13-i2c1-sda { + rockchip,pins = + <0 RK_PB5 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c2_scl: rm-io13-i2c2-scl { + rockchip,pins = + <0 RK_PB5 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_i2c2_sda: rm-io13-i2c2-sda { + rockchip,pins = + <0 RK_PB5 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_clk0: rm-io13-pdm-clk0 { + rockchip,pins = + <0 RK_PB5 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_sdi0: rm-io13-pdm-sdi0 { + rockchip,pins = + <0 RK_PB5 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_sdi1: rm-io13-pdm-sdi1 { + rockchip,pins = + <0 RK_PB5 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_sdi2: rm-io13-pdm-sdi2 { + rockchip,pins = + <0 RK_PB5 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_sdi3: rm-io13-pdm-sdi3 { + rockchip,pins = + <0 RK_PB5 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_can1_tx: rm-io13-can1-tx { + rockchip,pins = + <0 RK_PB5 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_can1_rx: rm-io13-can1-rx { + rockchip,pins = + <0 RK_PB5 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_can0_tx: rm-io13-can0-tx { + rockchip,pins = + <0 RK_PB5 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_can0_rx: rm-io13-can0-rx { + rockchip,pins = + <0 RK_PB5 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm0_ch0: rm-io13-pwm0-ch0 { + rockchip,pins = + <0 RK_PB5 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm0_ch1: rm-io13-pwm0-ch1 { + rockchip,pins = + <0 RK_PB5 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm0_ch2: rm-io13-pwm0-ch2 { + rockchip,pins = + <0 RK_PB5 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm0_ch3: rm-io13-pwm0-ch3 { + rockchip,pins = + <0 RK_PB5 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch0: rm-io13-pwm1-ch0 { + rockchip,pins = + <0 RK_PB5 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch1: rm-io13-pwm1-ch1 { + rockchip,pins = + <0 RK_PB5 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch2: rm-io13-pwm1-ch2 { + rockchip,pins = + <0 RK_PB5 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch3: rm-io13-pwm1-ch3 { + rockchip,pins = + <0 RK_PB5 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch4: rm-io13-pwm1-ch4 { + rockchip,pins = + <0 RK_PB5 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch5: rm-io13-pwm1-ch5 { + rockchip,pins = + <0 RK_PB5 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch6: rm-io13-pwm1-ch6 { + rockchip,pins = + <0 RK_PB5 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_ch7: rm-io13-pwm1-ch7 { + rockchip,pins = + <0 RK_PB5 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_drive: rm-io13-touch-key-drive { + rockchip,pins = + <0 RK_PB5 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in0: rm-io13-touch-key-in0 { + rockchip,pins = + <0 RK_PB5 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in1: rm-io13-touch-key-in1 { + rockchip,pins = + <0 RK_PB5 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in2: rm-io13-touch-key-in2 { + rockchip,pins = + <0 RK_PB5 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in3: rm-io13-touch-key-in3 { + rockchip,pins = + <0 RK_PB5 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in4: rm-io13-touch-key-in4 { + rockchip,pins = + <0 RK_PB5 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in5: rm-io13-touch-key-in5 { + rockchip,pins = + <0 RK_PB5 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in6: rm-io13-touch-key-in6 { + rockchip,pins = + <0 RK_PB5 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_touch_key_in7: rm-io13-touch-key-in7 { + rockchip,pins = + <0 RK_PB5 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_mclk: rm-io13-sai0-mclk { + rockchip,pins = + <0 RK_PB5 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sclk: rm-io13-sai0-sclk { + rockchip,pins = + <0 RK_PB5 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_lrck: rm-io13-sai0-lrck { + rockchip,pins = + <0 RK_PB5 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sdi0: rm-io13-sai0-sdi0 { + rockchip,pins = + <0 RK_PB5 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sdi1: rm-io13-sai0-sdi1 { + rockchip,pins = + <0 RK_PB5 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sdi2: rm-io13-sai0-sdi2 { + rockchip,pins = + <0 RK_PB5 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sdi3: rm-io13-sai0-sdi3 { + rockchip,pins = + <0 RK_PB5 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai0_sdo: rm-io13-sai0-sdo { + rockchip,pins = + <0 RK_PB5 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_mclk: rm-io13-sai1-mclk { + rockchip,pins = + <0 RK_PB5 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sclk: rm-io13-sai1-sclk { + rockchip,pins = + <0 RK_PB5 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_lrck: rm-io13-sai1-lrck { + rockchip,pins = + <0 RK_PB5 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sdi: rm-io13-sai1-sdi { + rockchip,pins = + <0 RK_PB5 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sdo0: rm-io13-sai1-sdo0 { + rockchip,pins = + <0 RK_PB5 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sdo1: rm-io13-sai1-sdo1 { + rockchip,pins = + <0 RK_PB5 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sdo2: rm-io13-sai1-sdo2 { + rockchip,pins = + <0 RK_PB5 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_sai1_sdo3: rm-io13-sai1-sdo3 { + rockchip,pins = + <0 RK_PB5 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi0_clk: rm-io13-spi0-clk { + rockchip,pins = + <0 RK_PB5 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi0_mosi: rm-io13-spi0-mosi { + rockchip,pins = + <0 RK_PB5 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi0_miso: rm-io13-spi0-miso { + rockchip,pins = + <0 RK_PB5 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi0_csn0: rm-io13-spi0-csn0 { + rockchip,pins = + <0 RK_PB5 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi0_csn1: rm-io13-spi0-csn1 { + rockchip,pins = + <0 RK_PB5 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi1_clk: rm-io13-spi1-clk { + rockchip,pins = + <0 RK_PB5 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi1_mosi: rm-io13-spi1-mosi { + rockchip,pins = + <0 RK_PB5 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi1_miso: rm-io13-spi1-miso { + rockchip,pins = + <0 RK_PB5 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi1_csn0: rm-io13-spi1-csn0 { + rockchip,pins = + <0 RK_PB5 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spi1_csn1: rm-io13-spi1-csn1 { + rockchip,pins = + <0 RK_PB5 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_wdt_tsadc_shut: rm-io13-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB5 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pmu_sleep: rm-io13-pmu-sleep { + rockchip,pins = + <0 RK_PB5 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_core_power_off: rm-io13-core-power-off { + rockchip,pins = + <0 RK_PB5 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spdif_tx: rm-io13-spdif-tx { + rockchip,pins = + <0 RK_PB5 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_spdif_rx: rm-io13-spdif-rx { + rockchip,pins = + <0 RK_PB5 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a0: rm-io13-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB5 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a1: rm-io13-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB5 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a2: rm-io13-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB5 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a3: rm-io13-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB5 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a4: rm-io13-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB5 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_a5: rm-io13-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB5 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b0: rm-io13-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB5 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b1: rm-io13-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB5 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b2: rm-io13-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB5 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b3: rm-io13-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB5 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b4: rm-io13-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB5 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pwm1_bip_cntr_b5: rm-io13-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB5 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_pdm_clk1: rm-io13-pdm-clk1 { + rockchip,pins = + <0 RK_PB5 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_eth_rmii0_ppsclk: rm-io13-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB5 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_eth_rmii0_ppstrig: rm-io13-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB5 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_eth_rmii1_ppsclk: rm-io13-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB5 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io13_eth_rmii1_ppstrig: rm-io13-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB5 113 &pcfg_pull_none>; + }; + }; + + rm_io14 { + /omit-if-no-ref/ + rm_io14_uart1_tx: rm-io14-uart1-tx { + rockchip,pins = + <0 RK_PB6 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart1_rx: rm-io14-uart1-rx { + rockchip,pins = + <0 RK_PB6 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io14_uart2_tx: rm-io14-uart2-tx { + rockchip,pins = + <0 RK_PB6 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart2_rx: rm-io14-uart2-rx { + rockchip,pins = + <0 RK_PB6 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io14_uart3_tx: rm-io14-uart3-tx { + rockchip,pins = + <0 RK_PB6 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart3_rx: rm-io14-uart3-rx { + rockchip,pins = + <0 RK_PB6 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io14_uart3_ctsn: rm-io14-uart3-ctsn { + rockchip,pins = + <0 RK_PB6 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart3_rtsn: rm-io14-uart3-rtsn { + rockchip,pins = + <0 RK_PB6 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart4_tx: rm-io14-uart4-tx { + rockchip,pins = + <0 RK_PB6 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart4_rx: rm-io14-uart4-rx { + rockchip,pins = + <0 RK_PB6 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io14_uart4_ctsn: rm-io14-uart4-ctsn { + rockchip,pins = + <0 RK_PB6 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_uart4_rtsn: rm-io14-uart4-rtsn { + rockchip,pins = + <0 RK_PB6 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_mipite: rm-io14-mipite { + rockchip,pins = + <0 RK_PB6 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_clk_32k: rm-io14-clk-32k { + rockchip,pins = + <0 RK_PB6 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c0_scl: rm-io14-i2c0-scl { + rockchip,pins = + <0 RK_PB6 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c0_sda: rm-io14-i2c0-sda { + rockchip,pins = + <0 RK_PB6 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c1_scl: rm-io14-i2c1-scl { + rockchip,pins = + <0 RK_PB6 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c1_sda: rm-io14-i2c1-sda { + rockchip,pins = + <0 RK_PB6 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c2_scl: rm-io14-i2c2-scl { + rockchip,pins = + <0 RK_PB6 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_i2c2_sda: rm-io14-i2c2-sda { + rockchip,pins = + <0 RK_PB6 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_clk0: rm-io14-pdm-clk0 { + rockchip,pins = + <0 RK_PB6 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_sdi0: rm-io14-pdm-sdi0 { + rockchip,pins = + <0 RK_PB6 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_sdi1: rm-io14-pdm-sdi1 { + rockchip,pins = + <0 RK_PB6 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_sdi2: rm-io14-pdm-sdi2 { + rockchip,pins = + <0 RK_PB6 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_sdi3: rm-io14-pdm-sdi3 { + rockchip,pins = + <0 RK_PB6 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_can1_tx: rm-io14-can1-tx { + rockchip,pins = + <0 RK_PB6 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_can1_rx: rm-io14-can1-rx { + rockchip,pins = + <0 RK_PB6 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_can0_tx: rm-io14-can0-tx { + rockchip,pins = + <0 RK_PB6 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_can0_rx: rm-io14-can0-rx { + rockchip,pins = + <0 RK_PB6 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm0_ch0: rm-io14-pwm0-ch0 { + rockchip,pins = + <0 RK_PB6 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm0_ch1: rm-io14-pwm0-ch1 { + rockchip,pins = + <0 RK_PB6 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm0_ch2: rm-io14-pwm0-ch2 { + rockchip,pins = + <0 RK_PB6 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm0_ch3: rm-io14-pwm0-ch3 { + rockchip,pins = + <0 RK_PB6 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch0: rm-io14-pwm1-ch0 { + rockchip,pins = + <0 RK_PB6 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch1: rm-io14-pwm1-ch1 { + rockchip,pins = + <0 RK_PB6 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch2: rm-io14-pwm1-ch2 { + rockchip,pins = + <0 RK_PB6 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch3: rm-io14-pwm1-ch3 { + rockchip,pins = + <0 RK_PB6 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch4: rm-io14-pwm1-ch4 { + rockchip,pins = + <0 RK_PB6 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch5: rm-io14-pwm1-ch5 { + rockchip,pins = + <0 RK_PB6 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch6: rm-io14-pwm1-ch6 { + rockchip,pins = + <0 RK_PB6 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_ch7: rm-io14-pwm1-ch7 { + rockchip,pins = + <0 RK_PB6 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_drive: rm-io14-touch-key-drive { + rockchip,pins = + <0 RK_PB6 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in0: rm-io14-touch-key-in0 { + rockchip,pins = + <0 RK_PB6 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in1: rm-io14-touch-key-in1 { + rockchip,pins = + <0 RK_PB6 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in2: rm-io14-touch-key-in2 { + rockchip,pins = + <0 RK_PB6 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in3: rm-io14-touch-key-in3 { + rockchip,pins = + <0 RK_PB6 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in4: rm-io14-touch-key-in4 { + rockchip,pins = + <0 RK_PB6 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in5: rm-io14-touch-key-in5 { + rockchip,pins = + <0 RK_PB6 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in6: rm-io14-touch-key-in6 { + rockchip,pins = + <0 RK_PB6 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_touch_key_in7: rm-io14-touch-key-in7 { + rockchip,pins = + <0 RK_PB6 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_mclk: rm-io14-sai0-mclk { + rockchip,pins = + <0 RK_PB6 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sclk: rm-io14-sai0-sclk { + rockchip,pins = + <0 RK_PB6 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_lrck: rm-io14-sai0-lrck { + rockchip,pins = + <0 RK_PB6 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sdi0: rm-io14-sai0-sdi0 { + rockchip,pins = + <0 RK_PB6 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sdi1: rm-io14-sai0-sdi1 { + rockchip,pins = + <0 RK_PB6 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sdi2: rm-io14-sai0-sdi2 { + rockchip,pins = + <0 RK_PB6 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sdi3: rm-io14-sai0-sdi3 { + rockchip,pins = + <0 RK_PB6 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai0_sdo: rm-io14-sai0-sdo { + rockchip,pins = + <0 RK_PB6 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_mclk: rm-io14-sai1-mclk { + rockchip,pins = + <0 RK_PB6 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sclk: rm-io14-sai1-sclk { + rockchip,pins = + <0 RK_PB6 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_lrck: rm-io14-sai1-lrck { + rockchip,pins = + <0 RK_PB6 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sdi: rm-io14-sai1-sdi { + rockchip,pins = + <0 RK_PB6 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sdo0: rm-io14-sai1-sdo0 { + rockchip,pins = + <0 RK_PB6 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sdo1: rm-io14-sai1-sdo1 { + rockchip,pins = + <0 RK_PB6 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sdo2: rm-io14-sai1-sdo2 { + rockchip,pins = + <0 RK_PB6 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_sai1_sdo3: rm-io14-sai1-sdo3 { + rockchip,pins = + <0 RK_PB6 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi0_clk: rm-io14-spi0-clk { + rockchip,pins = + <0 RK_PB6 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi0_mosi: rm-io14-spi0-mosi { + rockchip,pins = + <0 RK_PB6 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi0_miso: rm-io14-spi0-miso { + rockchip,pins = + <0 RK_PB6 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi0_csn0: rm-io14-spi0-csn0 { + rockchip,pins = + <0 RK_PB6 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi0_csn1: rm-io14-spi0-csn1 { + rockchip,pins = + <0 RK_PB6 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi1_clk: rm-io14-spi1-clk { + rockchip,pins = + <0 RK_PB6 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi1_mosi: rm-io14-spi1-mosi { + rockchip,pins = + <0 RK_PB6 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi1_miso: rm-io14-spi1-miso { + rockchip,pins = + <0 RK_PB6 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi1_csn0: rm-io14-spi1-csn0 { + rockchip,pins = + <0 RK_PB6 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spi1_csn1: rm-io14-spi1-csn1 { + rockchip,pins = + <0 RK_PB6 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_wdt_tsadc_shut: rm-io14-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB6 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pmu_sleep: rm-io14-pmu-sleep { + rockchip,pins = + <0 RK_PB6 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_core_power_off: rm-io14-core-power-off { + rockchip,pins = + <0 RK_PB6 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spdif_tx: rm-io14-spdif-tx { + rockchip,pins = + <0 RK_PB6 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_spdif_rx: rm-io14-spdif-rx { + rockchip,pins = + <0 RK_PB6 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a0: rm-io14-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB6 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a1: rm-io14-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB6 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a2: rm-io14-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB6 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a3: rm-io14-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB6 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a4: rm-io14-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB6 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_a5: rm-io14-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB6 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b0: rm-io14-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB6 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b1: rm-io14-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB6 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b2: rm-io14-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB6 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b3: rm-io14-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB6 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b4: rm-io14-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB6 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pwm1_bip_cntr_b5: rm-io14-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB6 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_pdm_clk1: rm-io14-pdm-clk1 { + rockchip,pins = + <0 RK_PB6 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_eth_rmii0_ppsclk: rm-io14-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB6 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_eth_rmii0_ppstrig: rm-io14-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB6 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_eth_rmii1_ppsclk: rm-io14-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB6 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io14_eth_rmii1_ppstrig: rm-io14-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB6 113 &pcfg_pull_none>; + }; + }; + + rm_io15 { + /omit-if-no-ref/ + rm_io15_uart1_tx: rm-io15-uart1-tx { + rockchip,pins = + <0 RK_PB7 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart1_rx: rm-io15-uart1-rx { + rockchip,pins = + <0 RK_PB7 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io15_uart2_tx: rm-io15-uart2-tx { + rockchip,pins = + <0 RK_PB7 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart2_rx: rm-io15-uart2-rx { + rockchip,pins = + <0 RK_PB7 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io15_uart3_tx: rm-io15-uart3-tx { + rockchip,pins = + <0 RK_PB7 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart3_rx: rm-io15-uart3-rx { + rockchip,pins = + <0 RK_PB7 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io15_uart3_ctsn: rm-io15-uart3-ctsn { + rockchip,pins = + <0 RK_PB7 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart3_rtsn: rm-io15-uart3-rtsn { + rockchip,pins = + <0 RK_PB7 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart4_tx: rm-io15-uart4-tx { + rockchip,pins = + <0 RK_PB7 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart4_rx: rm-io15-uart4-rx { + rockchip,pins = + <0 RK_PB7 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io15_uart4_ctsn: rm-io15-uart4-ctsn { + rockchip,pins = + <0 RK_PB7 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_uart4_rtsn: rm-io15-uart4-rtsn { + rockchip,pins = + <0 RK_PB7 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_mipite: rm-io15-mipite { + rockchip,pins = + <0 RK_PB7 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_clk_32k: rm-io15-clk-32k { + rockchip,pins = + <0 RK_PB7 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c0_scl: rm-io15-i2c0-scl { + rockchip,pins = + <0 RK_PB7 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c0_sda: rm-io15-i2c0-sda { + rockchip,pins = + <0 RK_PB7 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c1_scl: rm-io15-i2c1-scl { + rockchip,pins = + <0 RK_PB7 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c1_sda: rm-io15-i2c1-sda { + rockchip,pins = + <0 RK_PB7 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c2_scl: rm-io15-i2c2-scl { + rockchip,pins = + <0 RK_PB7 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_i2c2_sda: rm-io15-i2c2-sda { + rockchip,pins = + <0 RK_PB7 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_clk0: rm-io15-pdm-clk0 { + rockchip,pins = + <0 RK_PB7 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_sdi0: rm-io15-pdm-sdi0 { + rockchip,pins = + <0 RK_PB7 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_sdi1: rm-io15-pdm-sdi1 { + rockchip,pins = + <0 RK_PB7 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_sdi2: rm-io15-pdm-sdi2 { + rockchip,pins = + <0 RK_PB7 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_sdi3: rm-io15-pdm-sdi3 { + rockchip,pins = + <0 RK_PB7 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_can1_tx: rm-io15-can1-tx { + rockchip,pins = + <0 RK_PB7 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_can1_rx: rm-io15-can1-rx { + rockchip,pins = + <0 RK_PB7 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_can0_tx: rm-io15-can0-tx { + rockchip,pins = + <0 RK_PB7 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_can0_rx: rm-io15-can0-rx { + rockchip,pins = + <0 RK_PB7 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm0_ch0: rm-io15-pwm0-ch0 { + rockchip,pins = + <0 RK_PB7 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm0_ch1: rm-io15-pwm0-ch1 { + rockchip,pins = + <0 RK_PB7 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm0_ch2: rm-io15-pwm0-ch2 { + rockchip,pins = + <0 RK_PB7 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm0_ch3: rm-io15-pwm0-ch3 { + rockchip,pins = + <0 RK_PB7 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch0: rm-io15-pwm1-ch0 { + rockchip,pins = + <0 RK_PB7 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch1: rm-io15-pwm1-ch1 { + rockchip,pins = + <0 RK_PB7 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch2: rm-io15-pwm1-ch2 { + rockchip,pins = + <0 RK_PB7 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch3: rm-io15-pwm1-ch3 { + rockchip,pins = + <0 RK_PB7 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch4: rm-io15-pwm1-ch4 { + rockchip,pins = + <0 RK_PB7 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch5: rm-io15-pwm1-ch5 { + rockchip,pins = + <0 RK_PB7 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch6: rm-io15-pwm1-ch6 { + rockchip,pins = + <0 RK_PB7 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_ch7: rm-io15-pwm1-ch7 { + rockchip,pins = + <0 RK_PB7 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_drive: rm-io15-touch-key-drive { + rockchip,pins = + <0 RK_PB7 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in0: rm-io15-touch-key-in0 { + rockchip,pins = + <0 RK_PB7 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in1: rm-io15-touch-key-in1 { + rockchip,pins = + <0 RK_PB7 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in2: rm-io15-touch-key-in2 { + rockchip,pins = + <0 RK_PB7 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in3: rm-io15-touch-key-in3 { + rockchip,pins = + <0 RK_PB7 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in4: rm-io15-touch-key-in4 { + rockchip,pins = + <0 RK_PB7 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in5: rm-io15-touch-key-in5 { + rockchip,pins = + <0 RK_PB7 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in6: rm-io15-touch-key-in6 { + rockchip,pins = + <0 RK_PB7 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_touch_key_in7: rm-io15-touch-key-in7 { + rockchip,pins = + <0 RK_PB7 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_mclk: rm-io15-sai0-mclk { + rockchip,pins = + <0 RK_PB7 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sclk: rm-io15-sai0-sclk { + rockchip,pins = + <0 RK_PB7 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_lrck: rm-io15-sai0-lrck { + rockchip,pins = + <0 RK_PB7 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sdi0: rm-io15-sai0-sdi0 { + rockchip,pins = + <0 RK_PB7 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sdi1: rm-io15-sai0-sdi1 { + rockchip,pins = + <0 RK_PB7 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sdi2: rm-io15-sai0-sdi2 { + rockchip,pins = + <0 RK_PB7 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sdi3: rm-io15-sai0-sdi3 { + rockchip,pins = + <0 RK_PB7 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai0_sdo: rm-io15-sai0-sdo { + rockchip,pins = + <0 RK_PB7 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_mclk: rm-io15-sai1-mclk { + rockchip,pins = + <0 RK_PB7 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sclk: rm-io15-sai1-sclk { + rockchip,pins = + <0 RK_PB7 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_lrck: rm-io15-sai1-lrck { + rockchip,pins = + <0 RK_PB7 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sdi: rm-io15-sai1-sdi { + rockchip,pins = + <0 RK_PB7 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sdo0: rm-io15-sai1-sdo0 { + rockchip,pins = + <0 RK_PB7 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sdo1: rm-io15-sai1-sdo1 { + rockchip,pins = + <0 RK_PB7 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sdo2: rm-io15-sai1-sdo2 { + rockchip,pins = + <0 RK_PB7 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_sai1_sdo3: rm-io15-sai1-sdo3 { + rockchip,pins = + <0 RK_PB7 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi0_clk: rm-io15-spi0-clk { + rockchip,pins = + <0 RK_PB7 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi0_mosi: rm-io15-spi0-mosi { + rockchip,pins = + <0 RK_PB7 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi0_miso: rm-io15-spi0-miso { + rockchip,pins = + <0 RK_PB7 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi0_csn0: rm-io15-spi0-csn0 { + rockchip,pins = + <0 RK_PB7 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi0_csn1: rm-io15-spi0-csn1 { + rockchip,pins = + <0 RK_PB7 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi1_clk: rm-io15-spi1-clk { + rockchip,pins = + <0 RK_PB7 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi1_mosi: rm-io15-spi1-mosi { + rockchip,pins = + <0 RK_PB7 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi1_miso: rm-io15-spi1-miso { + rockchip,pins = + <0 RK_PB7 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi1_csn0: rm-io15-spi1-csn0 { + rockchip,pins = + <0 RK_PB7 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spi1_csn1: rm-io15-spi1-csn1 { + rockchip,pins = + <0 RK_PB7 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_wdt_tsadc_shut: rm-io15-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PB7 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pmu_sleep: rm-io15-pmu-sleep { + rockchip,pins = + <0 RK_PB7 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_core_power_off: rm-io15-core-power-off { + rockchip,pins = + <0 RK_PB7 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spdif_tx: rm-io15-spdif-tx { + rockchip,pins = + <0 RK_PB7 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_spdif_rx: rm-io15-spdif-rx { + rockchip,pins = + <0 RK_PB7 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a0: rm-io15-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PB7 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a1: rm-io15-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PB7 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a2: rm-io15-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PB7 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a3: rm-io15-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PB7 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a4: rm-io15-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PB7 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_a5: rm-io15-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PB7 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b0: rm-io15-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PB7 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b1: rm-io15-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PB7 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b2: rm-io15-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PB7 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b3: rm-io15-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PB7 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b4: rm-io15-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PB7 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pwm1_bip_cntr_b5: rm-io15-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PB7 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_pdm_clk1: rm-io15-pdm-clk1 { + rockchip,pins = + <0 RK_PB7 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_eth_rmii0_ppsclk: rm-io15-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PB7 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_eth_rmii0_ppstrig: rm-io15-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PB7 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_eth_rmii1_ppsclk: rm-io15-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PB7 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io15_eth_rmii1_ppstrig: rm-io15-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PB7 113 &pcfg_pull_none>; + }; + }; + + rm_io16 { + /omit-if-no-ref/ + rm_io16_uart1_tx: rm-io16-uart1-tx { + rockchip,pins = + <0 RK_PC0 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart1_rx: rm-io16-uart1-rx { + rockchip,pins = + <0 RK_PC0 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io16_uart2_tx: rm-io16-uart2-tx { + rockchip,pins = + <0 RK_PC0 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart2_rx: rm-io16-uart2-rx { + rockchip,pins = + <0 RK_PC0 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io16_uart3_tx: rm-io16-uart3-tx { + rockchip,pins = + <0 RK_PC0 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart3_rx: rm-io16-uart3-rx { + rockchip,pins = + <0 RK_PC0 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io16_uart3_ctsn: rm-io16-uart3-ctsn { + rockchip,pins = + <0 RK_PC0 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart3_rtsn: rm-io16-uart3-rtsn { + rockchip,pins = + <0 RK_PC0 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart4_tx: rm-io16-uart4-tx { + rockchip,pins = + <0 RK_PC0 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart4_rx: rm-io16-uart4-rx { + rockchip,pins = + <0 RK_PC0 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io16_uart4_ctsn: rm-io16-uart4-ctsn { + rockchip,pins = + <0 RK_PC0 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_uart4_rtsn: rm-io16-uart4-rtsn { + rockchip,pins = + <0 RK_PC0 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_mipite: rm-io16-mipite { + rockchip,pins = + <0 RK_PC0 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_clk_32k: rm-io16-clk-32k { + rockchip,pins = + <0 RK_PC0 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c0_scl: rm-io16-i2c0-scl { + rockchip,pins = + <0 RK_PC0 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c0_sda: rm-io16-i2c0-sda { + rockchip,pins = + <0 RK_PC0 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c1_scl: rm-io16-i2c1-scl { + rockchip,pins = + <0 RK_PC0 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c1_sda: rm-io16-i2c1-sda { + rockchip,pins = + <0 RK_PC0 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c2_scl: rm-io16-i2c2-scl { + rockchip,pins = + <0 RK_PC0 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_i2c2_sda: rm-io16-i2c2-sda { + rockchip,pins = + <0 RK_PC0 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_clk0: rm-io16-pdm-clk0 { + rockchip,pins = + <0 RK_PC0 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_sdi0: rm-io16-pdm-sdi0 { + rockchip,pins = + <0 RK_PC0 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_sdi1: rm-io16-pdm-sdi1 { + rockchip,pins = + <0 RK_PC0 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_sdi2: rm-io16-pdm-sdi2 { + rockchip,pins = + <0 RK_PC0 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_sdi3: rm-io16-pdm-sdi3 { + rockchip,pins = + <0 RK_PC0 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_can1_tx: rm-io16-can1-tx { + rockchip,pins = + <0 RK_PC0 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_can1_rx: rm-io16-can1-rx { + rockchip,pins = + <0 RK_PC0 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_can0_tx: rm-io16-can0-tx { + rockchip,pins = + <0 RK_PC0 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_can0_rx: rm-io16-can0-rx { + rockchip,pins = + <0 RK_PC0 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm0_ch0: rm-io16-pwm0-ch0 { + rockchip,pins = + <0 RK_PC0 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm0_ch1: rm-io16-pwm0-ch1 { + rockchip,pins = + <0 RK_PC0 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm0_ch2: rm-io16-pwm0-ch2 { + rockchip,pins = + <0 RK_PC0 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm0_ch3: rm-io16-pwm0-ch3 { + rockchip,pins = + <0 RK_PC0 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch0: rm-io16-pwm1-ch0 { + rockchip,pins = + <0 RK_PC0 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch1: rm-io16-pwm1-ch1 { + rockchip,pins = + <0 RK_PC0 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch2: rm-io16-pwm1-ch2 { + rockchip,pins = + <0 RK_PC0 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch3: rm-io16-pwm1-ch3 { + rockchip,pins = + <0 RK_PC0 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch4: rm-io16-pwm1-ch4 { + rockchip,pins = + <0 RK_PC0 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch5: rm-io16-pwm1-ch5 { + rockchip,pins = + <0 RK_PC0 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch6: rm-io16-pwm1-ch6 { + rockchip,pins = + <0 RK_PC0 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_ch7: rm-io16-pwm1-ch7 { + rockchip,pins = + <0 RK_PC0 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_drive: rm-io16-touch-key-drive { + rockchip,pins = + <0 RK_PC0 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in0: rm-io16-touch-key-in0 { + rockchip,pins = + <0 RK_PC0 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in1: rm-io16-touch-key-in1 { + rockchip,pins = + <0 RK_PC0 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in2: rm-io16-touch-key-in2 { + rockchip,pins = + <0 RK_PC0 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in3: rm-io16-touch-key-in3 { + rockchip,pins = + <0 RK_PC0 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in4: rm-io16-touch-key-in4 { + rockchip,pins = + <0 RK_PC0 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in5: rm-io16-touch-key-in5 { + rockchip,pins = + <0 RK_PC0 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in6: rm-io16-touch-key-in6 { + rockchip,pins = + <0 RK_PC0 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_touch_key_in7: rm-io16-touch-key-in7 { + rockchip,pins = + <0 RK_PC0 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_mclk: rm-io16-sai0-mclk { + rockchip,pins = + <0 RK_PC0 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sclk: rm-io16-sai0-sclk { + rockchip,pins = + <0 RK_PC0 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_lrck: rm-io16-sai0-lrck { + rockchip,pins = + <0 RK_PC0 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sdi0: rm-io16-sai0-sdi0 { + rockchip,pins = + <0 RK_PC0 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sdi1: rm-io16-sai0-sdi1 { + rockchip,pins = + <0 RK_PC0 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sdi2: rm-io16-sai0-sdi2 { + rockchip,pins = + <0 RK_PC0 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sdi3: rm-io16-sai0-sdi3 { + rockchip,pins = + <0 RK_PC0 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai0_sdo: rm-io16-sai0-sdo { + rockchip,pins = + <0 RK_PC0 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_mclk: rm-io16-sai1-mclk { + rockchip,pins = + <0 RK_PC0 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sclk: rm-io16-sai1-sclk { + rockchip,pins = + <0 RK_PC0 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_lrck: rm-io16-sai1-lrck { + rockchip,pins = + <0 RK_PC0 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sdi: rm-io16-sai1-sdi { + rockchip,pins = + <0 RK_PC0 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sdo0: rm-io16-sai1-sdo0 { + rockchip,pins = + <0 RK_PC0 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sdo1: rm-io16-sai1-sdo1 { + rockchip,pins = + <0 RK_PC0 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sdo2: rm-io16-sai1-sdo2 { + rockchip,pins = + <0 RK_PC0 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_sai1_sdo3: rm-io16-sai1-sdo3 { + rockchip,pins = + <0 RK_PC0 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi0_clk: rm-io16-spi0-clk { + rockchip,pins = + <0 RK_PC0 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi0_mosi: rm-io16-spi0-mosi { + rockchip,pins = + <0 RK_PC0 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi0_miso: rm-io16-spi0-miso { + rockchip,pins = + <0 RK_PC0 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi0_csn0: rm-io16-spi0-csn0 { + rockchip,pins = + <0 RK_PC0 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi0_csn1: rm-io16-spi0-csn1 { + rockchip,pins = + <0 RK_PC0 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi1_clk: rm-io16-spi1-clk { + rockchip,pins = + <0 RK_PC0 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi1_mosi: rm-io16-spi1-mosi { + rockchip,pins = + <0 RK_PC0 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi1_miso: rm-io16-spi1-miso { + rockchip,pins = + <0 RK_PC0 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi1_csn0: rm-io16-spi1-csn0 { + rockchip,pins = + <0 RK_PC0 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spi1_csn1: rm-io16-spi1-csn1 { + rockchip,pins = + <0 RK_PC0 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_wdt_tsadc_shut: rm-io16-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC0 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pmu_sleep: rm-io16-pmu-sleep { + rockchip,pins = + <0 RK_PC0 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_core_power_off: rm-io16-core-power-off { + rockchip,pins = + <0 RK_PC0 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spdif_tx: rm-io16-spdif-tx { + rockchip,pins = + <0 RK_PC0 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_spdif_rx: rm-io16-spdif-rx { + rockchip,pins = + <0 RK_PC0 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a0: rm-io16-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC0 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a1: rm-io16-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC0 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a2: rm-io16-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC0 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a3: rm-io16-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC0 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a4: rm-io16-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC0 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_a5: rm-io16-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC0 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b0: rm-io16-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC0 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b1: rm-io16-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC0 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b2: rm-io16-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC0 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b3: rm-io16-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC0 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b4: rm-io16-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC0 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pwm1_bip_cntr_b5: rm-io16-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC0 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_pdm_clk1: rm-io16-pdm-clk1 { + rockchip,pins = + <0 RK_PC0 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_eth_rmii0_ppsclk: rm-io16-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC0 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_eth_rmii0_ppstrig: rm-io16-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC0 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_eth_rmii1_ppsclk: rm-io16-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC0 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io16_eth_rmii1_ppstrig: rm-io16-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC0 113 &pcfg_pull_none>; + }; + }; + + rm_io17 { + /omit-if-no-ref/ + rm_io17_uart1_tx: rm-io17-uart1-tx { + rockchip,pins = + <0 RK_PC1 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart1_rx: rm-io17-uart1-rx { + rockchip,pins = + <0 RK_PC1 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io17_uart2_tx: rm-io17-uart2-tx { + rockchip,pins = + <0 RK_PC1 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart2_rx: rm-io17-uart2-rx { + rockchip,pins = + <0 RK_PC1 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io17_uart3_tx: rm-io17-uart3-tx { + rockchip,pins = + <0 RK_PC1 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart3_rx: rm-io17-uart3-rx { + rockchip,pins = + <0 RK_PC1 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io17_uart3_ctsn: rm-io17-uart3-ctsn { + rockchip,pins = + <0 RK_PC1 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart3_rtsn: rm-io17-uart3-rtsn { + rockchip,pins = + <0 RK_PC1 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart4_tx: rm-io17-uart4-tx { + rockchip,pins = + <0 RK_PC1 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart4_rx: rm-io17-uart4-rx { + rockchip,pins = + <0 RK_PC1 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io17_uart4_ctsn: rm-io17-uart4-ctsn { + rockchip,pins = + <0 RK_PC1 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_uart4_rtsn: rm-io17-uart4-rtsn { + rockchip,pins = + <0 RK_PC1 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_mipite: rm-io17-mipite { + rockchip,pins = + <0 RK_PC1 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_clk_32k: rm-io17-clk-32k { + rockchip,pins = + <0 RK_PC1 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c0_scl: rm-io17-i2c0-scl { + rockchip,pins = + <0 RK_PC1 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c0_sda: rm-io17-i2c0-sda { + rockchip,pins = + <0 RK_PC1 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c1_scl: rm-io17-i2c1-scl { + rockchip,pins = + <0 RK_PC1 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c1_sda: rm-io17-i2c1-sda { + rockchip,pins = + <0 RK_PC1 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c2_scl: rm-io17-i2c2-scl { + rockchip,pins = + <0 RK_PC1 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_i2c2_sda: rm-io17-i2c2-sda { + rockchip,pins = + <0 RK_PC1 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_clk0: rm-io17-pdm-clk0 { + rockchip,pins = + <0 RK_PC1 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_sdi0: rm-io17-pdm-sdi0 { + rockchip,pins = + <0 RK_PC1 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_sdi1: rm-io17-pdm-sdi1 { + rockchip,pins = + <0 RK_PC1 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_sdi2: rm-io17-pdm-sdi2 { + rockchip,pins = + <0 RK_PC1 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_sdi3: rm-io17-pdm-sdi3 { + rockchip,pins = + <0 RK_PC1 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_can1_tx: rm-io17-can1-tx { + rockchip,pins = + <0 RK_PC1 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_can1_rx: rm-io17-can1-rx { + rockchip,pins = + <0 RK_PC1 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_can0_tx: rm-io17-can0-tx { + rockchip,pins = + <0 RK_PC1 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_can0_rx: rm-io17-can0-rx { + rockchip,pins = + <0 RK_PC1 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm0_ch0: rm-io17-pwm0-ch0 { + rockchip,pins = + <0 RK_PC1 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm0_ch1: rm-io17-pwm0-ch1 { + rockchip,pins = + <0 RK_PC1 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm0_ch2: rm-io17-pwm0-ch2 { + rockchip,pins = + <0 RK_PC1 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm0_ch3: rm-io17-pwm0-ch3 { + rockchip,pins = + <0 RK_PC1 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch0: rm-io17-pwm1-ch0 { + rockchip,pins = + <0 RK_PC1 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch1: rm-io17-pwm1-ch1 { + rockchip,pins = + <0 RK_PC1 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch2: rm-io17-pwm1-ch2 { + rockchip,pins = + <0 RK_PC1 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch3: rm-io17-pwm1-ch3 { + rockchip,pins = + <0 RK_PC1 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch4: rm-io17-pwm1-ch4 { + rockchip,pins = + <0 RK_PC1 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch5: rm-io17-pwm1-ch5 { + rockchip,pins = + <0 RK_PC1 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch6: rm-io17-pwm1-ch6 { + rockchip,pins = + <0 RK_PC1 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_ch7: rm-io17-pwm1-ch7 { + rockchip,pins = + <0 RK_PC1 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_drive: rm-io17-touch-key-drive { + rockchip,pins = + <0 RK_PC1 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in0: rm-io17-touch-key-in0 { + rockchip,pins = + <0 RK_PC1 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in1: rm-io17-touch-key-in1 { + rockchip,pins = + <0 RK_PC1 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in2: rm-io17-touch-key-in2 { + rockchip,pins = + <0 RK_PC1 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in3: rm-io17-touch-key-in3 { + rockchip,pins = + <0 RK_PC1 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in4: rm-io17-touch-key-in4 { + rockchip,pins = + <0 RK_PC1 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in5: rm-io17-touch-key-in5 { + rockchip,pins = + <0 RK_PC1 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in6: rm-io17-touch-key-in6 { + rockchip,pins = + <0 RK_PC1 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_touch_key_in7: rm-io17-touch-key-in7 { + rockchip,pins = + <0 RK_PC1 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_mclk: rm-io17-sai0-mclk { + rockchip,pins = + <0 RK_PC1 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sclk: rm-io17-sai0-sclk { + rockchip,pins = + <0 RK_PC1 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_lrck: rm-io17-sai0-lrck { + rockchip,pins = + <0 RK_PC1 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sdi0: rm-io17-sai0-sdi0 { + rockchip,pins = + <0 RK_PC1 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sdi1: rm-io17-sai0-sdi1 { + rockchip,pins = + <0 RK_PC1 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sdi2: rm-io17-sai0-sdi2 { + rockchip,pins = + <0 RK_PC1 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sdi3: rm-io17-sai0-sdi3 { + rockchip,pins = + <0 RK_PC1 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai0_sdo: rm-io17-sai0-sdo { + rockchip,pins = + <0 RK_PC1 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_mclk: rm-io17-sai1-mclk { + rockchip,pins = + <0 RK_PC1 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sclk: rm-io17-sai1-sclk { + rockchip,pins = + <0 RK_PC1 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_lrck: rm-io17-sai1-lrck { + rockchip,pins = + <0 RK_PC1 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sdi: rm-io17-sai1-sdi { + rockchip,pins = + <0 RK_PC1 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sdo0: rm-io17-sai1-sdo0 { + rockchip,pins = + <0 RK_PC1 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sdo1: rm-io17-sai1-sdo1 { + rockchip,pins = + <0 RK_PC1 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sdo2: rm-io17-sai1-sdo2 { + rockchip,pins = + <0 RK_PC1 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_sai1_sdo3: rm-io17-sai1-sdo3 { + rockchip,pins = + <0 RK_PC1 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi0_clk: rm-io17-spi0-clk { + rockchip,pins = + <0 RK_PC1 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi0_mosi: rm-io17-spi0-mosi { + rockchip,pins = + <0 RK_PC1 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi0_miso: rm-io17-spi0-miso { + rockchip,pins = + <0 RK_PC1 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi0_csn0: rm-io17-spi0-csn0 { + rockchip,pins = + <0 RK_PC1 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi0_csn1: rm-io17-spi0-csn1 { + rockchip,pins = + <0 RK_PC1 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi1_clk: rm-io17-spi1-clk { + rockchip,pins = + <0 RK_PC1 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi1_mosi: rm-io17-spi1-mosi { + rockchip,pins = + <0 RK_PC1 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi1_miso: rm-io17-spi1-miso { + rockchip,pins = + <0 RK_PC1 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi1_csn0: rm-io17-spi1-csn0 { + rockchip,pins = + <0 RK_PC1 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spi1_csn1: rm-io17-spi1-csn1 { + rockchip,pins = + <0 RK_PC1 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_wdt_tsadc_shut: rm-io17-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC1 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pmu_sleep: rm-io17-pmu-sleep { + rockchip,pins = + <0 RK_PC1 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_core_power_off: rm-io17-core-power-off { + rockchip,pins = + <0 RK_PC1 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spdif_tx: rm-io17-spdif-tx { + rockchip,pins = + <0 RK_PC1 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_spdif_rx: rm-io17-spdif-rx { + rockchip,pins = + <0 RK_PC1 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a0: rm-io17-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC1 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a1: rm-io17-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC1 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a2: rm-io17-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC1 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a3: rm-io17-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC1 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a4: rm-io17-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC1 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_a5: rm-io17-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC1 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b0: rm-io17-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC1 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b1: rm-io17-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC1 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b2: rm-io17-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC1 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b3: rm-io17-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC1 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b4: rm-io17-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC1 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pwm1_bip_cntr_b5: rm-io17-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC1 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_pdm_clk1: rm-io17-pdm-clk1 { + rockchip,pins = + <0 RK_PC1 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_eth_rmii0_ppsclk: rm-io17-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC1 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_eth_rmii0_ppstrig: rm-io17-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC1 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_eth_rmii1_ppsclk: rm-io17-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC1 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io17_eth_rmii1_ppstrig: rm-io17-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC1 113 &pcfg_pull_none>; + }; + }; + + rm_io18 { + /omit-if-no-ref/ + rm_io18_uart1_tx: rm-io18-uart1-tx { + rockchip,pins = + <0 RK_PC2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart1_rx: rm-io18-uart1-rx { + rockchip,pins = + <0 RK_PC2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io18_uart2_tx: rm-io18-uart2-tx { + rockchip,pins = + <0 RK_PC2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart2_rx: rm-io18-uart2-rx { + rockchip,pins = + <0 RK_PC2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io18_uart3_tx: rm-io18-uart3-tx { + rockchip,pins = + <0 RK_PC2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart3_rx: rm-io18-uart3-rx { + rockchip,pins = + <0 RK_PC2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io18_uart3_ctsn: rm-io18-uart3-ctsn { + rockchip,pins = + <0 RK_PC2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart3_rtsn: rm-io18-uart3-rtsn { + rockchip,pins = + <0 RK_PC2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart4_tx: rm-io18-uart4-tx { + rockchip,pins = + <0 RK_PC2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart4_rx: rm-io18-uart4-rx { + rockchip,pins = + <0 RK_PC2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io18_uart4_ctsn: rm-io18-uart4-ctsn { + rockchip,pins = + <0 RK_PC2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_uart4_rtsn: rm-io18-uart4-rtsn { + rockchip,pins = + <0 RK_PC2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_mipite: rm-io18-mipite { + rockchip,pins = + <0 RK_PC2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_clk_32k: rm-io18-clk-32k { + rockchip,pins = + <0 RK_PC2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c0_scl: rm-io18-i2c0-scl { + rockchip,pins = + <0 RK_PC2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c0_sda: rm-io18-i2c0-sda { + rockchip,pins = + <0 RK_PC2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c1_scl: rm-io18-i2c1-scl { + rockchip,pins = + <0 RK_PC2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c1_sda: rm-io18-i2c1-sda { + rockchip,pins = + <0 RK_PC2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c2_scl: rm-io18-i2c2-scl { + rockchip,pins = + <0 RK_PC2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_i2c2_sda: rm-io18-i2c2-sda { + rockchip,pins = + <0 RK_PC2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_clk0: rm-io18-pdm-clk0 { + rockchip,pins = + <0 RK_PC2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_sdi0: rm-io18-pdm-sdi0 { + rockchip,pins = + <0 RK_PC2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_sdi1: rm-io18-pdm-sdi1 { + rockchip,pins = + <0 RK_PC2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_sdi2: rm-io18-pdm-sdi2 { + rockchip,pins = + <0 RK_PC2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_sdi3: rm-io18-pdm-sdi3 { + rockchip,pins = + <0 RK_PC2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_can1_tx: rm-io18-can1-tx { + rockchip,pins = + <0 RK_PC2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_can1_rx: rm-io18-can1-rx { + rockchip,pins = + <0 RK_PC2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_can0_tx: rm-io18-can0-tx { + rockchip,pins = + <0 RK_PC2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_can0_rx: rm-io18-can0-rx { + rockchip,pins = + <0 RK_PC2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm0_ch0: rm-io18-pwm0-ch0 { + rockchip,pins = + <0 RK_PC2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm0_ch1: rm-io18-pwm0-ch1 { + rockchip,pins = + <0 RK_PC2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm0_ch2: rm-io18-pwm0-ch2 { + rockchip,pins = + <0 RK_PC2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm0_ch3: rm-io18-pwm0-ch3 { + rockchip,pins = + <0 RK_PC2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch0: rm-io18-pwm1-ch0 { + rockchip,pins = + <0 RK_PC2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch1: rm-io18-pwm1-ch1 { + rockchip,pins = + <0 RK_PC2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch2: rm-io18-pwm1-ch2 { + rockchip,pins = + <0 RK_PC2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch3: rm-io18-pwm1-ch3 { + rockchip,pins = + <0 RK_PC2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch4: rm-io18-pwm1-ch4 { + rockchip,pins = + <0 RK_PC2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch5: rm-io18-pwm1-ch5 { + rockchip,pins = + <0 RK_PC2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch6: rm-io18-pwm1-ch6 { + rockchip,pins = + <0 RK_PC2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_ch7: rm-io18-pwm1-ch7 { + rockchip,pins = + <0 RK_PC2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_drive: rm-io18-touch-key-drive { + rockchip,pins = + <0 RK_PC2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in0: rm-io18-touch-key-in0 { + rockchip,pins = + <0 RK_PC2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in1: rm-io18-touch-key-in1 { + rockchip,pins = + <0 RK_PC2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in2: rm-io18-touch-key-in2 { + rockchip,pins = + <0 RK_PC2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in3: rm-io18-touch-key-in3 { + rockchip,pins = + <0 RK_PC2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in4: rm-io18-touch-key-in4 { + rockchip,pins = + <0 RK_PC2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in5: rm-io18-touch-key-in5 { + rockchip,pins = + <0 RK_PC2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in6: rm-io18-touch-key-in6 { + rockchip,pins = + <0 RK_PC2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_touch_key_in7: rm-io18-touch-key-in7 { + rockchip,pins = + <0 RK_PC2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_mclk: rm-io18-sai0-mclk { + rockchip,pins = + <0 RK_PC2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sclk: rm-io18-sai0-sclk { + rockchip,pins = + <0 RK_PC2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_lrck: rm-io18-sai0-lrck { + rockchip,pins = + <0 RK_PC2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sdi0: rm-io18-sai0-sdi0 { + rockchip,pins = + <0 RK_PC2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sdi1: rm-io18-sai0-sdi1 { + rockchip,pins = + <0 RK_PC2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sdi2: rm-io18-sai0-sdi2 { + rockchip,pins = + <0 RK_PC2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sdi3: rm-io18-sai0-sdi3 { + rockchip,pins = + <0 RK_PC2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai0_sdo: rm-io18-sai0-sdo { + rockchip,pins = + <0 RK_PC2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_mclk: rm-io18-sai1-mclk { + rockchip,pins = + <0 RK_PC2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sclk: rm-io18-sai1-sclk { + rockchip,pins = + <0 RK_PC2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_lrck: rm-io18-sai1-lrck { + rockchip,pins = + <0 RK_PC2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sdi: rm-io18-sai1-sdi { + rockchip,pins = + <0 RK_PC2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sdo0: rm-io18-sai1-sdo0 { + rockchip,pins = + <0 RK_PC2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sdo1: rm-io18-sai1-sdo1 { + rockchip,pins = + <0 RK_PC2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sdo2: rm-io18-sai1-sdo2 { + rockchip,pins = + <0 RK_PC2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_sai1_sdo3: rm-io18-sai1-sdo3 { + rockchip,pins = + <0 RK_PC2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi0_clk: rm-io18-spi0-clk { + rockchip,pins = + <0 RK_PC2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi0_mosi: rm-io18-spi0-mosi { + rockchip,pins = + <0 RK_PC2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi0_miso: rm-io18-spi0-miso { + rockchip,pins = + <0 RK_PC2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi0_csn0: rm-io18-spi0-csn0 { + rockchip,pins = + <0 RK_PC2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi0_csn1: rm-io18-spi0-csn1 { + rockchip,pins = + <0 RK_PC2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi1_clk: rm-io18-spi1-clk { + rockchip,pins = + <0 RK_PC2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi1_mosi: rm-io18-spi1-mosi { + rockchip,pins = + <0 RK_PC2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi1_miso: rm-io18-spi1-miso { + rockchip,pins = + <0 RK_PC2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi1_csn0: rm-io18-spi1-csn0 { + rockchip,pins = + <0 RK_PC2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spi1_csn1: rm-io18-spi1-csn1 { + rockchip,pins = + <0 RK_PC2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_wdt_tsadc_shut: rm-io18-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pmu_sleep: rm-io18-pmu-sleep { + rockchip,pins = + <0 RK_PC2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_core_power_off: rm-io18-core-power-off { + rockchip,pins = + <0 RK_PC2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spdif_tx: rm-io18-spdif-tx { + rockchip,pins = + <0 RK_PC2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_spdif_rx: rm-io18-spdif-rx { + rockchip,pins = + <0 RK_PC2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a0: rm-io18-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a1: rm-io18-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a2: rm-io18-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a3: rm-io18-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a4: rm-io18-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_a5: rm-io18-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b0: rm-io18-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b1: rm-io18-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b2: rm-io18-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b3: rm-io18-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b4: rm-io18-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pwm1_bip_cntr_b5: rm-io18-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_pdm_clk1: rm-io18-pdm-clk1 { + rockchip,pins = + <0 RK_PC2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_eth_rmii0_ppsclk: rm-io18-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_eth_rmii0_ppstrig: rm-io18-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_eth_rmii1_ppsclk: rm-io18-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io18_eth_rmii1_ppstrig: rm-io18-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC2 113 &pcfg_pull_none>; + }; + }; + + rm_io19 { + /omit-if-no-ref/ + rm_io19_uart1_tx: rm-io19-uart1-tx { + rockchip,pins = + <0 RK_PC3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart1_rx: rm-io19-uart1-rx { + rockchip,pins = + <0 RK_PC3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io19_uart2_tx: rm-io19-uart2-tx { + rockchip,pins = + <0 RK_PC3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart2_rx: rm-io19-uart2-rx { + rockchip,pins = + <0 RK_PC3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io19_uart3_tx: rm-io19-uart3-tx { + rockchip,pins = + <0 RK_PC3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart3_rx: rm-io19-uart3-rx { + rockchip,pins = + <0 RK_PC3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io19_uart3_ctsn: rm-io19-uart3-ctsn { + rockchip,pins = + <0 RK_PC3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart3_rtsn: rm-io19-uart3-rtsn { + rockchip,pins = + <0 RK_PC3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart4_tx: rm-io19-uart4-tx { + rockchip,pins = + <0 RK_PC3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart4_rx: rm-io19-uart4-rx { + rockchip,pins = + <0 RK_PC3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io19_uart4_ctsn: rm-io19-uart4-ctsn { + rockchip,pins = + <0 RK_PC3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_uart4_rtsn: rm-io19-uart4-rtsn { + rockchip,pins = + <0 RK_PC3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_mipite: rm-io19-mipite { + rockchip,pins = + <0 RK_PC3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_clk_32k: rm-io19-clk-32k { + rockchip,pins = + <0 RK_PC3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c0_scl: rm-io19-i2c0-scl { + rockchip,pins = + <0 RK_PC3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c0_sda: rm-io19-i2c0-sda { + rockchip,pins = + <0 RK_PC3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c1_scl: rm-io19-i2c1-scl { + rockchip,pins = + <0 RK_PC3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c1_sda: rm-io19-i2c1-sda { + rockchip,pins = + <0 RK_PC3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c2_scl: rm-io19-i2c2-scl { + rockchip,pins = + <0 RK_PC3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_i2c2_sda: rm-io19-i2c2-sda { + rockchip,pins = + <0 RK_PC3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_clk0: rm-io19-pdm-clk0 { + rockchip,pins = + <0 RK_PC3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_sdi0: rm-io19-pdm-sdi0 { + rockchip,pins = + <0 RK_PC3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_sdi1: rm-io19-pdm-sdi1 { + rockchip,pins = + <0 RK_PC3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_sdi2: rm-io19-pdm-sdi2 { + rockchip,pins = + <0 RK_PC3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_sdi3: rm-io19-pdm-sdi3 { + rockchip,pins = + <0 RK_PC3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_can1_tx: rm-io19-can1-tx { + rockchip,pins = + <0 RK_PC3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_can1_rx: rm-io19-can1-rx { + rockchip,pins = + <0 RK_PC3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_can0_tx: rm-io19-can0-tx { + rockchip,pins = + <0 RK_PC3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_can0_rx: rm-io19-can0-rx { + rockchip,pins = + <0 RK_PC3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm0_ch0: rm-io19-pwm0-ch0 { + rockchip,pins = + <0 RK_PC3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm0_ch1: rm-io19-pwm0-ch1 { + rockchip,pins = + <0 RK_PC3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm0_ch2: rm-io19-pwm0-ch2 { + rockchip,pins = + <0 RK_PC3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm0_ch3: rm-io19-pwm0-ch3 { + rockchip,pins = + <0 RK_PC3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch0: rm-io19-pwm1-ch0 { + rockchip,pins = + <0 RK_PC3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch1: rm-io19-pwm1-ch1 { + rockchip,pins = + <0 RK_PC3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch2: rm-io19-pwm1-ch2 { + rockchip,pins = + <0 RK_PC3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch3: rm-io19-pwm1-ch3 { + rockchip,pins = + <0 RK_PC3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch4: rm-io19-pwm1-ch4 { + rockchip,pins = + <0 RK_PC3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch5: rm-io19-pwm1-ch5 { + rockchip,pins = + <0 RK_PC3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch6: rm-io19-pwm1-ch6 { + rockchip,pins = + <0 RK_PC3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_ch7: rm-io19-pwm1-ch7 { + rockchip,pins = + <0 RK_PC3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_drive: rm-io19-touch-key-drive { + rockchip,pins = + <0 RK_PC3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in0: rm-io19-touch-key-in0 { + rockchip,pins = + <0 RK_PC3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in1: rm-io19-touch-key-in1 { + rockchip,pins = + <0 RK_PC3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in2: rm-io19-touch-key-in2 { + rockchip,pins = + <0 RK_PC3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in3: rm-io19-touch-key-in3 { + rockchip,pins = + <0 RK_PC3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in4: rm-io19-touch-key-in4 { + rockchip,pins = + <0 RK_PC3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in5: rm-io19-touch-key-in5 { + rockchip,pins = + <0 RK_PC3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in6: rm-io19-touch-key-in6 { + rockchip,pins = + <0 RK_PC3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_touch_key_in7: rm-io19-touch-key-in7 { + rockchip,pins = + <0 RK_PC3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_mclk: rm-io19-sai0-mclk { + rockchip,pins = + <0 RK_PC3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sclk: rm-io19-sai0-sclk { + rockchip,pins = + <0 RK_PC3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_lrck: rm-io19-sai0-lrck { + rockchip,pins = + <0 RK_PC3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sdi0: rm-io19-sai0-sdi0 { + rockchip,pins = + <0 RK_PC3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sdi1: rm-io19-sai0-sdi1 { + rockchip,pins = + <0 RK_PC3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sdi2: rm-io19-sai0-sdi2 { + rockchip,pins = + <0 RK_PC3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sdi3: rm-io19-sai0-sdi3 { + rockchip,pins = + <0 RK_PC3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai0_sdo: rm-io19-sai0-sdo { + rockchip,pins = + <0 RK_PC3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_mclk: rm-io19-sai1-mclk { + rockchip,pins = + <0 RK_PC3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sclk: rm-io19-sai1-sclk { + rockchip,pins = + <0 RK_PC3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_lrck: rm-io19-sai1-lrck { + rockchip,pins = + <0 RK_PC3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sdi: rm-io19-sai1-sdi { + rockchip,pins = + <0 RK_PC3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sdo0: rm-io19-sai1-sdo0 { + rockchip,pins = + <0 RK_PC3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sdo1: rm-io19-sai1-sdo1 { + rockchip,pins = + <0 RK_PC3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sdo2: rm-io19-sai1-sdo2 { + rockchip,pins = + <0 RK_PC3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_sai1_sdo3: rm-io19-sai1-sdo3 { + rockchip,pins = + <0 RK_PC3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi0_clk: rm-io19-spi0-clk { + rockchip,pins = + <0 RK_PC3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi0_mosi: rm-io19-spi0-mosi { + rockchip,pins = + <0 RK_PC3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi0_miso: rm-io19-spi0-miso { + rockchip,pins = + <0 RK_PC3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi0_csn0: rm-io19-spi0-csn0 { + rockchip,pins = + <0 RK_PC3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi0_csn1: rm-io19-spi0-csn1 { + rockchip,pins = + <0 RK_PC3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi1_clk: rm-io19-spi1-clk { + rockchip,pins = + <0 RK_PC3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi1_mosi: rm-io19-spi1-mosi { + rockchip,pins = + <0 RK_PC3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi1_miso: rm-io19-spi1-miso { + rockchip,pins = + <0 RK_PC3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi1_csn0: rm-io19-spi1-csn0 { + rockchip,pins = + <0 RK_PC3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spi1_csn1: rm-io19-spi1-csn1 { + rockchip,pins = + <0 RK_PC3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_wdt_tsadc_shut: rm-io19-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pmu_sleep: rm-io19-pmu-sleep { + rockchip,pins = + <0 RK_PC3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_core_power_off: rm-io19-core-power-off { + rockchip,pins = + <0 RK_PC3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spdif_tx: rm-io19-spdif-tx { + rockchip,pins = + <0 RK_PC3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_spdif_rx: rm-io19-spdif-rx { + rockchip,pins = + <0 RK_PC3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a0: rm-io19-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a1: rm-io19-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a2: rm-io19-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a3: rm-io19-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a4: rm-io19-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_a5: rm-io19-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b0: rm-io19-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b1: rm-io19-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b2: rm-io19-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b3: rm-io19-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b4: rm-io19-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pwm1_bip_cntr_b5: rm-io19-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_pdm_clk1: rm-io19-pdm-clk1 { + rockchip,pins = + <0 RK_PC3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_eth_rmii0_ppsclk: rm-io19-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_eth_rmii0_ppstrig: rm-io19-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_eth_rmii1_ppsclk: rm-io19-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io19_eth_rmii1_ppstrig: rm-io19-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC3 113 &pcfg_pull_none>; + }; + }; + + rm_io20 { + /omit-if-no-ref/ + rm_io20_uart1_tx: rm-io20-uart1-tx { + rockchip,pins = + <0 RK_PC4 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart1_rx: rm-io20-uart1-rx { + rockchip,pins = + <0 RK_PC4 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io20_uart2_tx: rm-io20-uart2-tx { + rockchip,pins = + <0 RK_PC4 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart2_rx: rm-io20-uart2-rx { + rockchip,pins = + <0 RK_PC4 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io20_uart3_tx: rm-io20-uart3-tx { + rockchip,pins = + <0 RK_PC4 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart3_rx: rm-io20-uart3-rx { + rockchip,pins = + <0 RK_PC4 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io20_uart3_ctsn: rm-io20-uart3-ctsn { + rockchip,pins = + <0 RK_PC4 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart3_rtsn: rm-io20-uart3-rtsn { + rockchip,pins = + <0 RK_PC4 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart4_tx: rm-io20-uart4-tx { + rockchip,pins = + <0 RK_PC4 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart4_rx: rm-io20-uart4-rx { + rockchip,pins = + <0 RK_PC4 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io20_uart4_ctsn: rm-io20-uart4-ctsn { + rockchip,pins = + <0 RK_PC4 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_uart4_rtsn: rm-io20-uart4-rtsn { + rockchip,pins = + <0 RK_PC4 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_mipite: rm-io20-mipite { + rockchip,pins = + <0 RK_PC4 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_clk_32k: rm-io20-clk-32k { + rockchip,pins = + <0 RK_PC4 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c0_scl: rm-io20-i2c0-scl { + rockchip,pins = + <0 RK_PC4 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c0_sda: rm-io20-i2c0-sda { + rockchip,pins = + <0 RK_PC4 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c1_scl: rm-io20-i2c1-scl { + rockchip,pins = + <0 RK_PC4 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c1_sda: rm-io20-i2c1-sda { + rockchip,pins = + <0 RK_PC4 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c2_scl: rm-io20-i2c2-scl { + rockchip,pins = + <0 RK_PC4 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_i2c2_sda: rm-io20-i2c2-sda { + rockchip,pins = + <0 RK_PC4 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_clk0: rm-io20-pdm-clk0 { + rockchip,pins = + <0 RK_PC4 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_sdi0: rm-io20-pdm-sdi0 { + rockchip,pins = + <0 RK_PC4 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_sdi1: rm-io20-pdm-sdi1 { + rockchip,pins = + <0 RK_PC4 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_sdi2: rm-io20-pdm-sdi2 { + rockchip,pins = + <0 RK_PC4 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_sdi3: rm-io20-pdm-sdi3 { + rockchip,pins = + <0 RK_PC4 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_can1_tx: rm-io20-can1-tx { + rockchip,pins = + <0 RK_PC4 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_can1_rx: rm-io20-can1-rx { + rockchip,pins = + <0 RK_PC4 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_can0_tx: rm-io20-can0-tx { + rockchip,pins = + <0 RK_PC4 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_can0_rx: rm-io20-can0-rx { + rockchip,pins = + <0 RK_PC4 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm0_ch0: rm-io20-pwm0-ch0 { + rockchip,pins = + <0 RK_PC4 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm0_ch1: rm-io20-pwm0-ch1 { + rockchip,pins = + <0 RK_PC4 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm0_ch2: rm-io20-pwm0-ch2 { + rockchip,pins = + <0 RK_PC4 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm0_ch3: rm-io20-pwm0-ch3 { + rockchip,pins = + <0 RK_PC4 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch0: rm-io20-pwm1-ch0 { + rockchip,pins = + <0 RK_PC4 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch1: rm-io20-pwm1-ch1 { + rockchip,pins = + <0 RK_PC4 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch2: rm-io20-pwm1-ch2 { + rockchip,pins = + <0 RK_PC4 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch3: rm-io20-pwm1-ch3 { + rockchip,pins = + <0 RK_PC4 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch4: rm-io20-pwm1-ch4 { + rockchip,pins = + <0 RK_PC4 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch5: rm-io20-pwm1-ch5 { + rockchip,pins = + <0 RK_PC4 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch6: rm-io20-pwm1-ch6 { + rockchip,pins = + <0 RK_PC4 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_ch7: rm-io20-pwm1-ch7 { + rockchip,pins = + <0 RK_PC4 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_drive: rm-io20-touch-key-drive { + rockchip,pins = + <0 RK_PC4 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in0: rm-io20-touch-key-in0 { + rockchip,pins = + <0 RK_PC4 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in1: rm-io20-touch-key-in1 { + rockchip,pins = + <0 RK_PC4 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in2: rm-io20-touch-key-in2 { + rockchip,pins = + <0 RK_PC4 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in3: rm-io20-touch-key-in3 { + rockchip,pins = + <0 RK_PC4 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in4: rm-io20-touch-key-in4 { + rockchip,pins = + <0 RK_PC4 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in5: rm-io20-touch-key-in5 { + rockchip,pins = + <0 RK_PC4 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in6: rm-io20-touch-key-in6 { + rockchip,pins = + <0 RK_PC4 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_touch_key_in7: rm-io20-touch-key-in7 { + rockchip,pins = + <0 RK_PC4 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_mclk: rm-io20-sai0-mclk { + rockchip,pins = + <0 RK_PC4 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sclk: rm-io20-sai0-sclk { + rockchip,pins = + <0 RK_PC4 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_lrck: rm-io20-sai0-lrck { + rockchip,pins = + <0 RK_PC4 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sdi0: rm-io20-sai0-sdi0 { + rockchip,pins = + <0 RK_PC4 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sdi1: rm-io20-sai0-sdi1 { + rockchip,pins = + <0 RK_PC4 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sdi2: rm-io20-sai0-sdi2 { + rockchip,pins = + <0 RK_PC4 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sdi3: rm-io20-sai0-sdi3 { + rockchip,pins = + <0 RK_PC4 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai0_sdo: rm-io20-sai0-sdo { + rockchip,pins = + <0 RK_PC4 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_mclk: rm-io20-sai1-mclk { + rockchip,pins = + <0 RK_PC4 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sclk: rm-io20-sai1-sclk { + rockchip,pins = + <0 RK_PC4 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_lrck: rm-io20-sai1-lrck { + rockchip,pins = + <0 RK_PC4 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sdi: rm-io20-sai1-sdi { + rockchip,pins = + <0 RK_PC4 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sdo0: rm-io20-sai1-sdo0 { + rockchip,pins = + <0 RK_PC4 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sdo1: rm-io20-sai1-sdo1 { + rockchip,pins = + <0 RK_PC4 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sdo2: rm-io20-sai1-sdo2 { + rockchip,pins = + <0 RK_PC4 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_sai1_sdo3: rm-io20-sai1-sdo3 { + rockchip,pins = + <0 RK_PC4 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi0_clk: rm-io20-spi0-clk { + rockchip,pins = + <0 RK_PC4 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi0_mosi: rm-io20-spi0-mosi { + rockchip,pins = + <0 RK_PC4 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi0_miso: rm-io20-spi0-miso { + rockchip,pins = + <0 RK_PC4 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi0_csn0: rm-io20-spi0-csn0 { + rockchip,pins = + <0 RK_PC4 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi0_csn1: rm-io20-spi0-csn1 { + rockchip,pins = + <0 RK_PC4 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi1_clk: rm-io20-spi1-clk { + rockchip,pins = + <0 RK_PC4 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi1_mosi: rm-io20-spi1-mosi { + rockchip,pins = + <0 RK_PC4 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi1_miso: rm-io20-spi1-miso { + rockchip,pins = + <0 RK_PC4 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi1_csn0: rm-io20-spi1-csn0 { + rockchip,pins = + <0 RK_PC4 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spi1_csn1: rm-io20-spi1-csn1 { + rockchip,pins = + <0 RK_PC4 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_wdt_tsadc_shut: rm-io20-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC4 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pmu_sleep: rm-io20-pmu-sleep { + rockchip,pins = + <0 RK_PC4 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_core_power_off: rm-io20-core-power-off { + rockchip,pins = + <0 RK_PC4 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spdif_tx: rm-io20-spdif-tx { + rockchip,pins = + <0 RK_PC4 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_spdif_rx: rm-io20-spdif-rx { + rockchip,pins = + <0 RK_PC4 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a0: rm-io20-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC4 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a1: rm-io20-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC4 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a2: rm-io20-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC4 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a3: rm-io20-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC4 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a4: rm-io20-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC4 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_a5: rm-io20-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC4 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b0: rm-io20-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC4 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b1: rm-io20-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC4 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b2: rm-io20-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC4 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b3: rm-io20-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC4 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b4: rm-io20-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC4 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pwm1_bip_cntr_b5: rm-io20-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC4 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_pdm_clk1: rm-io20-pdm-clk1 { + rockchip,pins = + <0 RK_PC4 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_eth_rmii0_ppsclk: rm-io20-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC4 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_eth_rmii0_ppstrig: rm-io20-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC4 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_eth_rmii1_ppsclk: rm-io20-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC4 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io20_eth_rmii1_ppstrig: rm-io20-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC4 113 &pcfg_pull_none>; + }; + }; + + rm_io21 { + /omit-if-no-ref/ + rm_io21_uart1_tx: rm-io21-uart1-tx { + rockchip,pins = + <0 RK_PC5 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart1_rx: rm-io21-uart1-rx { + rockchip,pins = + <0 RK_PC5 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io21_uart2_tx: rm-io21-uart2-tx { + rockchip,pins = + <0 RK_PC5 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart2_rx: rm-io21-uart2-rx { + rockchip,pins = + <0 RK_PC5 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io21_uart3_tx: rm-io21-uart3-tx { + rockchip,pins = + <0 RK_PC5 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart3_rx: rm-io21-uart3-rx { + rockchip,pins = + <0 RK_PC5 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io21_uart3_ctsn: rm-io21-uart3-ctsn { + rockchip,pins = + <0 RK_PC5 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart3_rtsn: rm-io21-uart3-rtsn { + rockchip,pins = + <0 RK_PC5 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart4_tx: rm-io21-uart4-tx { + rockchip,pins = + <0 RK_PC5 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart4_rx: rm-io21-uart4-rx { + rockchip,pins = + <0 RK_PC5 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io21_uart4_ctsn: rm-io21-uart4-ctsn { + rockchip,pins = + <0 RK_PC5 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_uart4_rtsn: rm-io21-uart4-rtsn { + rockchip,pins = + <0 RK_PC5 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_mipite: rm-io21-mipite { + rockchip,pins = + <0 RK_PC5 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_clk_32k: rm-io21-clk-32k { + rockchip,pins = + <0 RK_PC5 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c0_scl: rm-io21-i2c0-scl { + rockchip,pins = + <0 RK_PC5 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c0_sda: rm-io21-i2c0-sda { + rockchip,pins = + <0 RK_PC5 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c1_scl: rm-io21-i2c1-scl { + rockchip,pins = + <0 RK_PC5 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c1_sda: rm-io21-i2c1-sda { + rockchip,pins = + <0 RK_PC5 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c2_scl: rm-io21-i2c2-scl { + rockchip,pins = + <0 RK_PC5 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_i2c2_sda: rm-io21-i2c2-sda { + rockchip,pins = + <0 RK_PC5 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_clk0: rm-io21-pdm-clk0 { + rockchip,pins = + <0 RK_PC5 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_sdi0: rm-io21-pdm-sdi0 { + rockchip,pins = + <0 RK_PC5 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_sdi1: rm-io21-pdm-sdi1 { + rockchip,pins = + <0 RK_PC5 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_sdi2: rm-io21-pdm-sdi2 { + rockchip,pins = + <0 RK_PC5 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_sdi3: rm-io21-pdm-sdi3 { + rockchip,pins = + <0 RK_PC5 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_can1_tx: rm-io21-can1-tx { + rockchip,pins = + <0 RK_PC5 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_can1_rx: rm-io21-can1-rx { + rockchip,pins = + <0 RK_PC5 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_can0_tx: rm-io21-can0-tx { + rockchip,pins = + <0 RK_PC5 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_can0_rx: rm-io21-can0-rx { + rockchip,pins = + <0 RK_PC5 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm0_ch0: rm-io21-pwm0-ch0 { + rockchip,pins = + <0 RK_PC5 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm0_ch1: rm-io21-pwm0-ch1 { + rockchip,pins = + <0 RK_PC5 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm0_ch2: rm-io21-pwm0-ch2 { + rockchip,pins = + <0 RK_PC5 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm0_ch3: rm-io21-pwm0-ch3 { + rockchip,pins = + <0 RK_PC5 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch0: rm-io21-pwm1-ch0 { + rockchip,pins = + <0 RK_PC5 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch1: rm-io21-pwm1-ch1 { + rockchip,pins = + <0 RK_PC5 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch2: rm-io21-pwm1-ch2 { + rockchip,pins = + <0 RK_PC5 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch3: rm-io21-pwm1-ch3 { + rockchip,pins = + <0 RK_PC5 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch4: rm-io21-pwm1-ch4 { + rockchip,pins = + <0 RK_PC5 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch5: rm-io21-pwm1-ch5 { + rockchip,pins = + <0 RK_PC5 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch6: rm-io21-pwm1-ch6 { + rockchip,pins = + <0 RK_PC5 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_ch7: rm-io21-pwm1-ch7 { + rockchip,pins = + <0 RK_PC5 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_drive: rm-io21-touch-key-drive { + rockchip,pins = + <0 RK_PC5 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in0: rm-io21-touch-key-in0 { + rockchip,pins = + <0 RK_PC5 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in1: rm-io21-touch-key-in1 { + rockchip,pins = + <0 RK_PC5 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in2: rm-io21-touch-key-in2 { + rockchip,pins = + <0 RK_PC5 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in3: rm-io21-touch-key-in3 { + rockchip,pins = + <0 RK_PC5 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in4: rm-io21-touch-key-in4 { + rockchip,pins = + <0 RK_PC5 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in5: rm-io21-touch-key-in5 { + rockchip,pins = + <0 RK_PC5 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in6: rm-io21-touch-key-in6 { + rockchip,pins = + <0 RK_PC5 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_touch_key_in7: rm-io21-touch-key-in7 { + rockchip,pins = + <0 RK_PC5 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_mclk: rm-io21-sai0-mclk { + rockchip,pins = + <0 RK_PC5 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sclk: rm-io21-sai0-sclk { + rockchip,pins = + <0 RK_PC5 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_lrck: rm-io21-sai0-lrck { + rockchip,pins = + <0 RK_PC5 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sdi0: rm-io21-sai0-sdi0 { + rockchip,pins = + <0 RK_PC5 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sdi1: rm-io21-sai0-sdi1 { + rockchip,pins = + <0 RK_PC5 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sdi2: rm-io21-sai0-sdi2 { + rockchip,pins = + <0 RK_PC5 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sdi3: rm-io21-sai0-sdi3 { + rockchip,pins = + <0 RK_PC5 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai0_sdo: rm-io21-sai0-sdo { + rockchip,pins = + <0 RK_PC5 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_mclk: rm-io21-sai1-mclk { + rockchip,pins = + <0 RK_PC5 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sclk: rm-io21-sai1-sclk { + rockchip,pins = + <0 RK_PC5 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_lrck: rm-io21-sai1-lrck { + rockchip,pins = + <0 RK_PC5 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sdi: rm-io21-sai1-sdi { + rockchip,pins = + <0 RK_PC5 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sdo0: rm-io21-sai1-sdo0 { + rockchip,pins = + <0 RK_PC5 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sdo1: rm-io21-sai1-sdo1 { + rockchip,pins = + <0 RK_PC5 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sdo2: rm-io21-sai1-sdo2 { + rockchip,pins = + <0 RK_PC5 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_sai1_sdo3: rm-io21-sai1-sdo3 { + rockchip,pins = + <0 RK_PC5 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi0_clk: rm-io21-spi0-clk { + rockchip,pins = + <0 RK_PC5 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi0_mosi: rm-io21-spi0-mosi { + rockchip,pins = + <0 RK_PC5 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi0_miso: rm-io21-spi0-miso { + rockchip,pins = + <0 RK_PC5 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi0_csn0: rm-io21-spi0-csn0 { + rockchip,pins = + <0 RK_PC5 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi0_csn1: rm-io21-spi0-csn1 { + rockchip,pins = + <0 RK_PC5 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi1_clk: rm-io21-spi1-clk { + rockchip,pins = + <0 RK_PC5 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi1_mosi: rm-io21-spi1-mosi { + rockchip,pins = + <0 RK_PC5 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi1_miso: rm-io21-spi1-miso { + rockchip,pins = + <0 RK_PC5 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi1_csn0: rm-io21-spi1-csn0 { + rockchip,pins = + <0 RK_PC5 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spi1_csn1: rm-io21-spi1-csn1 { + rockchip,pins = + <0 RK_PC5 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_wdt_tsadc_shut: rm-io21-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC5 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pmu_sleep: rm-io21-pmu-sleep { + rockchip,pins = + <0 RK_PC5 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_core_power_off: rm-io21-core-power-off { + rockchip,pins = + <0 RK_PC5 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spdif_tx: rm-io21-spdif-tx { + rockchip,pins = + <0 RK_PC5 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_spdif_rx: rm-io21-spdif-rx { + rockchip,pins = + <0 RK_PC5 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a0: rm-io21-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC5 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a1: rm-io21-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC5 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a2: rm-io21-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC5 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a3: rm-io21-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC5 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a4: rm-io21-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC5 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_a5: rm-io21-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC5 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b0: rm-io21-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC5 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b1: rm-io21-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC5 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b2: rm-io21-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC5 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b3: rm-io21-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC5 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b4: rm-io21-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC5 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pwm1_bip_cntr_b5: rm-io21-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC5 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_pdm_clk1: rm-io21-pdm-clk1 { + rockchip,pins = + <0 RK_PC5 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_eth_rmii0_ppsclk: rm-io21-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC5 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_eth_rmii0_ppstrig: rm-io21-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC5 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_eth_rmii1_ppsclk: rm-io21-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC5 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io21_eth_rmii1_ppstrig: rm-io21-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC5 113 &pcfg_pull_none>; + }; + }; + + rm_io22 { + /omit-if-no-ref/ + rm_io22_uart1_tx: rm-io22-uart1-tx { + rockchip,pins = + <0 RK_PC6 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart1_rx: rm-io22-uart1-rx { + rockchip,pins = + <0 RK_PC6 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io22_uart2_tx: rm-io22-uart2-tx { + rockchip,pins = + <0 RK_PC6 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart2_rx: rm-io22-uart2-rx { + rockchip,pins = + <0 RK_PC6 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io22_uart3_tx: rm-io22-uart3-tx { + rockchip,pins = + <0 RK_PC6 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart3_rx: rm-io22-uart3-rx { + rockchip,pins = + <0 RK_PC6 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io22_uart3_ctsn: rm-io22-uart3-ctsn { + rockchip,pins = + <0 RK_PC6 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart3_rtsn: rm-io22-uart3-rtsn { + rockchip,pins = + <0 RK_PC6 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart4_tx: rm-io22-uart4-tx { + rockchip,pins = + <0 RK_PC6 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart4_rx: rm-io22-uart4-rx { + rockchip,pins = + <0 RK_PC6 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io22_uart4_ctsn: rm-io22-uart4-ctsn { + rockchip,pins = + <0 RK_PC6 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_uart4_rtsn: rm-io22-uart4-rtsn { + rockchip,pins = + <0 RK_PC6 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_mipite: rm-io22-mipite { + rockchip,pins = + <0 RK_PC6 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_clk_32k: rm-io22-clk-32k { + rockchip,pins = + <0 RK_PC6 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c0_scl: rm-io22-i2c0-scl { + rockchip,pins = + <0 RK_PC6 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c0_sda: rm-io22-i2c0-sda { + rockchip,pins = + <0 RK_PC6 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c1_scl: rm-io22-i2c1-scl { + rockchip,pins = + <0 RK_PC6 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c1_sda: rm-io22-i2c1-sda { + rockchip,pins = + <0 RK_PC6 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c2_scl: rm-io22-i2c2-scl { + rockchip,pins = + <0 RK_PC6 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_i2c2_sda: rm-io22-i2c2-sda { + rockchip,pins = + <0 RK_PC6 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_clk0: rm-io22-pdm-clk0 { + rockchip,pins = + <0 RK_PC6 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_sdi0: rm-io22-pdm-sdi0 { + rockchip,pins = + <0 RK_PC6 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_sdi1: rm-io22-pdm-sdi1 { + rockchip,pins = + <0 RK_PC6 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_sdi2: rm-io22-pdm-sdi2 { + rockchip,pins = + <0 RK_PC6 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_sdi3: rm-io22-pdm-sdi3 { + rockchip,pins = + <0 RK_PC6 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_can1_tx: rm-io22-can1-tx { + rockchip,pins = + <0 RK_PC6 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_can1_rx: rm-io22-can1-rx { + rockchip,pins = + <0 RK_PC6 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_can0_tx: rm-io22-can0-tx { + rockchip,pins = + <0 RK_PC6 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_can0_rx: rm-io22-can0-rx { + rockchip,pins = + <0 RK_PC6 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm0_ch0: rm-io22-pwm0-ch0 { + rockchip,pins = + <0 RK_PC6 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm0_ch1: rm-io22-pwm0-ch1 { + rockchip,pins = + <0 RK_PC6 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm0_ch2: rm-io22-pwm0-ch2 { + rockchip,pins = + <0 RK_PC6 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm0_ch3: rm-io22-pwm0-ch3 { + rockchip,pins = + <0 RK_PC6 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch0: rm-io22-pwm1-ch0 { + rockchip,pins = + <0 RK_PC6 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch1: rm-io22-pwm1-ch1 { + rockchip,pins = + <0 RK_PC6 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch2: rm-io22-pwm1-ch2 { + rockchip,pins = + <0 RK_PC6 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch3: rm-io22-pwm1-ch3 { + rockchip,pins = + <0 RK_PC6 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch4: rm-io22-pwm1-ch4 { + rockchip,pins = + <0 RK_PC6 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch5: rm-io22-pwm1-ch5 { + rockchip,pins = + <0 RK_PC6 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch6: rm-io22-pwm1-ch6 { + rockchip,pins = + <0 RK_PC6 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_ch7: rm-io22-pwm1-ch7 { + rockchip,pins = + <0 RK_PC6 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_drive: rm-io22-touch-key-drive { + rockchip,pins = + <0 RK_PC6 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in0: rm-io22-touch-key-in0 { + rockchip,pins = + <0 RK_PC6 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in1: rm-io22-touch-key-in1 { + rockchip,pins = + <0 RK_PC6 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in2: rm-io22-touch-key-in2 { + rockchip,pins = + <0 RK_PC6 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in3: rm-io22-touch-key-in3 { + rockchip,pins = + <0 RK_PC6 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in4: rm-io22-touch-key-in4 { + rockchip,pins = + <0 RK_PC6 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in5: rm-io22-touch-key-in5 { + rockchip,pins = + <0 RK_PC6 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in6: rm-io22-touch-key-in6 { + rockchip,pins = + <0 RK_PC6 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_touch_key_in7: rm-io22-touch-key-in7 { + rockchip,pins = + <0 RK_PC6 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_mclk: rm-io22-sai0-mclk { + rockchip,pins = + <0 RK_PC6 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sclk: rm-io22-sai0-sclk { + rockchip,pins = + <0 RK_PC6 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_lrck: rm-io22-sai0-lrck { + rockchip,pins = + <0 RK_PC6 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sdi0: rm-io22-sai0-sdi0 { + rockchip,pins = + <0 RK_PC6 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sdi1: rm-io22-sai0-sdi1 { + rockchip,pins = + <0 RK_PC6 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sdi2: rm-io22-sai0-sdi2 { + rockchip,pins = + <0 RK_PC6 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sdi3: rm-io22-sai0-sdi3 { + rockchip,pins = + <0 RK_PC6 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai0_sdo: rm-io22-sai0-sdo { + rockchip,pins = + <0 RK_PC6 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_mclk: rm-io22-sai1-mclk { + rockchip,pins = + <0 RK_PC6 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sclk: rm-io22-sai1-sclk { + rockchip,pins = + <0 RK_PC6 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_lrck: rm-io22-sai1-lrck { + rockchip,pins = + <0 RK_PC6 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sdi: rm-io22-sai1-sdi { + rockchip,pins = + <0 RK_PC6 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sdo0: rm-io22-sai1-sdo0 { + rockchip,pins = + <0 RK_PC6 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sdo1: rm-io22-sai1-sdo1 { + rockchip,pins = + <0 RK_PC6 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sdo2: rm-io22-sai1-sdo2 { + rockchip,pins = + <0 RK_PC6 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_sai1_sdo3: rm-io22-sai1-sdo3 { + rockchip,pins = + <0 RK_PC6 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi0_clk: rm-io22-spi0-clk { + rockchip,pins = + <0 RK_PC6 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi0_mosi: rm-io22-spi0-mosi { + rockchip,pins = + <0 RK_PC6 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi0_miso: rm-io22-spi0-miso { + rockchip,pins = + <0 RK_PC6 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi0_csn0: rm-io22-spi0-csn0 { + rockchip,pins = + <0 RK_PC6 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi0_csn1: rm-io22-spi0-csn1 { + rockchip,pins = + <0 RK_PC6 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi1_clk: rm-io22-spi1-clk { + rockchip,pins = + <0 RK_PC6 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi1_mosi: rm-io22-spi1-mosi { + rockchip,pins = + <0 RK_PC6 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi1_miso: rm-io22-spi1-miso { + rockchip,pins = + <0 RK_PC6 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi1_csn0: rm-io22-spi1-csn0 { + rockchip,pins = + <0 RK_PC6 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spi1_csn1: rm-io22-spi1-csn1 { + rockchip,pins = + <0 RK_PC6 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_wdt_tsadc_shut: rm-io22-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC6 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pmu_sleep: rm-io22-pmu-sleep { + rockchip,pins = + <0 RK_PC6 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_core_power_off: rm-io22-core-power-off { + rockchip,pins = + <0 RK_PC6 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spdif_tx: rm-io22-spdif-tx { + rockchip,pins = + <0 RK_PC6 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_spdif_rx: rm-io22-spdif-rx { + rockchip,pins = + <0 RK_PC6 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a0: rm-io22-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC6 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a1: rm-io22-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC6 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a2: rm-io22-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC6 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a3: rm-io22-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC6 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a4: rm-io22-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC6 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_a5: rm-io22-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC6 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b0: rm-io22-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC6 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b1: rm-io22-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC6 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b2: rm-io22-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC6 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b3: rm-io22-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC6 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b4: rm-io22-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC6 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pwm1_bip_cntr_b5: rm-io22-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC6 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_pdm_clk1: rm-io22-pdm-clk1 { + rockchip,pins = + <0 RK_PC6 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_eth_rmii0_ppsclk: rm-io22-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC6 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_eth_rmii0_ppstrig: rm-io22-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC6 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_eth_rmii1_ppsclk: rm-io22-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC6 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io22_eth_rmii1_ppstrig: rm-io22-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC6 113 &pcfg_pull_none>; + }; + }; + + rm_io23 { + /omit-if-no-ref/ + rm_io23_uart1_tx: rm-io23-uart1-tx { + rockchip,pins = + <0 RK_PC7 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart1_rx: rm-io23-uart1-rx { + rockchip,pins = + <0 RK_PC7 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io23_uart2_tx: rm-io23-uart2-tx { + rockchip,pins = + <0 RK_PC7 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart2_rx: rm-io23-uart2-rx { + rockchip,pins = + <0 RK_PC7 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io23_uart3_tx: rm-io23-uart3-tx { + rockchip,pins = + <0 RK_PC7 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart3_rx: rm-io23-uart3-rx { + rockchip,pins = + <0 RK_PC7 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io23_uart3_ctsn: rm-io23-uart3-ctsn { + rockchip,pins = + <0 RK_PC7 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart3_rtsn: rm-io23-uart3-rtsn { + rockchip,pins = + <0 RK_PC7 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart4_tx: rm-io23-uart4-tx { + rockchip,pins = + <0 RK_PC7 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart4_rx: rm-io23-uart4-rx { + rockchip,pins = + <0 RK_PC7 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io23_uart4_ctsn: rm-io23-uart4-ctsn { + rockchip,pins = + <0 RK_PC7 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_uart4_rtsn: rm-io23-uart4-rtsn { + rockchip,pins = + <0 RK_PC7 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_mipite: rm-io23-mipite { + rockchip,pins = + <0 RK_PC7 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_clk_32k: rm-io23-clk-32k { + rockchip,pins = + <0 RK_PC7 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c0_scl: rm-io23-i2c0-scl { + rockchip,pins = + <0 RK_PC7 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c0_sda: rm-io23-i2c0-sda { + rockchip,pins = + <0 RK_PC7 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c1_scl: rm-io23-i2c1-scl { + rockchip,pins = + <0 RK_PC7 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c1_sda: rm-io23-i2c1-sda { + rockchip,pins = + <0 RK_PC7 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c2_scl: rm-io23-i2c2-scl { + rockchip,pins = + <0 RK_PC7 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_i2c2_sda: rm-io23-i2c2-sda { + rockchip,pins = + <0 RK_PC7 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_clk0: rm-io23-pdm-clk0 { + rockchip,pins = + <0 RK_PC7 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_sdi0: rm-io23-pdm-sdi0 { + rockchip,pins = + <0 RK_PC7 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_sdi1: rm-io23-pdm-sdi1 { + rockchip,pins = + <0 RK_PC7 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_sdi2: rm-io23-pdm-sdi2 { + rockchip,pins = + <0 RK_PC7 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_sdi3: rm-io23-pdm-sdi3 { + rockchip,pins = + <0 RK_PC7 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_can1_tx: rm-io23-can1-tx { + rockchip,pins = + <0 RK_PC7 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_can1_rx: rm-io23-can1-rx { + rockchip,pins = + <0 RK_PC7 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_can0_tx: rm-io23-can0-tx { + rockchip,pins = + <0 RK_PC7 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_can0_rx: rm-io23-can0-rx { + rockchip,pins = + <0 RK_PC7 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm0_ch0: rm-io23-pwm0-ch0 { + rockchip,pins = + <0 RK_PC7 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm0_ch1: rm-io23-pwm0-ch1 { + rockchip,pins = + <0 RK_PC7 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm0_ch2: rm-io23-pwm0-ch2 { + rockchip,pins = + <0 RK_PC7 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm0_ch3: rm-io23-pwm0-ch3 { + rockchip,pins = + <0 RK_PC7 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch0: rm-io23-pwm1-ch0 { + rockchip,pins = + <0 RK_PC7 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch1: rm-io23-pwm1-ch1 { + rockchip,pins = + <0 RK_PC7 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch2: rm-io23-pwm1-ch2 { + rockchip,pins = + <0 RK_PC7 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch3: rm-io23-pwm1-ch3 { + rockchip,pins = + <0 RK_PC7 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch4: rm-io23-pwm1-ch4 { + rockchip,pins = + <0 RK_PC7 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch5: rm-io23-pwm1-ch5 { + rockchip,pins = + <0 RK_PC7 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch6: rm-io23-pwm1-ch6 { + rockchip,pins = + <0 RK_PC7 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_ch7: rm-io23-pwm1-ch7 { + rockchip,pins = + <0 RK_PC7 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_drive: rm-io23-touch-key-drive { + rockchip,pins = + <0 RK_PC7 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in0: rm-io23-touch-key-in0 { + rockchip,pins = + <0 RK_PC7 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in1: rm-io23-touch-key-in1 { + rockchip,pins = + <0 RK_PC7 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in2: rm-io23-touch-key-in2 { + rockchip,pins = + <0 RK_PC7 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in3: rm-io23-touch-key-in3 { + rockchip,pins = + <0 RK_PC7 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in4: rm-io23-touch-key-in4 { + rockchip,pins = + <0 RK_PC7 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in5: rm-io23-touch-key-in5 { + rockchip,pins = + <0 RK_PC7 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in6: rm-io23-touch-key-in6 { + rockchip,pins = + <0 RK_PC7 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_touch_key_in7: rm-io23-touch-key-in7 { + rockchip,pins = + <0 RK_PC7 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_mclk: rm-io23-sai0-mclk { + rockchip,pins = + <0 RK_PC7 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sclk: rm-io23-sai0-sclk { + rockchip,pins = + <0 RK_PC7 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_lrck: rm-io23-sai0-lrck { + rockchip,pins = + <0 RK_PC7 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sdi0: rm-io23-sai0-sdi0 { + rockchip,pins = + <0 RK_PC7 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sdi1: rm-io23-sai0-sdi1 { + rockchip,pins = + <0 RK_PC7 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sdi2: rm-io23-sai0-sdi2 { + rockchip,pins = + <0 RK_PC7 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sdi3: rm-io23-sai0-sdi3 { + rockchip,pins = + <0 RK_PC7 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai0_sdo: rm-io23-sai0-sdo { + rockchip,pins = + <0 RK_PC7 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_mclk: rm-io23-sai1-mclk { + rockchip,pins = + <0 RK_PC7 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sclk: rm-io23-sai1-sclk { + rockchip,pins = + <0 RK_PC7 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_lrck: rm-io23-sai1-lrck { + rockchip,pins = + <0 RK_PC7 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sdi: rm-io23-sai1-sdi { + rockchip,pins = + <0 RK_PC7 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sdo0: rm-io23-sai1-sdo0 { + rockchip,pins = + <0 RK_PC7 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sdo1: rm-io23-sai1-sdo1 { + rockchip,pins = + <0 RK_PC7 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sdo2: rm-io23-sai1-sdo2 { + rockchip,pins = + <0 RK_PC7 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_sai1_sdo3: rm-io23-sai1-sdo3 { + rockchip,pins = + <0 RK_PC7 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi0_clk: rm-io23-spi0-clk { + rockchip,pins = + <0 RK_PC7 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi0_mosi: rm-io23-spi0-mosi { + rockchip,pins = + <0 RK_PC7 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi0_miso: rm-io23-spi0-miso { + rockchip,pins = + <0 RK_PC7 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi0_csn0: rm-io23-spi0-csn0 { + rockchip,pins = + <0 RK_PC7 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi0_csn1: rm-io23-spi0-csn1 { + rockchip,pins = + <0 RK_PC7 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi1_clk: rm-io23-spi1-clk { + rockchip,pins = + <0 RK_PC7 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi1_mosi: rm-io23-spi1-mosi { + rockchip,pins = + <0 RK_PC7 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi1_miso: rm-io23-spi1-miso { + rockchip,pins = + <0 RK_PC7 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi1_csn0: rm-io23-spi1-csn0 { + rockchip,pins = + <0 RK_PC7 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spi1_csn1: rm-io23-spi1-csn1 { + rockchip,pins = + <0 RK_PC7 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_wdt_tsadc_shut: rm-io23-wdt-tsadc-shut { + rockchip,pins = + <0 RK_PC7 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pmu_sleep: rm-io23-pmu-sleep { + rockchip,pins = + <0 RK_PC7 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_core_power_off: rm-io23-core-power-off { + rockchip,pins = + <0 RK_PC7 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spdif_tx: rm-io23-spdif-tx { + rockchip,pins = + <0 RK_PC7 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_spdif_rx: rm-io23-spdif-rx { + rockchip,pins = + <0 RK_PC7 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a0: rm-io23-pwm1-bip-cntr-a0 { + rockchip,pins = + <0 RK_PC7 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a1: rm-io23-pwm1-bip-cntr-a1 { + rockchip,pins = + <0 RK_PC7 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a2: rm-io23-pwm1-bip-cntr-a2 { + rockchip,pins = + <0 RK_PC7 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a3: rm-io23-pwm1-bip-cntr-a3 { + rockchip,pins = + <0 RK_PC7 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a4: rm-io23-pwm1-bip-cntr-a4 { + rockchip,pins = + <0 RK_PC7 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_a5: rm-io23-pwm1-bip-cntr-a5 { + rockchip,pins = + <0 RK_PC7 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b0: rm-io23-pwm1-bip-cntr-b0 { + rockchip,pins = + <0 RK_PC7 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b1: rm-io23-pwm1-bip-cntr-b1 { + rockchip,pins = + <0 RK_PC7 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b2: rm-io23-pwm1-bip-cntr-b2 { + rockchip,pins = + <0 RK_PC7 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b3: rm-io23-pwm1-bip-cntr-b3 { + rockchip,pins = + <0 RK_PC7 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b4: rm-io23-pwm1-bip-cntr-b4 { + rockchip,pins = + <0 RK_PC7 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pwm1_bip_cntr_b5: rm-io23-pwm1-bip-cntr-b5 { + rockchip,pins = + <0 RK_PC7 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_pdm_clk1: rm-io23-pdm-clk1 { + rockchip,pins = + <0 RK_PC7 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_eth_rmii0_ppsclk: rm-io23-eth-rmii0-ppsclk { + rockchip,pins = + <0 RK_PC7 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_eth_rmii0_ppstrig: rm-io23-eth-rmii0-ppstrig { + rockchip,pins = + <0 RK_PC7 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_eth_rmii1_ppsclk: rm-io23-eth-rmii1-ppsclk { + rockchip,pins = + <0 RK_PC7 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io23_eth_rmii1_ppstrig: rm-io23-eth-rmii1-ppstrig { + rockchip,pins = + <0 RK_PC7 113 &pcfg_pull_none>; + }; + }; + + rm_io24 { + /omit-if-no-ref/ + rm_io24_uart1_tx: rm-io24-uart1-tx { + rockchip,pins = + <1 RK_PB1 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart1_rx: rm-io24-uart1-rx { + rockchip,pins = + <1 RK_PB1 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io24_uart2_tx: rm-io24-uart2-tx { + rockchip,pins = + <1 RK_PB1 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart2_rx: rm-io24-uart2-rx { + rockchip,pins = + <1 RK_PB1 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io24_uart3_tx: rm-io24-uart3-tx { + rockchip,pins = + <1 RK_PB1 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart3_rx: rm-io24-uart3-rx { + rockchip,pins = + <1 RK_PB1 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io24_uart3_ctsn: rm-io24-uart3-ctsn { + rockchip,pins = + <1 RK_PB1 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart3_rtsn: rm-io24-uart3-rtsn { + rockchip,pins = + <1 RK_PB1 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart4_tx: rm-io24-uart4-tx { + rockchip,pins = + <1 RK_PB1 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart4_rx: rm-io24-uart4-rx { + rockchip,pins = + <1 RK_PB1 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io24_uart4_ctsn: rm-io24-uart4-ctsn { + rockchip,pins = + <1 RK_PB1 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_uart4_rtsn: rm-io24-uart4-rtsn { + rockchip,pins = + <1 RK_PB1 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_mipite: rm-io24-mipite { + rockchip,pins = + <1 RK_PB1 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_clk_32k: rm-io24-clk-32k { + rockchip,pins = + <1 RK_PB1 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c0_scl: rm-io24-i2c0-scl { + rockchip,pins = + <1 RK_PB1 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c0_sda: rm-io24-i2c0-sda { + rockchip,pins = + <1 RK_PB1 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c1_scl: rm-io24-i2c1-scl { + rockchip,pins = + <1 RK_PB1 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c1_sda: rm-io24-i2c1-sda { + rockchip,pins = + <1 RK_PB1 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c2_scl: rm-io24-i2c2-scl { + rockchip,pins = + <1 RK_PB1 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_i2c2_sda: rm-io24-i2c2-sda { + rockchip,pins = + <1 RK_PB1 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_clk0: rm-io24-pdm-clk0 { + rockchip,pins = + <1 RK_PB1 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_sdi0: rm-io24-pdm-sdi0 { + rockchip,pins = + <1 RK_PB1 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_sdi1: rm-io24-pdm-sdi1 { + rockchip,pins = + <1 RK_PB1 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_sdi2: rm-io24-pdm-sdi2 { + rockchip,pins = + <1 RK_PB1 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_sdi3: rm-io24-pdm-sdi3 { + rockchip,pins = + <1 RK_PB1 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_can1_tx: rm-io24-can1-tx { + rockchip,pins = + <1 RK_PB1 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_can1_rx: rm-io24-can1-rx { + rockchip,pins = + <1 RK_PB1 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_can0_tx: rm-io24-can0-tx { + rockchip,pins = + <1 RK_PB1 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_can0_rx: rm-io24-can0-rx { + rockchip,pins = + <1 RK_PB1 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm0_ch0: rm-io24-pwm0-ch0 { + rockchip,pins = + <1 RK_PB1 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm0_ch1: rm-io24-pwm0-ch1 { + rockchip,pins = + <1 RK_PB1 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm0_ch2: rm-io24-pwm0-ch2 { + rockchip,pins = + <1 RK_PB1 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm0_ch3: rm-io24-pwm0-ch3 { + rockchip,pins = + <1 RK_PB1 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch0: rm-io24-pwm1-ch0 { + rockchip,pins = + <1 RK_PB1 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch1: rm-io24-pwm1-ch1 { + rockchip,pins = + <1 RK_PB1 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch2: rm-io24-pwm1-ch2 { + rockchip,pins = + <1 RK_PB1 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch3: rm-io24-pwm1-ch3 { + rockchip,pins = + <1 RK_PB1 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch4: rm-io24-pwm1-ch4 { + rockchip,pins = + <1 RK_PB1 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch5: rm-io24-pwm1-ch5 { + rockchip,pins = + <1 RK_PB1 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch6: rm-io24-pwm1-ch6 { + rockchip,pins = + <1 RK_PB1 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_ch7: rm-io24-pwm1-ch7 { + rockchip,pins = + <1 RK_PB1 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_drive: rm-io24-touch-key-drive { + rockchip,pins = + <1 RK_PB1 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in0: rm-io24-touch-key-in0 { + rockchip,pins = + <1 RK_PB1 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in1: rm-io24-touch-key-in1 { + rockchip,pins = + <1 RK_PB1 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in2: rm-io24-touch-key-in2 { + rockchip,pins = + <1 RK_PB1 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in3: rm-io24-touch-key-in3 { + rockchip,pins = + <1 RK_PB1 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in4: rm-io24-touch-key-in4 { + rockchip,pins = + <1 RK_PB1 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in5: rm-io24-touch-key-in5 { + rockchip,pins = + <1 RK_PB1 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in6: rm-io24-touch-key-in6 { + rockchip,pins = + <1 RK_PB1 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_touch_key_in7: rm-io24-touch-key-in7 { + rockchip,pins = + <1 RK_PB1 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_mclk: rm-io24-sai0-mclk { + rockchip,pins = + <1 RK_PB1 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sclk: rm-io24-sai0-sclk { + rockchip,pins = + <1 RK_PB1 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_lrck: rm-io24-sai0-lrck { + rockchip,pins = + <1 RK_PB1 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sdi0: rm-io24-sai0-sdi0 { + rockchip,pins = + <1 RK_PB1 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sdi1: rm-io24-sai0-sdi1 { + rockchip,pins = + <1 RK_PB1 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sdi2: rm-io24-sai0-sdi2 { + rockchip,pins = + <1 RK_PB1 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sdi3: rm-io24-sai0-sdi3 { + rockchip,pins = + <1 RK_PB1 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai0_sdo: rm-io24-sai0-sdo { + rockchip,pins = + <1 RK_PB1 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_mclk: rm-io24-sai1-mclk { + rockchip,pins = + <1 RK_PB1 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sclk: rm-io24-sai1-sclk { + rockchip,pins = + <1 RK_PB1 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_lrck: rm-io24-sai1-lrck { + rockchip,pins = + <1 RK_PB1 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sdi: rm-io24-sai1-sdi { + rockchip,pins = + <1 RK_PB1 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sdo0: rm-io24-sai1-sdo0 { + rockchip,pins = + <1 RK_PB1 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sdo1: rm-io24-sai1-sdo1 { + rockchip,pins = + <1 RK_PB1 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sdo2: rm-io24-sai1-sdo2 { + rockchip,pins = + <1 RK_PB1 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_sai1_sdo3: rm-io24-sai1-sdo3 { + rockchip,pins = + <1 RK_PB1 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi0_clk: rm-io24-spi0-clk { + rockchip,pins = + <1 RK_PB1 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi0_mosi: rm-io24-spi0-mosi { + rockchip,pins = + <1 RK_PB1 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi0_miso: rm-io24-spi0-miso { + rockchip,pins = + <1 RK_PB1 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi0_csn0: rm-io24-spi0-csn0 { + rockchip,pins = + <1 RK_PB1 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi0_csn1: rm-io24-spi0-csn1 { + rockchip,pins = + <1 RK_PB1 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi1_clk: rm-io24-spi1-clk { + rockchip,pins = + <1 RK_PB1 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi1_mosi: rm-io24-spi1-mosi { + rockchip,pins = + <1 RK_PB1 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi1_miso: rm-io24-spi1-miso { + rockchip,pins = + <1 RK_PB1 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi1_csn0: rm-io24-spi1-csn0 { + rockchip,pins = + <1 RK_PB1 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spi1_csn1: rm-io24-spi1-csn1 { + rockchip,pins = + <1 RK_PB1 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_wdt_tsadc_shut: rm-io24-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PB1 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pmu_sleep: rm-io24-pmu-sleep { + rockchip,pins = + <1 RK_PB1 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_core_power_off: rm-io24-core-power-off { + rockchip,pins = + <1 RK_PB1 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spdif_tx: rm-io24-spdif-tx { + rockchip,pins = + <1 RK_PB1 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_spdif_rx: rm-io24-spdif-rx { + rockchip,pins = + <1 RK_PB1 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a0: rm-io24-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PB1 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a1: rm-io24-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PB1 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a2: rm-io24-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PB1 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a3: rm-io24-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PB1 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a4: rm-io24-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PB1 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_a5: rm-io24-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PB1 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b0: rm-io24-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PB1 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b1: rm-io24-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PB1 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b2: rm-io24-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PB1 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b3: rm-io24-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PB1 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b4: rm-io24-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PB1 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pwm1_bip_cntr_b5: rm-io24-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PB1 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_pdm_clk1: rm-io24-pdm-clk1 { + rockchip,pins = + <1 RK_PB1 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_eth_rmii0_ppsclk: rm-io24-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PB1 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_eth_rmii0_ppstrig: rm-io24-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PB1 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_eth_rmii1_ppsclk: rm-io24-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PB1 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io24_eth_rmii1_ppstrig: rm-io24-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PB1 113 &pcfg_pull_none>; + }; + }; + + rm_io25 { + /omit-if-no-ref/ + rm_io25_uart1_tx: rm-io25-uart1-tx { + rockchip,pins = + <1 RK_PB2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart1_rx: rm-io25-uart1-rx { + rockchip,pins = + <1 RK_PB2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io25_uart2_tx: rm-io25-uart2-tx { + rockchip,pins = + <1 RK_PB2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart2_rx: rm-io25-uart2-rx { + rockchip,pins = + <1 RK_PB2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io25_uart3_tx: rm-io25-uart3-tx { + rockchip,pins = + <1 RK_PB2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart3_rx: rm-io25-uart3-rx { + rockchip,pins = + <1 RK_PB2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io25_uart3_ctsn: rm-io25-uart3-ctsn { + rockchip,pins = + <1 RK_PB2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart3_rtsn: rm-io25-uart3-rtsn { + rockchip,pins = + <1 RK_PB2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart4_tx: rm-io25-uart4-tx { + rockchip,pins = + <1 RK_PB2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart4_rx: rm-io25-uart4-rx { + rockchip,pins = + <1 RK_PB2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io25_uart4_ctsn: rm-io25-uart4-ctsn { + rockchip,pins = + <1 RK_PB2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_uart4_rtsn: rm-io25-uart4-rtsn { + rockchip,pins = + <1 RK_PB2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_mipite: rm-io25-mipite { + rockchip,pins = + <1 RK_PB2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_clk_32k: rm-io25-clk-32k { + rockchip,pins = + <1 RK_PB2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c0_scl: rm-io25-i2c0-scl { + rockchip,pins = + <1 RK_PB2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c0_sda: rm-io25-i2c0-sda { + rockchip,pins = + <1 RK_PB2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c1_scl: rm-io25-i2c1-scl { + rockchip,pins = + <1 RK_PB2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c1_sda: rm-io25-i2c1-sda { + rockchip,pins = + <1 RK_PB2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c2_scl: rm-io25-i2c2-scl { + rockchip,pins = + <1 RK_PB2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_i2c2_sda: rm-io25-i2c2-sda { + rockchip,pins = + <1 RK_PB2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_clk0: rm-io25-pdm-clk0 { + rockchip,pins = + <1 RK_PB2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_sdi0: rm-io25-pdm-sdi0 { + rockchip,pins = + <1 RK_PB2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_sdi1: rm-io25-pdm-sdi1 { + rockchip,pins = + <1 RK_PB2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_sdi2: rm-io25-pdm-sdi2 { + rockchip,pins = + <1 RK_PB2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_sdi3: rm-io25-pdm-sdi3 { + rockchip,pins = + <1 RK_PB2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_can1_tx: rm-io25-can1-tx { + rockchip,pins = + <1 RK_PB2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_can1_rx: rm-io25-can1-rx { + rockchip,pins = + <1 RK_PB2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_can0_tx: rm-io25-can0-tx { + rockchip,pins = + <1 RK_PB2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_can0_rx: rm-io25-can0-rx { + rockchip,pins = + <1 RK_PB2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm0_ch0: rm-io25-pwm0-ch0 { + rockchip,pins = + <1 RK_PB2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm0_ch1: rm-io25-pwm0-ch1 { + rockchip,pins = + <1 RK_PB2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm0_ch2: rm-io25-pwm0-ch2 { + rockchip,pins = + <1 RK_PB2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm0_ch3: rm-io25-pwm0-ch3 { + rockchip,pins = + <1 RK_PB2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch0: rm-io25-pwm1-ch0 { + rockchip,pins = + <1 RK_PB2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch1: rm-io25-pwm1-ch1 { + rockchip,pins = + <1 RK_PB2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch2: rm-io25-pwm1-ch2 { + rockchip,pins = + <1 RK_PB2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch3: rm-io25-pwm1-ch3 { + rockchip,pins = + <1 RK_PB2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch4: rm-io25-pwm1-ch4 { + rockchip,pins = + <1 RK_PB2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch5: rm-io25-pwm1-ch5 { + rockchip,pins = + <1 RK_PB2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch6: rm-io25-pwm1-ch6 { + rockchip,pins = + <1 RK_PB2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_ch7: rm-io25-pwm1-ch7 { + rockchip,pins = + <1 RK_PB2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_drive: rm-io25-touch-key-drive { + rockchip,pins = + <1 RK_PB2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in0: rm-io25-touch-key-in0 { + rockchip,pins = + <1 RK_PB2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in1: rm-io25-touch-key-in1 { + rockchip,pins = + <1 RK_PB2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in2: rm-io25-touch-key-in2 { + rockchip,pins = + <1 RK_PB2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in3: rm-io25-touch-key-in3 { + rockchip,pins = + <1 RK_PB2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in4: rm-io25-touch-key-in4 { + rockchip,pins = + <1 RK_PB2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in5: rm-io25-touch-key-in5 { + rockchip,pins = + <1 RK_PB2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in6: rm-io25-touch-key-in6 { + rockchip,pins = + <1 RK_PB2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_touch_key_in7: rm-io25-touch-key-in7 { + rockchip,pins = + <1 RK_PB2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_mclk: rm-io25-sai0-mclk { + rockchip,pins = + <1 RK_PB2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sclk: rm-io25-sai0-sclk { + rockchip,pins = + <1 RK_PB2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_lrck: rm-io25-sai0-lrck { + rockchip,pins = + <1 RK_PB2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sdi0: rm-io25-sai0-sdi0 { + rockchip,pins = + <1 RK_PB2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sdi1: rm-io25-sai0-sdi1 { + rockchip,pins = + <1 RK_PB2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sdi2: rm-io25-sai0-sdi2 { + rockchip,pins = + <1 RK_PB2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sdi3: rm-io25-sai0-sdi3 { + rockchip,pins = + <1 RK_PB2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai0_sdo: rm-io25-sai0-sdo { + rockchip,pins = + <1 RK_PB2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_mclk: rm-io25-sai1-mclk { + rockchip,pins = + <1 RK_PB2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sclk: rm-io25-sai1-sclk { + rockchip,pins = + <1 RK_PB2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_lrck: rm-io25-sai1-lrck { + rockchip,pins = + <1 RK_PB2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sdi: rm-io25-sai1-sdi { + rockchip,pins = + <1 RK_PB2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sdo0: rm-io25-sai1-sdo0 { + rockchip,pins = + <1 RK_PB2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sdo1: rm-io25-sai1-sdo1 { + rockchip,pins = + <1 RK_PB2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sdo2: rm-io25-sai1-sdo2 { + rockchip,pins = + <1 RK_PB2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_sai1_sdo3: rm-io25-sai1-sdo3 { + rockchip,pins = + <1 RK_PB2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi0_clk: rm-io25-spi0-clk { + rockchip,pins = + <1 RK_PB2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi0_mosi: rm-io25-spi0-mosi { + rockchip,pins = + <1 RK_PB2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi0_miso: rm-io25-spi0-miso { + rockchip,pins = + <1 RK_PB2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi0_csn0: rm-io25-spi0-csn0 { + rockchip,pins = + <1 RK_PB2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi0_csn1: rm-io25-spi0-csn1 { + rockchip,pins = + <1 RK_PB2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi1_clk: rm-io25-spi1-clk { + rockchip,pins = + <1 RK_PB2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi1_mosi: rm-io25-spi1-mosi { + rockchip,pins = + <1 RK_PB2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi1_miso: rm-io25-spi1-miso { + rockchip,pins = + <1 RK_PB2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi1_csn0: rm-io25-spi1-csn0 { + rockchip,pins = + <1 RK_PB2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spi1_csn1: rm-io25-spi1-csn1 { + rockchip,pins = + <1 RK_PB2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_wdt_tsadc_shut: rm-io25-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PB2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pmu_sleep: rm-io25-pmu-sleep { + rockchip,pins = + <1 RK_PB2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_core_power_off: rm-io25-core-power-off { + rockchip,pins = + <1 RK_PB2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spdif_tx: rm-io25-spdif-tx { + rockchip,pins = + <1 RK_PB2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_spdif_rx: rm-io25-spdif-rx { + rockchip,pins = + <1 RK_PB2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a0: rm-io25-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PB2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a1: rm-io25-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PB2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a2: rm-io25-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PB2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a3: rm-io25-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PB2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a4: rm-io25-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PB2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_a5: rm-io25-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PB2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b0: rm-io25-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PB2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b1: rm-io25-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PB2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b2: rm-io25-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PB2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b3: rm-io25-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PB2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b4: rm-io25-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PB2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pwm1_bip_cntr_b5: rm-io25-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PB2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_pdm_clk1: rm-io25-pdm-clk1 { + rockchip,pins = + <1 RK_PB2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_eth_rmii0_ppsclk: rm-io25-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PB2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_eth_rmii0_ppstrig: rm-io25-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PB2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_eth_rmii1_ppsclk: rm-io25-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PB2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io25_eth_rmii1_ppstrig: rm-io25-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PB2 113 &pcfg_pull_none>; + }; + }; + + rm_io26 { + /omit-if-no-ref/ + rm_io26_uart1_tx: rm-io26-uart1-tx { + rockchip,pins = + <1 RK_PB3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart1_rx: rm-io26-uart1-rx { + rockchip,pins = + <1 RK_PB3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io26_uart2_tx: rm-io26-uart2-tx { + rockchip,pins = + <1 RK_PB3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart2_rx: rm-io26-uart2-rx { + rockchip,pins = + <1 RK_PB3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io26_uart3_tx: rm-io26-uart3-tx { + rockchip,pins = + <1 RK_PB3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart3_rx: rm-io26-uart3-rx { + rockchip,pins = + <1 RK_PB3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io26_uart3_ctsn: rm-io26-uart3-ctsn { + rockchip,pins = + <1 RK_PB3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart3_rtsn: rm-io26-uart3-rtsn { + rockchip,pins = + <1 RK_PB3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart4_tx: rm-io26-uart4-tx { + rockchip,pins = + <1 RK_PB3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart4_rx: rm-io26-uart4-rx { + rockchip,pins = + <1 RK_PB3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io26_uart4_ctsn: rm-io26-uart4-ctsn { + rockchip,pins = + <1 RK_PB3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_uart4_rtsn: rm-io26-uart4-rtsn { + rockchip,pins = + <1 RK_PB3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_mipite: rm-io26-mipite { + rockchip,pins = + <1 RK_PB3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_clk_32k: rm-io26-clk-32k { + rockchip,pins = + <1 RK_PB3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c0_scl: rm-io26-i2c0-scl { + rockchip,pins = + <1 RK_PB3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c0_sda: rm-io26-i2c0-sda { + rockchip,pins = + <1 RK_PB3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c1_scl: rm-io26-i2c1-scl { + rockchip,pins = + <1 RK_PB3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c1_sda: rm-io26-i2c1-sda { + rockchip,pins = + <1 RK_PB3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c2_scl: rm-io26-i2c2-scl { + rockchip,pins = + <1 RK_PB3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_i2c2_sda: rm-io26-i2c2-sda { + rockchip,pins = + <1 RK_PB3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_clk0: rm-io26-pdm-clk0 { + rockchip,pins = + <1 RK_PB3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_sdi0: rm-io26-pdm-sdi0 { + rockchip,pins = + <1 RK_PB3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_sdi1: rm-io26-pdm-sdi1 { + rockchip,pins = + <1 RK_PB3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_sdi2: rm-io26-pdm-sdi2 { + rockchip,pins = + <1 RK_PB3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_sdi3: rm-io26-pdm-sdi3 { + rockchip,pins = + <1 RK_PB3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_can1_tx: rm-io26-can1-tx { + rockchip,pins = + <1 RK_PB3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_can1_rx: rm-io26-can1-rx { + rockchip,pins = + <1 RK_PB3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_can0_tx: rm-io26-can0-tx { + rockchip,pins = + <1 RK_PB3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_can0_rx: rm-io26-can0-rx { + rockchip,pins = + <1 RK_PB3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm0_ch0: rm-io26-pwm0-ch0 { + rockchip,pins = + <1 RK_PB3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm0_ch1: rm-io26-pwm0-ch1 { + rockchip,pins = + <1 RK_PB3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm0_ch2: rm-io26-pwm0-ch2 { + rockchip,pins = + <1 RK_PB3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm0_ch3: rm-io26-pwm0-ch3 { + rockchip,pins = + <1 RK_PB3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch0: rm-io26-pwm1-ch0 { + rockchip,pins = + <1 RK_PB3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch1: rm-io26-pwm1-ch1 { + rockchip,pins = + <1 RK_PB3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch2: rm-io26-pwm1-ch2 { + rockchip,pins = + <1 RK_PB3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch3: rm-io26-pwm1-ch3 { + rockchip,pins = + <1 RK_PB3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch4: rm-io26-pwm1-ch4 { + rockchip,pins = + <1 RK_PB3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch5: rm-io26-pwm1-ch5 { + rockchip,pins = + <1 RK_PB3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch6: rm-io26-pwm1-ch6 { + rockchip,pins = + <1 RK_PB3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_ch7: rm-io26-pwm1-ch7 { + rockchip,pins = + <1 RK_PB3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_drive: rm-io26-touch-key-drive { + rockchip,pins = + <1 RK_PB3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in0: rm-io26-touch-key-in0 { + rockchip,pins = + <1 RK_PB3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in1: rm-io26-touch-key-in1 { + rockchip,pins = + <1 RK_PB3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in2: rm-io26-touch-key-in2 { + rockchip,pins = + <1 RK_PB3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in3: rm-io26-touch-key-in3 { + rockchip,pins = + <1 RK_PB3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in4: rm-io26-touch-key-in4 { + rockchip,pins = + <1 RK_PB3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in5: rm-io26-touch-key-in5 { + rockchip,pins = + <1 RK_PB3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in6: rm-io26-touch-key-in6 { + rockchip,pins = + <1 RK_PB3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_touch_key_in7: rm-io26-touch-key-in7 { + rockchip,pins = + <1 RK_PB3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_mclk: rm-io26-sai0-mclk { + rockchip,pins = + <1 RK_PB3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sclk: rm-io26-sai0-sclk { + rockchip,pins = + <1 RK_PB3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_lrck: rm-io26-sai0-lrck { + rockchip,pins = + <1 RK_PB3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sdi0: rm-io26-sai0-sdi0 { + rockchip,pins = + <1 RK_PB3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sdi1: rm-io26-sai0-sdi1 { + rockchip,pins = + <1 RK_PB3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sdi2: rm-io26-sai0-sdi2 { + rockchip,pins = + <1 RK_PB3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sdi3: rm-io26-sai0-sdi3 { + rockchip,pins = + <1 RK_PB3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai0_sdo: rm-io26-sai0-sdo { + rockchip,pins = + <1 RK_PB3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_mclk: rm-io26-sai1-mclk { + rockchip,pins = + <1 RK_PB3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sclk: rm-io26-sai1-sclk { + rockchip,pins = + <1 RK_PB3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_lrck: rm-io26-sai1-lrck { + rockchip,pins = + <1 RK_PB3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sdi: rm-io26-sai1-sdi { + rockchip,pins = + <1 RK_PB3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sdo0: rm-io26-sai1-sdo0 { + rockchip,pins = + <1 RK_PB3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sdo1: rm-io26-sai1-sdo1 { + rockchip,pins = + <1 RK_PB3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sdo2: rm-io26-sai1-sdo2 { + rockchip,pins = + <1 RK_PB3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_sai1_sdo3: rm-io26-sai1-sdo3 { + rockchip,pins = + <1 RK_PB3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi0_clk: rm-io26-spi0-clk { + rockchip,pins = + <1 RK_PB3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi0_mosi: rm-io26-spi0-mosi { + rockchip,pins = + <1 RK_PB3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi0_miso: rm-io26-spi0-miso { + rockchip,pins = + <1 RK_PB3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi0_csn0: rm-io26-spi0-csn0 { + rockchip,pins = + <1 RK_PB3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi0_csn1: rm-io26-spi0-csn1 { + rockchip,pins = + <1 RK_PB3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi1_clk: rm-io26-spi1-clk { + rockchip,pins = + <1 RK_PB3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi1_mosi: rm-io26-spi1-mosi { + rockchip,pins = + <1 RK_PB3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi1_miso: rm-io26-spi1-miso { + rockchip,pins = + <1 RK_PB3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi1_csn0: rm-io26-spi1-csn0 { + rockchip,pins = + <1 RK_PB3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spi1_csn1: rm-io26-spi1-csn1 { + rockchip,pins = + <1 RK_PB3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_wdt_tsadc_shut: rm-io26-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PB3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pmu_sleep: rm-io26-pmu-sleep { + rockchip,pins = + <1 RK_PB3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_core_power_off: rm-io26-core-power-off { + rockchip,pins = + <1 RK_PB3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spdif_tx: rm-io26-spdif-tx { + rockchip,pins = + <1 RK_PB3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_spdif_rx: rm-io26-spdif-rx { + rockchip,pins = + <1 RK_PB3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a0: rm-io26-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PB3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a1: rm-io26-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PB3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a2: rm-io26-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PB3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a3: rm-io26-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PB3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a4: rm-io26-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PB3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_a5: rm-io26-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PB3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b0: rm-io26-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PB3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b1: rm-io26-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PB3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b2: rm-io26-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PB3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b3: rm-io26-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PB3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b4: rm-io26-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PB3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pwm1_bip_cntr_b5: rm-io26-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PB3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_pdm_clk1: rm-io26-pdm-clk1 { + rockchip,pins = + <1 RK_PB3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_eth_rmii0_ppsclk: rm-io26-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PB3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_eth_rmii0_ppstrig: rm-io26-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PB3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_eth_rmii1_ppsclk: rm-io26-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PB3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io26_eth_rmii1_ppstrig: rm-io26-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PB3 113 &pcfg_pull_none>; + }; + }; + + rm_io27 { + /omit-if-no-ref/ + rm_io27_uart1_tx: rm-io27-uart1-tx { + rockchip,pins = + <1 RK_PC2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart1_rx: rm-io27-uart1-rx { + rockchip,pins = + <1 RK_PC2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io27_uart2_tx: rm-io27-uart2-tx { + rockchip,pins = + <1 RK_PC2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart2_rx: rm-io27-uart2-rx { + rockchip,pins = + <1 RK_PC2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io27_uart3_tx: rm-io27-uart3-tx { + rockchip,pins = + <1 RK_PC2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart3_rx: rm-io27-uart3-rx { + rockchip,pins = + <1 RK_PC2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io27_uart3_ctsn: rm-io27-uart3-ctsn { + rockchip,pins = + <1 RK_PC2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart3_rtsn: rm-io27-uart3-rtsn { + rockchip,pins = + <1 RK_PC2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart4_tx: rm-io27-uart4-tx { + rockchip,pins = + <1 RK_PC2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart4_rx: rm-io27-uart4-rx { + rockchip,pins = + <1 RK_PC2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io27_uart4_ctsn: rm-io27-uart4-ctsn { + rockchip,pins = + <1 RK_PC2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_uart4_rtsn: rm-io27-uart4-rtsn { + rockchip,pins = + <1 RK_PC2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_mipite: rm-io27-mipite { + rockchip,pins = + <1 RK_PC2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_clk_32k: rm-io27-clk-32k { + rockchip,pins = + <1 RK_PC2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c0_scl: rm-io27-i2c0-scl { + rockchip,pins = + <1 RK_PC2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c0_sda: rm-io27-i2c0-sda { + rockchip,pins = + <1 RK_PC2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c1_scl: rm-io27-i2c1-scl { + rockchip,pins = + <1 RK_PC2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c1_sda: rm-io27-i2c1-sda { + rockchip,pins = + <1 RK_PC2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c2_scl: rm-io27-i2c2-scl { + rockchip,pins = + <1 RK_PC2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_i2c2_sda: rm-io27-i2c2-sda { + rockchip,pins = + <1 RK_PC2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_clk0: rm-io27-pdm-clk0 { + rockchip,pins = + <1 RK_PC2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_sdi0: rm-io27-pdm-sdi0 { + rockchip,pins = + <1 RK_PC2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_sdi1: rm-io27-pdm-sdi1 { + rockchip,pins = + <1 RK_PC2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_sdi2: rm-io27-pdm-sdi2 { + rockchip,pins = + <1 RK_PC2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_sdi3: rm-io27-pdm-sdi3 { + rockchip,pins = + <1 RK_PC2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_can1_tx: rm-io27-can1-tx { + rockchip,pins = + <1 RK_PC2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_can1_rx: rm-io27-can1-rx { + rockchip,pins = + <1 RK_PC2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_can0_tx: rm-io27-can0-tx { + rockchip,pins = + <1 RK_PC2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_can0_rx: rm-io27-can0-rx { + rockchip,pins = + <1 RK_PC2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm0_ch0: rm-io27-pwm0-ch0 { + rockchip,pins = + <1 RK_PC2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm0_ch1: rm-io27-pwm0-ch1 { + rockchip,pins = + <1 RK_PC2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm0_ch2: rm-io27-pwm0-ch2 { + rockchip,pins = + <1 RK_PC2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm0_ch3: rm-io27-pwm0-ch3 { + rockchip,pins = + <1 RK_PC2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch0: rm-io27-pwm1-ch0 { + rockchip,pins = + <1 RK_PC2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch1: rm-io27-pwm1-ch1 { + rockchip,pins = + <1 RK_PC2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch2: rm-io27-pwm1-ch2 { + rockchip,pins = + <1 RK_PC2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch3: rm-io27-pwm1-ch3 { + rockchip,pins = + <1 RK_PC2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch4: rm-io27-pwm1-ch4 { + rockchip,pins = + <1 RK_PC2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch5: rm-io27-pwm1-ch5 { + rockchip,pins = + <1 RK_PC2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch6: rm-io27-pwm1-ch6 { + rockchip,pins = + <1 RK_PC2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_ch7: rm-io27-pwm1-ch7 { + rockchip,pins = + <1 RK_PC2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_drive: rm-io27-touch-key-drive { + rockchip,pins = + <1 RK_PC2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in0: rm-io27-touch-key-in0 { + rockchip,pins = + <1 RK_PC2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in1: rm-io27-touch-key-in1 { + rockchip,pins = + <1 RK_PC2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in2: rm-io27-touch-key-in2 { + rockchip,pins = + <1 RK_PC2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in3: rm-io27-touch-key-in3 { + rockchip,pins = + <1 RK_PC2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in4: rm-io27-touch-key-in4 { + rockchip,pins = + <1 RK_PC2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in5: rm-io27-touch-key-in5 { + rockchip,pins = + <1 RK_PC2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in6: rm-io27-touch-key-in6 { + rockchip,pins = + <1 RK_PC2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_touch_key_in7: rm-io27-touch-key-in7 { + rockchip,pins = + <1 RK_PC2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_mclk: rm-io27-sai0-mclk { + rockchip,pins = + <1 RK_PC2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sclk: rm-io27-sai0-sclk { + rockchip,pins = + <1 RK_PC2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_lrck: rm-io27-sai0-lrck { + rockchip,pins = + <1 RK_PC2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sdi0: rm-io27-sai0-sdi0 { + rockchip,pins = + <1 RK_PC2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sdi1: rm-io27-sai0-sdi1 { + rockchip,pins = + <1 RK_PC2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sdi2: rm-io27-sai0-sdi2 { + rockchip,pins = + <1 RK_PC2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sdi3: rm-io27-sai0-sdi3 { + rockchip,pins = + <1 RK_PC2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai0_sdo: rm-io27-sai0-sdo { + rockchip,pins = + <1 RK_PC2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_mclk: rm-io27-sai1-mclk { + rockchip,pins = + <1 RK_PC2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sclk: rm-io27-sai1-sclk { + rockchip,pins = + <1 RK_PC2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_lrck: rm-io27-sai1-lrck { + rockchip,pins = + <1 RK_PC2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sdi: rm-io27-sai1-sdi { + rockchip,pins = + <1 RK_PC2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sdo0: rm-io27-sai1-sdo0 { + rockchip,pins = + <1 RK_PC2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sdo1: rm-io27-sai1-sdo1 { + rockchip,pins = + <1 RK_PC2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sdo2: rm-io27-sai1-sdo2 { + rockchip,pins = + <1 RK_PC2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_sai1_sdo3: rm-io27-sai1-sdo3 { + rockchip,pins = + <1 RK_PC2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi0_clk: rm-io27-spi0-clk { + rockchip,pins = + <1 RK_PC2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi0_mosi: rm-io27-spi0-mosi { + rockchip,pins = + <1 RK_PC2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi0_miso: rm-io27-spi0-miso { + rockchip,pins = + <1 RK_PC2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi0_csn0: rm-io27-spi0-csn0 { + rockchip,pins = + <1 RK_PC2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi0_csn1: rm-io27-spi0-csn1 { + rockchip,pins = + <1 RK_PC2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi1_clk: rm-io27-spi1-clk { + rockchip,pins = + <1 RK_PC2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi1_mosi: rm-io27-spi1-mosi { + rockchip,pins = + <1 RK_PC2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi1_miso: rm-io27-spi1-miso { + rockchip,pins = + <1 RK_PC2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi1_csn0: rm-io27-spi1-csn0 { + rockchip,pins = + <1 RK_PC2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spi1_csn1: rm-io27-spi1-csn1 { + rockchip,pins = + <1 RK_PC2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_wdt_tsadc_shut: rm-io27-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PC2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pmu_sleep: rm-io27-pmu-sleep { + rockchip,pins = + <1 RK_PC2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_core_power_off: rm-io27-core-power-off { + rockchip,pins = + <1 RK_PC2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spdif_tx: rm-io27-spdif-tx { + rockchip,pins = + <1 RK_PC2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_spdif_rx: rm-io27-spdif-rx { + rockchip,pins = + <1 RK_PC2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a0: rm-io27-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PC2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a1: rm-io27-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PC2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a2: rm-io27-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PC2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a3: rm-io27-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PC2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a4: rm-io27-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PC2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_a5: rm-io27-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PC2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b0: rm-io27-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PC2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b1: rm-io27-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PC2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b2: rm-io27-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PC2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b3: rm-io27-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PC2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b4: rm-io27-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PC2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pwm1_bip_cntr_b5: rm-io27-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PC2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_pdm_clk1: rm-io27-pdm-clk1 { + rockchip,pins = + <1 RK_PC2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_eth_rmii0_ppsclk: rm-io27-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PC2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_eth_rmii0_ppstrig: rm-io27-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PC2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_eth_rmii1_ppsclk: rm-io27-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PC2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io27_eth_rmii1_ppstrig: rm-io27-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PC2 113 &pcfg_pull_none>; + }; + }; + + rm_io28 { + /omit-if-no-ref/ + rm_io28_uart1_tx: rm-io28-uart1-tx { + rockchip,pins = + <1 RK_PC3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart1_rx: rm-io28-uart1-rx { + rockchip,pins = + <1 RK_PC3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io28_uart2_tx: rm-io28-uart2-tx { + rockchip,pins = + <1 RK_PC3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart2_rx: rm-io28-uart2-rx { + rockchip,pins = + <1 RK_PC3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io28_uart3_tx: rm-io28-uart3-tx { + rockchip,pins = + <1 RK_PC3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart3_rx: rm-io28-uart3-rx { + rockchip,pins = + <1 RK_PC3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io28_uart3_ctsn: rm-io28-uart3-ctsn { + rockchip,pins = + <1 RK_PC3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart3_rtsn: rm-io28-uart3-rtsn { + rockchip,pins = + <1 RK_PC3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart4_tx: rm-io28-uart4-tx { + rockchip,pins = + <1 RK_PC3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart4_rx: rm-io28-uart4-rx { + rockchip,pins = + <1 RK_PC3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io28_uart4_ctsn: rm-io28-uart4-ctsn { + rockchip,pins = + <1 RK_PC3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_uart4_rtsn: rm-io28-uart4-rtsn { + rockchip,pins = + <1 RK_PC3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_mipite: rm-io28-mipite { + rockchip,pins = + <1 RK_PC3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_clk_32k: rm-io28-clk-32k { + rockchip,pins = + <1 RK_PC3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c0_scl: rm-io28-i2c0-scl { + rockchip,pins = + <1 RK_PC3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c0_sda: rm-io28-i2c0-sda { + rockchip,pins = + <1 RK_PC3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c1_scl: rm-io28-i2c1-scl { + rockchip,pins = + <1 RK_PC3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c1_sda: rm-io28-i2c1-sda { + rockchip,pins = + <1 RK_PC3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c2_scl: rm-io28-i2c2-scl { + rockchip,pins = + <1 RK_PC3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_i2c2_sda: rm-io28-i2c2-sda { + rockchip,pins = + <1 RK_PC3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_clk0: rm-io28-pdm-clk0 { + rockchip,pins = + <1 RK_PC3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_sdi0: rm-io28-pdm-sdi0 { + rockchip,pins = + <1 RK_PC3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_sdi1: rm-io28-pdm-sdi1 { + rockchip,pins = + <1 RK_PC3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_sdi2: rm-io28-pdm-sdi2 { + rockchip,pins = + <1 RK_PC3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_sdi3: rm-io28-pdm-sdi3 { + rockchip,pins = + <1 RK_PC3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_can1_tx: rm-io28-can1-tx { + rockchip,pins = + <1 RK_PC3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_can1_rx: rm-io28-can1-rx { + rockchip,pins = + <1 RK_PC3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_can0_tx: rm-io28-can0-tx { + rockchip,pins = + <1 RK_PC3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_can0_rx: rm-io28-can0-rx { + rockchip,pins = + <1 RK_PC3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm0_ch0: rm-io28-pwm0-ch0 { + rockchip,pins = + <1 RK_PC3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm0_ch1: rm-io28-pwm0-ch1 { + rockchip,pins = + <1 RK_PC3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm0_ch2: rm-io28-pwm0-ch2 { + rockchip,pins = + <1 RK_PC3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm0_ch3: rm-io28-pwm0-ch3 { + rockchip,pins = + <1 RK_PC3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch0: rm-io28-pwm1-ch0 { + rockchip,pins = + <1 RK_PC3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch1: rm-io28-pwm1-ch1 { + rockchip,pins = + <1 RK_PC3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch2: rm-io28-pwm1-ch2 { + rockchip,pins = + <1 RK_PC3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch3: rm-io28-pwm1-ch3 { + rockchip,pins = + <1 RK_PC3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch4: rm-io28-pwm1-ch4 { + rockchip,pins = + <1 RK_PC3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch5: rm-io28-pwm1-ch5 { + rockchip,pins = + <1 RK_PC3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch6: rm-io28-pwm1-ch6 { + rockchip,pins = + <1 RK_PC3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_ch7: rm-io28-pwm1-ch7 { + rockchip,pins = + <1 RK_PC3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_drive: rm-io28-touch-key-drive { + rockchip,pins = + <1 RK_PC3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in0: rm-io28-touch-key-in0 { + rockchip,pins = + <1 RK_PC3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in1: rm-io28-touch-key-in1 { + rockchip,pins = + <1 RK_PC3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in2: rm-io28-touch-key-in2 { + rockchip,pins = + <1 RK_PC3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in3: rm-io28-touch-key-in3 { + rockchip,pins = + <1 RK_PC3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in4: rm-io28-touch-key-in4 { + rockchip,pins = + <1 RK_PC3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in5: rm-io28-touch-key-in5 { + rockchip,pins = + <1 RK_PC3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in6: rm-io28-touch-key-in6 { + rockchip,pins = + <1 RK_PC3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_touch_key_in7: rm-io28-touch-key-in7 { + rockchip,pins = + <1 RK_PC3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_mclk: rm-io28-sai0-mclk { + rockchip,pins = + <1 RK_PC3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sclk: rm-io28-sai0-sclk { + rockchip,pins = + <1 RK_PC3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_lrck: rm-io28-sai0-lrck { + rockchip,pins = + <1 RK_PC3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sdi0: rm-io28-sai0-sdi0 { + rockchip,pins = + <1 RK_PC3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sdi1: rm-io28-sai0-sdi1 { + rockchip,pins = + <1 RK_PC3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sdi2: rm-io28-sai0-sdi2 { + rockchip,pins = + <1 RK_PC3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sdi3: rm-io28-sai0-sdi3 { + rockchip,pins = + <1 RK_PC3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai0_sdo: rm-io28-sai0-sdo { + rockchip,pins = + <1 RK_PC3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_mclk: rm-io28-sai1-mclk { + rockchip,pins = + <1 RK_PC3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sclk: rm-io28-sai1-sclk { + rockchip,pins = + <1 RK_PC3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_lrck: rm-io28-sai1-lrck { + rockchip,pins = + <1 RK_PC3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sdi: rm-io28-sai1-sdi { + rockchip,pins = + <1 RK_PC3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sdo0: rm-io28-sai1-sdo0 { + rockchip,pins = + <1 RK_PC3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sdo1: rm-io28-sai1-sdo1 { + rockchip,pins = + <1 RK_PC3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sdo2: rm-io28-sai1-sdo2 { + rockchip,pins = + <1 RK_PC3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_sai1_sdo3: rm-io28-sai1-sdo3 { + rockchip,pins = + <1 RK_PC3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi0_clk: rm-io28-spi0-clk { + rockchip,pins = + <1 RK_PC3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi0_mosi: rm-io28-spi0-mosi { + rockchip,pins = + <1 RK_PC3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi0_miso: rm-io28-spi0-miso { + rockchip,pins = + <1 RK_PC3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi0_csn0: rm-io28-spi0-csn0 { + rockchip,pins = + <1 RK_PC3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi0_csn1: rm-io28-spi0-csn1 { + rockchip,pins = + <1 RK_PC3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi1_clk: rm-io28-spi1-clk { + rockchip,pins = + <1 RK_PC3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi1_mosi: rm-io28-spi1-mosi { + rockchip,pins = + <1 RK_PC3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi1_miso: rm-io28-spi1-miso { + rockchip,pins = + <1 RK_PC3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi1_csn0: rm-io28-spi1-csn0 { + rockchip,pins = + <1 RK_PC3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spi1_csn1: rm-io28-spi1-csn1 { + rockchip,pins = + <1 RK_PC3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_wdt_tsadc_shut: rm-io28-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PC3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pmu_sleep: rm-io28-pmu-sleep { + rockchip,pins = + <1 RK_PC3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_core_power_off: rm-io28-core-power-off { + rockchip,pins = + <1 RK_PC3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spdif_tx: rm-io28-spdif-tx { + rockchip,pins = + <1 RK_PC3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_spdif_rx: rm-io28-spdif-rx { + rockchip,pins = + <1 RK_PC3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a0: rm-io28-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PC3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a1: rm-io28-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PC3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a2: rm-io28-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PC3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a3: rm-io28-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PC3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a4: rm-io28-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PC3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_a5: rm-io28-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PC3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b0: rm-io28-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PC3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b1: rm-io28-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PC3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b2: rm-io28-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PC3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b3: rm-io28-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PC3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b4: rm-io28-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PC3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pwm1_bip_cntr_b5: rm-io28-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PC3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_pdm_clk1: rm-io28-pdm-clk1 { + rockchip,pins = + <1 RK_PC3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_eth_rmii0_ppsclk: rm-io28-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PC3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_eth_rmii0_ppstrig: rm-io28-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PC3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_eth_rmii1_ppsclk: rm-io28-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PC3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io28_eth_rmii1_ppstrig: rm-io28-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PC3 113 &pcfg_pull_none>; + }; + }; + + rm_io29 { + /omit-if-no-ref/ + rm_io29_uart1_tx: rm-io29-uart1-tx { + rockchip,pins = + <1 RK_PD1 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart1_rx: rm-io29-uart1-rx { + rockchip,pins = + <1 RK_PD1 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io29_uart2_tx: rm-io29-uart2-tx { + rockchip,pins = + <1 RK_PD1 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart2_rx: rm-io29-uart2-rx { + rockchip,pins = + <1 RK_PD1 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io29_uart3_tx: rm-io29-uart3-tx { + rockchip,pins = + <1 RK_PD1 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart3_rx: rm-io29-uart3-rx { + rockchip,pins = + <1 RK_PD1 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io29_uart3_ctsn: rm-io29-uart3-ctsn { + rockchip,pins = + <1 RK_PD1 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart3_rtsn: rm-io29-uart3-rtsn { + rockchip,pins = + <1 RK_PD1 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart4_tx: rm-io29-uart4-tx { + rockchip,pins = + <1 RK_PD1 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart4_rx: rm-io29-uart4-rx { + rockchip,pins = + <1 RK_PD1 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io29_uart4_ctsn: rm-io29-uart4-ctsn { + rockchip,pins = + <1 RK_PD1 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_uart4_rtsn: rm-io29-uart4-rtsn { + rockchip,pins = + <1 RK_PD1 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_mipite: rm-io29-mipite { + rockchip,pins = + <1 RK_PD1 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_clk_32k: rm-io29-clk-32k { + rockchip,pins = + <1 RK_PD1 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c0_scl: rm-io29-i2c0-scl { + rockchip,pins = + <1 RK_PD1 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c0_sda: rm-io29-i2c0-sda { + rockchip,pins = + <1 RK_PD1 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c1_scl: rm-io29-i2c1-scl { + rockchip,pins = + <1 RK_PD1 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c1_sda: rm-io29-i2c1-sda { + rockchip,pins = + <1 RK_PD1 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c2_scl: rm-io29-i2c2-scl { + rockchip,pins = + <1 RK_PD1 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_i2c2_sda: rm-io29-i2c2-sda { + rockchip,pins = + <1 RK_PD1 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_clk0: rm-io29-pdm-clk0 { + rockchip,pins = + <1 RK_PD1 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_sdi0: rm-io29-pdm-sdi0 { + rockchip,pins = + <1 RK_PD1 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_sdi1: rm-io29-pdm-sdi1 { + rockchip,pins = + <1 RK_PD1 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_sdi2: rm-io29-pdm-sdi2 { + rockchip,pins = + <1 RK_PD1 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_sdi3: rm-io29-pdm-sdi3 { + rockchip,pins = + <1 RK_PD1 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_can1_tx: rm-io29-can1-tx { + rockchip,pins = + <1 RK_PD1 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_can1_rx: rm-io29-can1-rx { + rockchip,pins = + <1 RK_PD1 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_can0_tx: rm-io29-can0-tx { + rockchip,pins = + <1 RK_PD1 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_can0_rx: rm-io29-can0-rx { + rockchip,pins = + <1 RK_PD1 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm0_ch0: rm-io29-pwm0-ch0 { + rockchip,pins = + <1 RK_PD1 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm0_ch1: rm-io29-pwm0-ch1 { + rockchip,pins = + <1 RK_PD1 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm0_ch2: rm-io29-pwm0-ch2 { + rockchip,pins = + <1 RK_PD1 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm0_ch3: rm-io29-pwm0-ch3 { + rockchip,pins = + <1 RK_PD1 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch0: rm-io29-pwm1-ch0 { + rockchip,pins = + <1 RK_PD1 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch1: rm-io29-pwm1-ch1 { + rockchip,pins = + <1 RK_PD1 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch2: rm-io29-pwm1-ch2 { + rockchip,pins = + <1 RK_PD1 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch3: rm-io29-pwm1-ch3 { + rockchip,pins = + <1 RK_PD1 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch4: rm-io29-pwm1-ch4 { + rockchip,pins = + <1 RK_PD1 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch5: rm-io29-pwm1-ch5 { + rockchip,pins = + <1 RK_PD1 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch6: rm-io29-pwm1-ch6 { + rockchip,pins = + <1 RK_PD1 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_ch7: rm-io29-pwm1-ch7 { + rockchip,pins = + <1 RK_PD1 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_drive: rm-io29-touch-key-drive { + rockchip,pins = + <1 RK_PD1 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in0: rm-io29-touch-key-in0 { + rockchip,pins = + <1 RK_PD1 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in1: rm-io29-touch-key-in1 { + rockchip,pins = + <1 RK_PD1 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in2: rm-io29-touch-key-in2 { + rockchip,pins = + <1 RK_PD1 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in3: rm-io29-touch-key-in3 { + rockchip,pins = + <1 RK_PD1 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in4: rm-io29-touch-key-in4 { + rockchip,pins = + <1 RK_PD1 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in5: rm-io29-touch-key-in5 { + rockchip,pins = + <1 RK_PD1 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in6: rm-io29-touch-key-in6 { + rockchip,pins = + <1 RK_PD1 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_touch_key_in7: rm-io29-touch-key-in7 { + rockchip,pins = + <1 RK_PD1 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_mclk: rm-io29-sai0-mclk { + rockchip,pins = + <1 RK_PD1 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sclk: rm-io29-sai0-sclk { + rockchip,pins = + <1 RK_PD1 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_lrck: rm-io29-sai0-lrck { + rockchip,pins = + <1 RK_PD1 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sdi0: rm-io29-sai0-sdi0 { + rockchip,pins = + <1 RK_PD1 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sdi1: rm-io29-sai0-sdi1 { + rockchip,pins = + <1 RK_PD1 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sdi2: rm-io29-sai0-sdi2 { + rockchip,pins = + <1 RK_PD1 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sdi3: rm-io29-sai0-sdi3 { + rockchip,pins = + <1 RK_PD1 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai0_sdo: rm-io29-sai0-sdo { + rockchip,pins = + <1 RK_PD1 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_mclk: rm-io29-sai1-mclk { + rockchip,pins = + <1 RK_PD1 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sclk: rm-io29-sai1-sclk { + rockchip,pins = + <1 RK_PD1 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_lrck: rm-io29-sai1-lrck { + rockchip,pins = + <1 RK_PD1 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sdi: rm-io29-sai1-sdi { + rockchip,pins = + <1 RK_PD1 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sdo0: rm-io29-sai1-sdo0 { + rockchip,pins = + <1 RK_PD1 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sdo1: rm-io29-sai1-sdo1 { + rockchip,pins = + <1 RK_PD1 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sdo2: rm-io29-sai1-sdo2 { + rockchip,pins = + <1 RK_PD1 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_sai1_sdo3: rm-io29-sai1-sdo3 { + rockchip,pins = + <1 RK_PD1 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi0_clk: rm-io29-spi0-clk { + rockchip,pins = + <1 RK_PD1 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi0_mosi: rm-io29-spi0-mosi { + rockchip,pins = + <1 RK_PD1 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi0_miso: rm-io29-spi0-miso { + rockchip,pins = + <1 RK_PD1 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi0_csn0: rm-io29-spi0-csn0 { + rockchip,pins = + <1 RK_PD1 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi0_csn1: rm-io29-spi0-csn1 { + rockchip,pins = + <1 RK_PD1 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi1_clk: rm-io29-spi1-clk { + rockchip,pins = + <1 RK_PD1 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi1_mosi: rm-io29-spi1-mosi { + rockchip,pins = + <1 RK_PD1 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi1_miso: rm-io29-spi1-miso { + rockchip,pins = + <1 RK_PD1 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi1_csn0: rm-io29-spi1-csn0 { + rockchip,pins = + <1 RK_PD1 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spi1_csn1: rm-io29-spi1-csn1 { + rockchip,pins = + <1 RK_PD1 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_wdt_tsadc_shut: rm-io29-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PD1 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pmu_sleep: rm-io29-pmu-sleep { + rockchip,pins = + <1 RK_PD1 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_core_power_off: rm-io29-core-power-off { + rockchip,pins = + <1 RK_PD1 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spdif_tx: rm-io29-spdif-tx { + rockchip,pins = + <1 RK_PD1 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_spdif_rx: rm-io29-spdif-rx { + rockchip,pins = + <1 RK_PD1 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a0: rm-io29-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PD1 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a1: rm-io29-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PD1 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a2: rm-io29-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PD1 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a3: rm-io29-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PD1 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a4: rm-io29-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PD1 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_a5: rm-io29-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PD1 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b0: rm-io29-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PD1 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b1: rm-io29-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PD1 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b2: rm-io29-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PD1 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b3: rm-io29-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PD1 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b4: rm-io29-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PD1 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pwm1_bip_cntr_b5: rm-io29-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PD1 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_pdm_clk1: rm-io29-pdm-clk1 { + rockchip,pins = + <1 RK_PD1 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_eth_rmii0_ppsclk: rm-io29-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PD1 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_eth_rmii0_ppstrig: rm-io29-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PD1 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_eth_rmii1_ppsclk: rm-io29-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PD1 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io29_eth_rmii1_ppstrig: rm-io29-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PD1 113 &pcfg_pull_none>; + }; + }; + + rm_io30 { + /omit-if-no-ref/ + rm_io30_uart1_tx: rm-io30-uart1-tx { + rockchip,pins = + <1 RK_PD2 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart1_rx: rm-io30-uart1-rx { + rockchip,pins = + <1 RK_PD2 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io30_uart2_tx: rm-io30-uart2-tx { + rockchip,pins = + <1 RK_PD2 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart2_rx: rm-io30-uart2-rx { + rockchip,pins = + <1 RK_PD2 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io30_uart3_tx: rm-io30-uart3-tx { + rockchip,pins = + <1 RK_PD2 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart3_rx: rm-io30-uart3-rx { + rockchip,pins = + <1 RK_PD2 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io30_uart3_ctsn: rm-io30-uart3-ctsn { + rockchip,pins = + <1 RK_PD2 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart3_rtsn: rm-io30-uart3-rtsn { + rockchip,pins = + <1 RK_PD2 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart4_tx: rm-io30-uart4-tx { + rockchip,pins = + <1 RK_PD2 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart4_rx: rm-io30-uart4-rx { + rockchip,pins = + <1 RK_PD2 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io30_uart4_ctsn: rm-io30-uart4-ctsn { + rockchip,pins = + <1 RK_PD2 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_uart4_rtsn: rm-io30-uart4-rtsn { + rockchip,pins = + <1 RK_PD2 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_mipite: rm-io30-mipite { + rockchip,pins = + <1 RK_PD2 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_clk_32k: rm-io30-clk-32k { + rockchip,pins = + <1 RK_PD2 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c0_scl: rm-io30-i2c0-scl { + rockchip,pins = + <1 RK_PD2 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c0_sda: rm-io30-i2c0-sda { + rockchip,pins = + <1 RK_PD2 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c1_scl: rm-io30-i2c1-scl { + rockchip,pins = + <1 RK_PD2 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c1_sda: rm-io30-i2c1-sda { + rockchip,pins = + <1 RK_PD2 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c2_scl: rm-io30-i2c2-scl { + rockchip,pins = + <1 RK_PD2 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_i2c2_sda: rm-io30-i2c2-sda { + rockchip,pins = + <1 RK_PD2 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_clk0: rm-io30-pdm-clk0 { + rockchip,pins = + <1 RK_PD2 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_sdi0: rm-io30-pdm-sdi0 { + rockchip,pins = + <1 RK_PD2 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_sdi1: rm-io30-pdm-sdi1 { + rockchip,pins = + <1 RK_PD2 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_sdi2: rm-io30-pdm-sdi2 { + rockchip,pins = + <1 RK_PD2 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_sdi3: rm-io30-pdm-sdi3 { + rockchip,pins = + <1 RK_PD2 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_can1_tx: rm-io30-can1-tx { + rockchip,pins = + <1 RK_PD2 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_can1_rx: rm-io30-can1-rx { + rockchip,pins = + <1 RK_PD2 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_can0_tx: rm-io30-can0-tx { + rockchip,pins = + <1 RK_PD2 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_can0_rx: rm-io30-can0-rx { + rockchip,pins = + <1 RK_PD2 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm0_ch0: rm-io30-pwm0-ch0 { + rockchip,pins = + <1 RK_PD2 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm0_ch1: rm-io30-pwm0-ch1 { + rockchip,pins = + <1 RK_PD2 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm0_ch2: rm-io30-pwm0-ch2 { + rockchip,pins = + <1 RK_PD2 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm0_ch3: rm-io30-pwm0-ch3 { + rockchip,pins = + <1 RK_PD2 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch0: rm-io30-pwm1-ch0 { + rockchip,pins = + <1 RK_PD2 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch1: rm-io30-pwm1-ch1 { + rockchip,pins = + <1 RK_PD2 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch2: rm-io30-pwm1-ch2 { + rockchip,pins = + <1 RK_PD2 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch3: rm-io30-pwm1-ch3 { + rockchip,pins = + <1 RK_PD2 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch4: rm-io30-pwm1-ch4 { + rockchip,pins = + <1 RK_PD2 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch5: rm-io30-pwm1-ch5 { + rockchip,pins = + <1 RK_PD2 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch6: rm-io30-pwm1-ch6 { + rockchip,pins = + <1 RK_PD2 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_ch7: rm-io30-pwm1-ch7 { + rockchip,pins = + <1 RK_PD2 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_drive: rm-io30-touch-key-drive { + rockchip,pins = + <1 RK_PD2 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in0: rm-io30-touch-key-in0 { + rockchip,pins = + <1 RK_PD2 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in1: rm-io30-touch-key-in1 { + rockchip,pins = + <1 RK_PD2 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in2: rm-io30-touch-key-in2 { + rockchip,pins = + <1 RK_PD2 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in3: rm-io30-touch-key-in3 { + rockchip,pins = + <1 RK_PD2 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in4: rm-io30-touch-key-in4 { + rockchip,pins = + <1 RK_PD2 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in5: rm-io30-touch-key-in5 { + rockchip,pins = + <1 RK_PD2 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in6: rm-io30-touch-key-in6 { + rockchip,pins = + <1 RK_PD2 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_touch_key_in7: rm-io30-touch-key-in7 { + rockchip,pins = + <1 RK_PD2 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_mclk: rm-io30-sai0-mclk { + rockchip,pins = + <1 RK_PD2 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sclk: rm-io30-sai0-sclk { + rockchip,pins = + <1 RK_PD2 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_lrck: rm-io30-sai0-lrck { + rockchip,pins = + <1 RK_PD2 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sdi0: rm-io30-sai0-sdi0 { + rockchip,pins = + <1 RK_PD2 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sdi1: rm-io30-sai0-sdi1 { + rockchip,pins = + <1 RK_PD2 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sdi2: rm-io30-sai0-sdi2 { + rockchip,pins = + <1 RK_PD2 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sdi3: rm-io30-sai0-sdi3 { + rockchip,pins = + <1 RK_PD2 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai0_sdo: rm-io30-sai0-sdo { + rockchip,pins = + <1 RK_PD2 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_mclk: rm-io30-sai1-mclk { + rockchip,pins = + <1 RK_PD2 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sclk: rm-io30-sai1-sclk { + rockchip,pins = + <1 RK_PD2 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_lrck: rm-io30-sai1-lrck { + rockchip,pins = + <1 RK_PD2 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sdi: rm-io30-sai1-sdi { + rockchip,pins = + <1 RK_PD2 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sdo0: rm-io30-sai1-sdo0 { + rockchip,pins = + <1 RK_PD2 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sdo1: rm-io30-sai1-sdo1 { + rockchip,pins = + <1 RK_PD2 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sdo2: rm-io30-sai1-sdo2 { + rockchip,pins = + <1 RK_PD2 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_sai1_sdo3: rm-io30-sai1-sdo3 { + rockchip,pins = + <1 RK_PD2 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi0_clk: rm-io30-spi0-clk { + rockchip,pins = + <1 RK_PD2 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi0_mosi: rm-io30-spi0-mosi { + rockchip,pins = + <1 RK_PD2 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi0_miso: rm-io30-spi0-miso { + rockchip,pins = + <1 RK_PD2 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi0_csn0: rm-io30-spi0-csn0 { + rockchip,pins = + <1 RK_PD2 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi0_csn1: rm-io30-spi0-csn1 { + rockchip,pins = + <1 RK_PD2 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi1_clk: rm-io30-spi1-clk { + rockchip,pins = + <1 RK_PD2 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi1_mosi: rm-io30-spi1-mosi { + rockchip,pins = + <1 RK_PD2 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi1_miso: rm-io30-spi1-miso { + rockchip,pins = + <1 RK_PD2 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi1_csn0: rm-io30-spi1-csn0 { + rockchip,pins = + <1 RK_PD2 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spi1_csn1: rm-io30-spi1-csn1 { + rockchip,pins = + <1 RK_PD2 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_wdt_tsadc_shut: rm-io30-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PD2 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pmu_sleep: rm-io30-pmu-sleep { + rockchip,pins = + <1 RK_PD2 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_core_power_off: rm-io30-core-power-off { + rockchip,pins = + <1 RK_PD2 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spdif_tx: rm-io30-spdif-tx { + rockchip,pins = + <1 RK_PD2 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_spdif_rx: rm-io30-spdif-rx { + rockchip,pins = + <1 RK_PD2 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a0: rm-io30-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PD2 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a1: rm-io30-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PD2 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a2: rm-io30-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PD2 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a3: rm-io30-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PD2 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a4: rm-io30-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PD2 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_a5: rm-io30-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PD2 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b0: rm-io30-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PD2 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b1: rm-io30-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PD2 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b2: rm-io30-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PD2 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b3: rm-io30-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PD2 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b4: rm-io30-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PD2 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pwm1_bip_cntr_b5: rm-io30-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PD2 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_pdm_clk1: rm-io30-pdm-clk1 { + rockchip,pins = + <1 RK_PD2 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_eth_rmii0_ppsclk: rm-io30-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PD2 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_eth_rmii0_ppstrig: rm-io30-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PD2 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_eth_rmii1_ppsclk: rm-io30-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PD2 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io30_eth_rmii1_ppstrig: rm-io30-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PD2 113 &pcfg_pull_none>; + }; + }; + + rm_io31 { + /omit-if-no-ref/ + rm_io31_uart1_tx: rm-io31-uart1-tx { + rockchip,pins = + <1 RK_PD3 16 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart1_rx: rm-io31-uart1-rx { + rockchip,pins = + <1 RK_PD3 17 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io31_uart2_tx: rm-io31-uart2-tx { + rockchip,pins = + <1 RK_PD3 18 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart2_rx: rm-io31-uart2-rx { + rockchip,pins = + <1 RK_PD3 19 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io31_uart3_tx: rm-io31-uart3-tx { + rockchip,pins = + <1 RK_PD3 20 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart3_rx: rm-io31-uart3-rx { + rockchip,pins = + <1 RK_PD3 21 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io31_uart3_ctsn: rm-io31-uart3-ctsn { + rockchip,pins = + <1 RK_PD3 22 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart3_rtsn: rm-io31-uart3-rtsn { + rockchip,pins = + <1 RK_PD3 23 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart4_tx: rm-io31-uart4-tx { + rockchip,pins = + <1 RK_PD3 24 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart4_rx: rm-io31-uart4-rx { + rockchip,pins = + <1 RK_PD3 25 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + rm_io31_uart4_ctsn: rm-io31-uart4-ctsn { + rockchip,pins = + <1 RK_PD3 26 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_uart4_rtsn: rm-io31-uart4-rtsn { + rockchip,pins = + <1 RK_PD3 27 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_mipite: rm-io31-mipite { + rockchip,pins = + <1 RK_PD3 28 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_clk_32k: rm-io31-clk-32k { + rockchip,pins = + <1 RK_PD3 29 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c0_scl: rm-io31-i2c0-scl { + rockchip,pins = + <1 RK_PD3 30 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c0_sda: rm-io31-i2c0-sda { + rockchip,pins = + <1 RK_PD3 31 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c1_scl: rm-io31-i2c1-scl { + rockchip,pins = + <1 RK_PD3 32 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c1_sda: rm-io31-i2c1-sda { + rockchip,pins = + <1 RK_PD3 33 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c2_scl: rm-io31-i2c2-scl { + rockchip,pins = + <1 RK_PD3 34 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_i2c2_sda: rm-io31-i2c2-sda { + rockchip,pins = + <1 RK_PD3 35 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_clk0: rm-io31-pdm-clk0 { + rockchip,pins = + <1 RK_PD3 36 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_sdi0: rm-io31-pdm-sdi0 { + rockchip,pins = + <1 RK_PD3 37 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_sdi1: rm-io31-pdm-sdi1 { + rockchip,pins = + <1 RK_PD3 38 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_sdi2: rm-io31-pdm-sdi2 { + rockchip,pins = + <1 RK_PD3 39 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_sdi3: rm-io31-pdm-sdi3 { + rockchip,pins = + <1 RK_PD3 40 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_can1_tx: rm-io31-can1-tx { + rockchip,pins = + <1 RK_PD3 41 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_can1_rx: rm-io31-can1-rx { + rockchip,pins = + <1 RK_PD3 42 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_can0_tx: rm-io31-can0-tx { + rockchip,pins = + <1 RK_PD3 43 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_can0_rx: rm-io31-can0-rx { + rockchip,pins = + <1 RK_PD3 44 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm0_ch0: rm-io31-pwm0-ch0 { + rockchip,pins = + <1 RK_PD3 45 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm0_ch1: rm-io31-pwm0-ch1 { + rockchip,pins = + <1 RK_PD3 46 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm0_ch2: rm-io31-pwm0-ch2 { + rockchip,pins = + <1 RK_PD3 47 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm0_ch3: rm-io31-pwm0-ch3 { + rockchip,pins = + <1 RK_PD3 48 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch0: rm-io31-pwm1-ch0 { + rockchip,pins = + <1 RK_PD3 49 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch1: rm-io31-pwm1-ch1 { + rockchip,pins = + <1 RK_PD3 50 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch2: rm-io31-pwm1-ch2 { + rockchip,pins = + <1 RK_PD3 51 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch3: rm-io31-pwm1-ch3 { + rockchip,pins = + <1 RK_PD3 52 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch4: rm-io31-pwm1-ch4 { + rockchip,pins = + <1 RK_PD3 53 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch5: rm-io31-pwm1-ch5 { + rockchip,pins = + <1 RK_PD3 54 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch6: rm-io31-pwm1-ch6 { + rockchip,pins = + <1 RK_PD3 55 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_ch7: rm-io31-pwm1-ch7 { + rockchip,pins = + <1 RK_PD3 56 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_drive: rm-io31-touch-key-drive { + rockchip,pins = + <1 RK_PD3 57 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in0: rm-io31-touch-key-in0 { + rockchip,pins = + <1 RK_PD3 58 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in1: rm-io31-touch-key-in1 { + rockchip,pins = + <1 RK_PD3 59 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in2: rm-io31-touch-key-in2 { + rockchip,pins = + <1 RK_PD3 60 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in3: rm-io31-touch-key-in3 { + rockchip,pins = + <1 RK_PD3 61 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in4: rm-io31-touch-key-in4 { + rockchip,pins = + <1 RK_PD3 62 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in5: rm-io31-touch-key-in5 { + rockchip,pins = + <1 RK_PD3 63 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in6: rm-io31-touch-key-in6 { + rockchip,pins = + <1 RK_PD3 64 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_touch_key_in7: rm-io31-touch-key-in7 { + rockchip,pins = + <1 RK_PD3 65 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_mclk: rm-io31-sai0-mclk { + rockchip,pins = + <1 RK_PD3 66 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sclk: rm-io31-sai0-sclk { + rockchip,pins = + <1 RK_PD3 67 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_lrck: rm-io31-sai0-lrck { + rockchip,pins = + <1 RK_PD3 68 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sdi0: rm-io31-sai0-sdi0 { + rockchip,pins = + <1 RK_PD3 69 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sdi1: rm-io31-sai0-sdi1 { + rockchip,pins = + <1 RK_PD3 70 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sdi2: rm-io31-sai0-sdi2 { + rockchip,pins = + <1 RK_PD3 71 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sdi3: rm-io31-sai0-sdi3 { + rockchip,pins = + <1 RK_PD3 72 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai0_sdo: rm-io31-sai0-sdo { + rockchip,pins = + <1 RK_PD3 73 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_mclk: rm-io31-sai1-mclk { + rockchip,pins = + <1 RK_PD3 74 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sclk: rm-io31-sai1-sclk { + rockchip,pins = + <1 RK_PD3 75 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_lrck: rm-io31-sai1-lrck { + rockchip,pins = + <1 RK_PD3 76 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sdi: rm-io31-sai1-sdi { + rockchip,pins = + <1 RK_PD3 77 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sdo0: rm-io31-sai1-sdo0 { + rockchip,pins = + <1 RK_PD3 78 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sdo1: rm-io31-sai1-sdo1 { + rockchip,pins = + <1 RK_PD3 79 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sdo2: rm-io31-sai1-sdo2 { + rockchip,pins = + <1 RK_PD3 80 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_sai1_sdo3: rm-io31-sai1-sdo3 { + rockchip,pins = + <1 RK_PD3 81 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi0_clk: rm-io31-spi0-clk { + rockchip,pins = + <1 RK_PD3 82 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi0_mosi: rm-io31-spi0-mosi { + rockchip,pins = + <1 RK_PD3 83 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi0_miso: rm-io31-spi0-miso { + rockchip,pins = + <1 RK_PD3 84 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi0_csn0: rm-io31-spi0-csn0 { + rockchip,pins = + <1 RK_PD3 85 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi0_csn1: rm-io31-spi0-csn1 { + rockchip,pins = + <1 RK_PD3 86 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi1_clk: rm-io31-spi1-clk { + rockchip,pins = + <1 RK_PD3 87 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi1_mosi: rm-io31-spi1-mosi { + rockchip,pins = + <1 RK_PD3 88 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi1_miso: rm-io31-spi1-miso { + rockchip,pins = + <1 RK_PD3 89 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi1_csn0: rm-io31-spi1-csn0 { + rockchip,pins = + <1 RK_PD3 90 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spi1_csn1: rm-io31-spi1-csn1 { + rockchip,pins = + <1 RK_PD3 91 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_wdt_tsadc_shut: rm-io31-wdt-tsadc-shut { + rockchip,pins = + <1 RK_PD3 92 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pmu_sleep: rm-io31-pmu-sleep { + rockchip,pins = + <1 RK_PD3 93 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_core_power_off: rm-io31-core-power-off { + rockchip,pins = + <1 RK_PD3 94 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spdif_tx: rm-io31-spdif-tx { + rockchip,pins = + <1 RK_PD3 95 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_spdif_rx: rm-io31-spdif-rx { + rockchip,pins = + <1 RK_PD3 96 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a0: rm-io31-pwm1-bip-cntr-a0 { + rockchip,pins = + <1 RK_PD3 97 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a1: rm-io31-pwm1-bip-cntr-a1 { + rockchip,pins = + <1 RK_PD3 98 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a2: rm-io31-pwm1-bip-cntr-a2 { + rockchip,pins = + <1 RK_PD3 99 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a3: rm-io31-pwm1-bip-cntr-a3 { + rockchip,pins = + <1 RK_PD3 100 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a4: rm-io31-pwm1-bip-cntr-a4 { + rockchip,pins = + <1 RK_PD3 101 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_a5: rm-io31-pwm1-bip-cntr-a5 { + rockchip,pins = + <1 RK_PD3 102 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b0: rm-io31-pwm1-bip-cntr-b0 { + rockchip,pins = + <1 RK_PD3 103 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b1: rm-io31-pwm1-bip-cntr-b1 { + rockchip,pins = + <1 RK_PD3 104 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b2: rm-io31-pwm1-bip-cntr-b2 { + rockchip,pins = + <1 RK_PD3 105 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b3: rm-io31-pwm1-bip-cntr-b3 { + rockchip,pins = + <1 RK_PD3 106 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b4: rm-io31-pwm1-bip-cntr-b4 { + rockchip,pins = + <1 RK_PD3 107 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pwm1_bip_cntr_b5: rm-io31-pwm1-bip-cntr-b5 { + rockchip,pins = + <1 RK_PD3 108 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_pdm_clk1: rm-io31-pdm-clk1 { + rockchip,pins = + <1 RK_PD3 109 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_eth_rmii0_ppsclk: rm-io31-eth-rmii0-ppsclk { + rockchip,pins = + <1 RK_PD3 110 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_eth_rmii0_ppstrig: rm-io31-eth-rmii0-ppstrig { + rockchip,pins = + <1 RK_PD3 111 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_eth_rmii1_ppsclk: rm-io31-eth-rmii1-ppsclk { + rockchip,pins = + <1 RK_PD3 112 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rm_io31_eth_rmii1_ppstrig: rm-io31-eth-rmii1-ppstrig { + rockchip,pins = + <1 RK_PD3 113 &pcfg_pull_none>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 4d8514b8c65c..f501c223be8e 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -280,6 +280,11 @@ <0xff814000 0x1000>; }; + grf_pmu: syscon@ff910000 { + compatible = "rockchip,rk3506-grf-pmu", "syscon"; + reg = <0xff910000 0x4000>; + }; + pwm0_4ch_0: pwm@ff930000 { compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff930000 0x200>; @@ -338,6 +343,7 @@ rockchip,grf = <&ioc_grf>; rockchip,ioc1 = <&ioc1>; rockchip,pmu = <&ioc_pmu>; + rockchip,rmio = <&grf_pmu>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -410,3 +416,4 @@ }; #include "rk3506-pinctrl.dtsi" +#include "rk3506-pinctrl-rmio.dtsi" From 7a0978f7820f09eec312135b10dcf88870ac50d4 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Mon, 3 Jun 2024 17:37:11 +0800 Subject: [PATCH 116/191] ARM: dts: rockchip: rk3506: add hwspinlock/mailbox nodes This adds HWSpinlock/Mailbox DT for RK3506 SoC. Signed-off-by: Frank Wang Change-Id: I4612eead10070777307878af88550fd695c8e72d --- arch/arm/boot/dts/rk3506.dtsi | 72 +++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index f501c223be8e..ea1eb2603e8a 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -195,6 +195,38 @@ status = "disabled"; }; + hwlock0: hwspinlock@ff240000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff240000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock1: hwspinlock@ff241000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff241000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock2: hwspinlock@ff242000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff242000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + + hwlock3: hwspinlock@ff243000 { + compatible = "rockchip,hwspinlock"; + reg = <0xff243000 0x20>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <8>; + status = "disabled"; + }; + grf: syscon@ff288000 { compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; reg = <0xff288000 0x4000>; @@ -221,6 +253,46 @@ }; }; + mailbox0: mailbox@ff290000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff290000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox1: mailbox@ff291000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff291000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox2: mailbox@ff292000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff292000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox3: mailbox@ff293000 { + compatible = "rockchip,rk3506-mailbox", "rockchip,rk3576-mailbox"; + reg = <0xff293000 0x20>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + fspi: spi@ff488000 { compatible = "rockchip,fspi"; reg = <0xff488000 0x4000>; From 71a4b6dca77cb721617bbf029f255e36c4d65eb9 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 5 Jun 2024 16:01:30 +0800 Subject: [PATCH 117/191] ARM: dts: rockchip: rk3506: add DMAC/UART nodes Change-Id: Id804041ae57f7e8551e0ab4f3d9233b74dbebc42 Signed-off-by: Huibin Hong --- arch/arm/boot/dts/rk3506.dtsi | 95 ++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index ea1eb2603e8a..3ec92bc8811f 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -23,6 +23,11 @@ gpio3 = &gpio3; gpio4 = &gpio4; serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; spi2 = &fspi; }; @@ -105,13 +110,87 @@ clock-frequency = <24000000>; }; + dmac0: dma-controller@ff000000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff000000 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dma-controller@ff008000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff008000 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + uart0: serial@ff0a0000 { compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; reg = <0xff0a0000 0x100>; interrupts = ; - clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + dmas = <&dmac0 4>, <&dmac0 5>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer_pins>; + status = "disabled"; + }; + + uart1: serial@ff0b0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0b0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@ff0c0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0c0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@ff0d0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0d0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@ff0e0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff0e0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 12>, <&dmac1 13>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; status = "disabled"; }; @@ -309,6 +388,20 @@ reg = <0xff4d8000 0x8000>; }; + uart5: serial@ff4e0000 { + compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; + reg = <0xff4e0000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 14>, <&dmac1 15>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; + status = "disabled"; + }; + gic: interrupt-controller@ff581000 { compatible = "arm,gic-400"; reg = <0xff581000 0x1000>, From 945a065db49e73a426e4155a39ae74e93c93b1c3 Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 11 Apr 2024 18:17:15 +0800 Subject: [PATCH 118/191] ARM: dts: RK3506: add RGA node Signed-off-by: Yu Qiaowei Change-Id: I064ec3bb7329291266b6fd52c4bfcac8f0bf94d9 --- arch/arm/boot/dts/rk3506.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 3ec92bc8811f..0e0c5781bbcd 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -433,6 +433,16 @@ }; }; + rga2: rga@ff610000 { + compatible = "rockchip,rga2"; + reg = <0xff610000 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + status = "disabled"; + }; + ioc1: syscon@ff660000 { compatible = "rockchip,rk3506-ioc1", "syscon"; reg = <0xff660000 0x10000>; From 4b4c0f34082a694eea9e31e452a1a02fd4629648 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Mon, 3 Jun 2024 19:45:12 +0800 Subject: [PATCH 119/191] ARM: dts: rockchip: rk3506: add pinctrl configs for vop Change-Id: I13a7f67351bf2b376b41ed1f25d1a912cf8678f2 Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-pinctrl.dtsi | 305 ++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-pinctrl.dtsi b/arch/arm/boot/dts/rk3506-pinctrl.dtsi index 2d14d841cab4..bdfde8e7c839 100644 --- a/arch/arm/boot/dts/rk3506-pinctrl.dtsi +++ b/arch/arm/boot/dts/rk3506-pinctrl.dtsi @@ -1446,3 +1446,308 @@ }; }; }; + +/* + * This part is edited handly. + */ +&pinctrl { + vo_lcdc { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656_m0_pins: bt656-m0-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656_m1_pins: bt656-m1-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb3x8_rgb2x8_m0_pins: rgb3x8-rgb2x8-m0-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb3x8_rgb2x8_m1_pins: rgb3x8-rgb2x8-m1-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <1 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgb888_pins: rgb888-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <1 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <1 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <1 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <1 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <1 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <1 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <1 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <1 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <1 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <1 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <1 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <1 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <1 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <1 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <1 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <1 RK_PA1 1 &pcfg_pull_none>; + }; + }; +}; From e30a89f393a8399655fda7a3b4a4a00df242c4e1 Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Mon, 17 Jun 2024 11:46:01 +0800 Subject: [PATCH 120/191] ARM: dts: rk3506: Add tsadc/thermal_zones node Signed-off-by: Ye Zhang Change-Id: I888cb1e358cf018c2c1ae406110c28b96a6c3a1c --- arch/arm/boot/dts/rk3506.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 0e0c5781bbcd..27fe997f7505 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -101,6 +101,23 @@ method = "smc"; }; + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 0>; + trips { + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -443,6 +460,24 @@ status = "disabled"; }; + tsadc: tsadc@ff650000 { + compatible = "rockchip,rk3506-tsadc"; + reg = <0xff650000 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; + clock-names = "tsadc", "apb_pclk", "tsen"; + assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; + assigned-clock-rates = <1000000>, <12000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "disabled"; + }; + ioc1: syscon@ff660000 { compatible = "rockchip,rk3506-ioc1", "syscon"; reg = <0xff660000 0x10000>; From 554a89fd6d284dbcbd1df438998cfd1c59e05093 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 17 Jun 2024 15:37:09 +0800 Subject: [PATCH 121/191] ARM: dts: rk3506: Add i2c nodes Change-Id: Ib860e9b93fff8a0d84b1ecb35279a911420c9f10 Signed-off-by: David Wu --- arch/arm/boot/dts/rk3506.dtsi | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 27fe997f7505..a6d1a6ba2fe6 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -22,6 +22,9 @@ gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -149,6 +152,39 @@ arm,pl330-periph-burst; }; + i2c0: i2c@ff040000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff040000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + + i2c1: i2c@ff050000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff050000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@ff060000 { + compatible = "rockchip,rk3506-i2c", "rockchip,rk3399-i2c"; + reg = <0xff060000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + status = "disabled"; + }; + uart0: serial@ff0a0000 { compatible = "rockchip,rk3506-uart", "snps,dw-apb-uart"; reg = <0xff0a0000 0x100>; From f090d642cdb284caeec24f5e070b73936aa1958f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 17 Jun 2024 11:36:39 +0800 Subject: [PATCH 122/191] ARM: dts: RK3506: add CAN dts nodes Change-Id: I091746467f07dd3c9840179f634467f28a54eb1e Signed-off-by: Elaine Zhang Signed-off-by: Finley Xiao --- arch/arm/boot/dts/rk3506.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index a6d1a6ba2fe6..1225de9ea729 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -425,6 +425,28 @@ status = "disabled"; }; + can0: can@ff320000 { + compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; + reg = <0xff320000 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_H_CAN0>; + reset-names = "can", "can-apb"; + status = "disabled"; + }; + + can1: can@ff330000 { + compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; + reg = <0xff330000 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_H_CAN1>; + reset-names = "can", "can-apb"; + status = "disabled"; + }; + fspi: spi@ff488000 { compatible = "rockchip,fspi"; reg = <0xff488000 0x4000>; From 5053336fd5bbccefac1d15be766de74a4fa81512 Mon Sep 17 00:00:00 2001 From: Xuhui Lin Date: Tue, 18 Jun 2024 12:41:53 +0800 Subject: [PATCH 123/191] ARM: dts: rk3506: Add spi nodes Change-Id: I05eed1a4be8ef58b0ccc5335d09080aa67ea424b Signed-off-by: Xuhui Lin --- arch/arm/boot/dts/rk3506.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 1225de9ea729..3d607dec85da 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -31,6 +31,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; + spi0 = &spi0; + spi1 = &spi1; spi2 = &fspi; }; @@ -247,6 +249,36 @@ status = "disabled"; }; + spi0: spi@ff120000 { + compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; + reg = <0xff120000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_csn0_pins &spi0_csn1_pins &spi0_clk_pins>; + status = "disabled"; + }; + + spi1: spi@ff130000 { + compatible = "rockchip,rk3506-spi", "rockchip,rk3066-spi"; + reg = <0xff130000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_csn0_pins &spi1_csn1_pins &spi1_clk_pins>; + status = "disabled"; + }; + pwm1_8ch_0: pwm@ff170000 { compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm"; reg = <0xff170000 0x200>; From 07565cc55436c5ab8ff5d5e11e5b4bf2aeaeb988 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Mon, 17 Jun 2024 16:13:46 +0800 Subject: [PATCH 124/191] ARM: dts: rk3506: Add flexbus node Change-Id: I31cab3bdd40cde7f5ab3dd4bc02c9bc7a6ca1d01 Signed-off-by: Wesley Yao --- arch/arm/boot/dts/rk3506.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 3d607dec85da..4e07e722b669 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -580,6 +580,36 @@ <0xff814000 0x1000>; }; + flexbus: flexbus@ff880000 { + compatible = "rockchip,rk3506-flexbus"; + reg = <0xff880000 0x200>; + interrupts = ; + clocks = <&cru CLK_FLEXBUS_TX>, <&cru CLK_FLEXBUS_RX>, + <&cru ACLK_FLEXBUS>, <&cru HCLK_FLEXBUS>; + clock-names = "tx_clk_flexbus", "rx_clk_flexbus", + "aclk_flexbus", "hclk_flexbus"; + rockchip,grf = <&grf>; + status = "disabled"; + + flexbus_adc: adc { + compatible = "rockchip,flexbus-adc"; + #io-channel-cells = <0>; + rockchip,slave-mode; + rockchip,free-sclk; + rockchip,auto-pad; + rockchip,dfs = <16>; + status = "disabled"; + }; + + flexbus_dac: dac { + compatible = "rockchip,flexbus-dac"; + #io-channel-cells = <0>; + rockchip,free-sclk; + rockchip,dfs = <16>; + status = "disabled"; + }; + }; + grf_pmu: syscon@ff910000 { compatible = "rockchip,rk3506-grf-pmu", "syscon"; reg = <0xff910000 0x4000>; From 15f82e0d7ebb0581d13b3c77c69cc07d99e0c957 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Mon, 24 Jun 2024 11:34:44 +0800 Subject: [PATCH 125/191] ARM: dts: rockchip: rk3506: add flexbus cif Signed-off-by: Zefa Chen Change-Id: I53ff326583920615a20509a34bb8e79887dd876a --- arch/arm/boot/dts/rk3506.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 4e07e722b669..5f7e50a66ccc 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -601,6 +601,11 @@ status = "disabled"; }; + flexbus_cif: cif { + compatible = "rockchip,flexbus-cif-rk3506"; + status = "disabled"; + }; + flexbus_dac: dac { compatible = "rockchip,flexbus-dac"; #io-channel-cells = <0>; From 2474aa08d019647d478495896edfb9487fbb1ac6 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Tue, 18 Jun 2024 11:59:09 +0800 Subject: [PATCH 126/191] ARM: dts: rockchip: rk3506: add acdcdig_dsm/pdm node Change-Id: I8af92d054d73e59ce71225e9f72b33250db7ca6b Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3506.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 5f7e50a66ccc..21bb021bdf43 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -479,6 +479,26 @@ status = "disabled"; }; + pdm: pdm@ff380000 { + compatible = "rockchip,rk3506-pdm", "rockchip,rk3576-pdm"; + reg = <0xff380000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; + clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; + dmas = <&dmac1 9>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_pdm_clk0 + &rm_io0_pdm_clk1 + &rm_io0_pdm_sdi0 + &rm_io0_pdm_sdi1 + &rm_io0_pdm_sdi2 + &rm_io0_pdm_sdi3>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM0"; + status = "disabled"; + }; + fspi: spi@ff488000 { compatible = "rockchip,fspi"; reg = <0xff488000 0x4000>; @@ -490,6 +510,23 @@ status = "disabled"; }; + acdcdig_dsm: acdcdig-dsm@ff4b0000 { + compatible = "rockchip,rk3506-dsm"; + reg = <0xff4b0000 0x1000>; + clocks = <&cru MCLK_DSM>, <&cru HCLK_DSM>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_M_DSM>; + reset-names = "reset" ; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_audm0_ln_pins + &dsm_audm0_lp_pins + &dsm_audm0_rn_pins + &dsm_audm0_rp_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + ioc_grf: syscon@ff4d8000 { compatible = "rockchip,rk3506-ioc-grf", "syscon"; reg = <0xff4d8000 0x8000>; From 7be89c5ef0be744f8221a54143aec447877bc6da Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Fri, 24 May 2024 18:06:40 +0800 Subject: [PATCH 127/191] ARM: dts: rockchip: Add usb controllers and usb2 phy nodes for RK3506 Soc Change-Id: I20ebbbe5d19bab6cb270b4930cebd7fcd72a9c7f Signed-off-by: Jianwei Zheng --- arch/arm/boot/dts/rk3506.dtsi | 66 +++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 21bb021bdf43..fbd2bee5a95b 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -457,6 +457,38 @@ status = "disabled"; }; + usb2phy: usb2-phy@ff2b0000 { + compatible = "rockchip,rk3506-usb2phy"; + reg = <0xff2b0000 0x8000>; + clocks = <&cru CLK_REF_USBPHY_TOP>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "apb_pclk"; + #clock-cells = <0>; + rockchip,usbgrf = <&grf>; + status = "disabled"; + + u2phy_otg0: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", + "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_otg1: host-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", + "otg-id", + "linestate"; + status = "disabled"; + }; + }; + can0: can@ff320000 { compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; reg = <0xff320000 0x1000>; @@ -610,6 +642,40 @@ reg = <0xff660000 0x10000>; }; + usb20_otg0: usb@ff740000 { + compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff740000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBOTG0>, <&cru HCLK_USBOTG0_PMU>, + <&cru CLK_USBOTG0_ADP>; + clock-names = "otg", "pmu", "adp"; + dr_mode = "otg"; + phys = <&u2phy_otg0>; + phy-names = "usb2-phy"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + status = "disabled"; + }; + + usb20_otg1: usb@ff780000 { + compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff780000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBOTG1>, <&cru HCLK_USBOTG1_PMU>, + <&cru CLK_USBOTG1_ADP>; + clock-names = "otg", "pmu", "adp"; + dr_mode = "otg"; + phys = <&u2phy_otg1>; + phy-names = "usb2-phy"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + status = "disabled"; + }; + arm-debug@ff810000 { compatible = "rockchip,debug"; reg = <0xff810000 0x1000>, From f1bd21e650b30645c40ba9e707cb76e97f0ca15b Mon Sep 17 00:00:00 2001 From: Simon Xue Date: Tue, 18 Jun 2024 14:48:00 +0800 Subject: [PATCH 128/191] ARM: dts: RK3506: add wdt0/wdt1/saradc Change-Id: Ic50718f3c852cd33566acb71610556bc9f0bd0b8 Signed-off-by: Simon Xue --- arch/arm/boot/dts/rk3506.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index fbd2bee5a95b..ff5a1d48be52 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -391,6 +391,24 @@ status = "disabled"; }; + wdt0: watchdog@ff260000 { + compatible = "snps,dw-wdt"; + reg = <0xff260000 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + wdt1: watchdog@ff268000 { + compatible = "snps,dw-wdt"; + reg = <0xff268000 0x100>; + clocks = <&cru TCLK_WDT1>, <&cru PCLK_WDT1>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + grf: syscon@ff288000 { compatible = "rockchip,rk3506-grf", "syscon", "simple-mfd"; reg = <0xff288000 0x4000>; @@ -578,6 +596,18 @@ status = "disabled"; }; + saradc: adc@ff4e8000 { + compatible = "rockchip,rk3506-saradc", "rockchip,rk3562-saradc"; + reg = <0xff4e8000 0x8000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + gic: interrupt-controller@ff581000 { compatible = "arm,gic-400"; reg = <0xff581000 0x1000>, From 5aeec8ff7c8d96374d8e1d228e24b66b34c40e17 Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Wed, 19 Jun 2024 10:44:20 +0800 Subject: [PATCH 129/191] ARM: dts: rockchip: rk3506: add crypto & rng node Signed-off-by: Lin Jinhan Change-Id: I04458efe3cf446df39e096a76fb68bdfbc4bd348 --- arch/arm/boot/dts/rk3506.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index ff5a1d48be52..8417ea392ff8 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -672,6 +672,29 @@ reg = <0xff660000 0x10000>; }; + crypto: crypto@ff700000 { + compatible = "rockchip,crypto-v4"; + reg = <0xff700000 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_CORE_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; + clock-names = "aclk", "hclk", "core", "pka"; + resets = <&cru SRST_H_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ff710000 { + compatible = "rockchip,rkrng"; + reg = <0xff710000 0x200>; + interrupts = ; + clocks = <&cru HCLK_RNG>; + clock-names = "hclk_trng"; + resets = <&cru SRST_H_RNG>; + reset-names = "reset"; + status = "disabled"; + }; + usb20_otg0: usb@ff740000 { compatible = "rockchip,rk3506-usb", "rockchip,rk3066-usb", "snps,dwc2"; From 63f7e039b7836762e5338c1265d0eeaa0bff4eaf Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Thu, 20 Jun 2024 09:19:55 +0800 Subject: [PATCH 130/191] ARM: dts: rk3506: Add SAI/SPDIF device nodes Signed-off-by: Sugar Zhang Change-Id: I53968fc88d986db3bdb33e6e01ab781b99d622e5 --- arch/arm/boot/dts/rk3506.dtsi | 131 ++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 8417ea392ff8..0ed1a623569b 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -507,6 +507,52 @@ }; }; + sai0: sai@ff300000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff300000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 1>, <&dmac1 0>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI0>, <&cru SRST_H_SAI0>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + pinctrl-names = "default"; + pinctrl-0 = <&sai0_lrck_pins + &sai0_sclk_pins + &sai0_sdi0_pins + &sai0_sdi1_pins + &sai0_sdi2_pins + &sai0_sdi3_pins + &sai0_sdo_pins>; + status = "disabled"; + }; + + sai1: sai@ff310000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff310000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 3>, <&dmac1 2>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI1>, <&cru SRST_H_SAI1>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1_lrck_pins + &sai1_sclk_pins + &sai1_sdi_pins + &sai1_sdo0_pins + &sai1_sdo1_pins + &sai1_sdo2_pins + &sai1_sdo3_pins>; + status = "disabled"; + }; + can0: can@ff320000 { compatible = "rockchip,rk3506-canfd", "rockchip,rk3576-canfd"; reg = <0xff320000 0x1000>; @@ -549,6 +595,36 @@ status = "disabled"; }; + spdif_tx: spdif-tx@ff3a0000 { + compatible = "rockchip,rk3506-spdif", "rockchip,rk3066-spdif"; + reg = <0xff3a0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFTX>, <&cru HCLK_SPDIFTX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 10>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx: spdif-rx@ff3b0000 { + compatible = "rockchip,rk3506-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0xff3b0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX>, <&cru HCLK_SPDIFRX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 11>; + dma-names = "rx"; + resets = <&cru SRST_SPDIFRX>; + reset-names = "spdifrx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_spdif_rx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + fspi: spi@ff488000 { compatible = "rockchip,fspi"; reg = <0xff488000 0x4000>; @@ -560,6 +636,61 @@ status = "disabled"; }; + sai2: sai@ff498000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff498000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 5>, <&dmac1 4>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI2>, <&cru SRST_H_SAI2>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck_pins + &sai2m0_sclk_pins + &sai2m0_sdi_pins + &sai2m0_sdo_pins>; + status = "disabled"; + }; + + sai3: sai@ff4a0000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff4a0000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI3>, <&cru HCLK_SAI3>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 6>, <&dmac1 7>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI3>, <&cru SRST_H_SAI3>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI3"; + pinctrl-names = "default"; + pinctrl-0 = <&sai3_lrck_pins + &sai3_sclk_pins + &sai3_sdi_pins + &sai3_sdo_pins>; + status = "disabled"; + }; + + sai4: sai@ff4a8000 { + compatible = "rockchip,rk3506-sai", "rockchip,sai-v1"; + reg = <0xff4a8000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI4>, <&cru HCLK_SAI4>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 8>; + dma-names = "rx"; + resets = <&cru SRST_M_SAI4>, <&cru SRST_H_SAI4>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI4"; + status = "disabled"; + }; + acdcdig_dsm: acdcdig-dsm@ff4b0000 { compatible = "rockchip,rk3506-dsm"; reg = <0xff4b0000 0x1000>; From e0210ee2f4a2bbc6789db8de02854999322a8b3b Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 17 Jun 2024 17:47:51 +0800 Subject: [PATCH 131/191] ARM: dts: Add gmac support for rk3506 Change-Id: I8fe90a6f30b887f452a36347bfb5bb84b7d36b2c Signed-off-by: David Wu --- arch/arm/boot/dts/rk3506.dtsi | 96 +++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 0ed1a623569b..c83fece098af 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -17,6 +17,8 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -708,6 +710,100 @@ status = "disabled"; }; + gmac0: ethernet@ff4c8000 { + compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a"; + reg = <0xff4c8000 0x2000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_MAC0>, <&cru CLK_MAC0_PTP>, + <&cru PCLK_MAC0>, <&cru ACLK_MAC0>; + clock-names = "stmmaceth", "ptp_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_MAC0>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + + phy-mode = "rmii"; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + gmac1: ethernet@ff4d0000 { + compatible = "rockchip,rk3506-gmac", "snps,dwmac-4.20a"; + reg = <0xff4d0000 0x2000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_MAC1>, <&cru CLK_MAC1_PTP>, + <&cru PCLK_MAC1>, <&cru ACLK_MAC1>; + clock-names = "stmmaceth", "ptp_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_MAC1>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + + phy-mode = "rmii"; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + ioc_grf: syscon@ff4d8000 { compatible = "rockchip,rk3506-ioc-grf", "syscon"; reg = <0xff4d8000 0x8000>; From bce5538f4d855022b88b9c0e00cb908f9f2f5d46 Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Wed, 19 Jun 2024 10:44:42 +0800 Subject: [PATCH 132/191] ARM: dts: rockchip: rk3506: add dsmc & dsmc_slave & dsmc_lb_slave node Change-Id: Ibcccffe7447ce2996047f3f90a2c32f9b5f60838 Signed-off-by: Zhihuan He --- arch/arm/boot/dts/rk3506.dtsi | 215 ++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index c83fece098af..cc12c3450b31 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -998,6 +998,221 @@ }; }; + dsmc_lb_slave: dsmc-lb-slave@ff880000 { + compatible = "rockchip,rk3506-dsmc-lb-slave"; + reg = <0xff880000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + rockchip,grf = <&grf>; + interrupts = ; + resets = <&cru SRST_DSMC_SLV>, <&cru SRST_A_DSMC_SLV>, + <&cru SRST_H_DSMC_SLV>; + reset-names = "dsmc_slv", "a_dsmc_slv", "h_dsmc_slv"; + clocks = <&cru ACLK_DSMC_SLV>, + <&cru HCLK_DSMC_SLV>; + clock-names = "aclk_dsmc_slv", "hclk_dsmc_slv"; + status = "disabled"; + }; + + dsmc: dsmc@ff8b0000 { + compatible = "rockchip,rk3506-dsmc"; + reg = <0xff8b0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + rockchip,grf = <&ioc_grf>; + interrupts = ; + resets = <&cru SRST_A_DSMC>, <&cru SRST_P_DSMC>; + reset-names = "dsmc", "apb"; + clocks = <&cru CLK_DSMC>, + <&cru ACLK_DSMC>, + <&cru PCLK_DSMC>, + <&cru CLK_DSMC>; + clock-names = "clk_sys", "aclk_dsmc", "pclk", "aclk_root"; + clock-frequency = <100000000>; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "req0", "req1"; + status = "disabled"; + slave { + rockchip,dqs-dll = <0x40 0x40 + 0x40 0x40 + 0x40 0x40 + 0x40 0x40>; + rockchip,ranges = <0x0 0xc0000000 0x0 0x2000000>; + rockchip,slave-dev = <&dsmc_slave>; + }; + }; + + dsmc_slave: dsmc-slave { + compatible = "rockchip,dsmc-slave"; + rockchip,clk-mode = <0>; + status = "disabled"; + psram { + dsmc_psram0: psram0 { + status = "disabled"; + }; + dsmc_psram1: psram1 { + status = "disabled"; + }; + dsmc_psram2: psram2 { + status = "disabled"; + }; + dsmc_psram3: psram3 { + status = "disabled"; + }; + }; + + lb-slave { + dsmc_lb_slave0: lb-slave0 { + status = "disabled"; + dsmc_p0_region: region { + dsmc_p0_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave1: lb-slave1 { + status = "disabled"; + dsmc_p1_region: region { + dsmc_p1_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave2: lb-slave2 { + status = "disabled"; + dsmc_p2_region: region { + dsmc_p2_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave3: lb-slave3 { + status = "disabled"; + dsmc_p3_region: region { + dsmc_p3_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + }; + }; + grf_pmu: syscon@ff910000 { compatible = "rockchip,rk3506-grf-pmu", "syscon"; reg = <0xff910000 0x4000>; From f76099f5110eabb0e2a887c046600d1de6174f9f Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Tue, 18 Jun 2024 16:15:34 +0800 Subject: [PATCH 133/191] ARM: dts: rockchip: add rk3503.dtsi Signed-off-by: Huibin Hong Change-Id: I919c5b502621eac4a6db0fcec9a0914c9f923f75 --- arch/arm/boot/dts/rk3503.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 arch/arm/boot/dts/rk3503.dtsi diff --git a/arch/arm/boot/dts/rk3503.dtsi b/arch/arm/boot/dts/rk3503.dtsi new file mode 100644 index 000000000000..7bec89f51977 --- /dev/null +++ b/arch/arm/boot/dts/rk3503.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "rk3506.dtsi" From c3d120bce5f1ec7901eec4944401aee13369896f Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 21 Jun 2024 14:34:24 +0800 Subject: [PATCH 134/191] ARM: dts: rockchip: rk3506: Add mmc node Signed-off-by: Shawn Lin Change-Id: I99c2e17919df6cea704d1a355ca74ea23fb98662 --- arch/arm/boot/dts/rk3506.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index cc12c3450b31..5f5bfe0da0a1 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -627,6 +627,20 @@ status = "disabled"; }; + mmc: mmc@ff480000 { + compatible = "rockchip,rk3506-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xff480000 0x4000>; + interrupts = ; + max-frequency = <150000000>; + bus-width = <4>; + clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + resets = <&cru SRST_H_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + fspi: spi@ff488000 { compatible = "rockchip,fspi"; reg = <0xff488000 0x4000>; From f1a4a909e6e2ab74b4de630322ef9ae386aed54c Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 21 Jun 2024 17:35:18 +0800 Subject: [PATCH 135/191] ARM: dts: rk3506: Add SAIx_MCLK{OUT,IN} nodes Signed-off-by: Sugar Zhang Change-Id: Iab05e8dfa9745c39a4e1e221bac69db7a40cf42b --- arch/arm/boot/dts/rk3506.dtsi | 67 +++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 5f5bfe0da0a1..a41c39b8a114 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -40,6 +40,9 @@ clocks { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; clk_rc: clk-rc { compatible = "fixed-clock"; @@ -61,6 +64,70 @@ clock-frequency = <32768>; clock-output-names = "xin32k"; }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_mclk_in"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_mclk_in"; + }; + + mclkin_sai2: mclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_mclk_in"; + }; + + mclkin_sai3: mclkin-sai3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_mclk_in"; + }; + + mclkout_sai0: mclkout-sai0@ff910004 { + compatible = "rockchip,clk-out"; + reg = <0xff910004 0x4>; + clocks = <&cru MCLK_OUT_SAI0>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <8>; + }; + + mclkout_sai1: mclkout-sai1@ff910004 { + compatible = "rockchip,clk-out"; + reg = <0xff910004 0x4>; + clocks = <&cru MCLK_OUT_SAI1>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <9>; + }; + + mclkout_sai2: mclkout-sai2@ff288004 { + compatible = "rockchip,clk-out"; + reg = <0xff288004 0x4>; + clocks = <&cru MCLK_OUT_SAI2>; + #clock-cells = <0>; + clock-output-names = "mclk_sai2_to_io"; + rockchip,bit-shift = <2>; + }; + + mclkout_sai3: mclkout-sai3@ff288004 { + compatible = "rockchip,clk-out"; + reg = <0xff288004 0x4>; + clocks = <&cru MCLK_OUT_SAI3>; + #clock-cells = <0>; + clock-output-names = "mclk_sai3_to_io"; + rockchip,bit-shift = <3>; + }; }; cpus { From 51f35c22f42e46f0c14e0ef03a2df3b1e32921c5 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Sat, 22 Jun 2024 09:25:46 +0800 Subject: [PATCH 136/191] ARM: dts: rockchip: rk3506: add cpu opp-table/core pvtpll/rockchip-system-monitor Signed-off-by: Liang Chen Change-Id: I903ac99555d38d40e38c166fedda8b3d1687c4f6 --- arch/arm/boot/dts/rk3506.dtsi | 115 ++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index a41c39b8a114..3899fead90c6 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -128,6 +128,15 @@ clock-output-names = "mclk_sai3_to_io"; rockchip,bit-shift = <3>; }; + + pvtpll_core: pvtpll-core@ff840000 { + compatible = "rockchip,rk3506-core-pvtpll", "syscon"; + reg = <0xff840000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_core_pvtpll"; + assigned-clocks = <&pvtpll_core>; + assigned-clock-rates = <1200000000>; + }; }; cpus { @@ -139,6 +148,8 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@f01 { @@ -146,6 +157,8 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@f02 { @@ -153,6 +166,102 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,pvtm-voltage-sel = < + 0 1584 0 + 1585 1619 1 + 1620 1654 2 + 1655 1689 3 + 1690 1724 4 + 1725 1759 5 + 1760 1794 6 + 1795 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <500>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <1000000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&pvtpll_core>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000 850000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <887500 887500 1000000>; + opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <862500 862500 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>; + opp-microvolt-L7 = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <937500 937500 1000000>; + opp-microvolt-L0 = <937500 937500 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <912500 912500 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <887500 887500 1000000>; + opp-microvolt-L5 = <875000 875000 1000000>; + opp-microvolt-L6 = <862500 862500 1000000>; + opp-microvolt-L7 = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <962500 962500 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <937500 937500 1000000>; + opp-microvolt-L4 = <925000 925000 1000000>; + opp-microvolt-L5 = <912500 912000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <887500 887500 1000000>; + clock-latency-ns = <40000>; }; }; @@ -175,6 +284,12 @@ method = "smc"; }; + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + }; + thermal_zones: thermal-zones { soc_thermal: soc-thermal { polling-delay-passive = <20>; /* milliseconds */ From 64d3411010441e3a87a13f9d47400e449320ef49 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 11:00:56 +0800 Subject: [PATCH 137/191] ARM: dts: rockchip: rk3506: include gpio dt-bindings Change-Id: Id04661a23ca63db686cf24f25aac31420fcf2779 Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 3899fead90c6..de524f9b320b 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include From 25467135522181b2585b5e1f489c05e6a56374e7 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Fri, 21 Jun 2024 10:46:49 +0800 Subject: [PATCH 138/191] ARM: dts: rockchip: rk3506: add audio_adc node Change-Id: Ia6ba417eb4ca972b8ec322b63ec92e72b1dbd0cb Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3506.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index de524f9b320b..e62e6c611b17 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -1032,6 +1032,17 @@ status = "disabled"; }; + audio_codec: audio-codec@ff4f8000 { + compatible = "rockchip,rk3506-codec"; + reg = <0xff4f8000 0x1000>; + #sound-dai-cells = <0>; + clocks = <&cru PCLK_AUDIO_ADC>, <&cru MCLK_AUDIO_ADC>; + clock-names = "pclk", "mclk"; + resets = <&cru SRST_M_AUDIO_ADC>; + reset-names = "rst"; + status = "disabled"; + }; + gic: interrupt-controller@ff581000 { compatible = "arm,gic-400"; reg = <0xff581000 0x1000>, From 314df85f9a1550a0863062659c78652f53e8e2d6 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Mon, 24 Jun 2024 16:20:01 +0800 Subject: [PATCH 139/191] ARM: dts: Add dsi support for rk3506 Change-Id: I0c78c0f2ea998621a800cf63c3413e38bdb77fdb Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3506.dtsi | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index e62e6c611b17..0f4acac2a111 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -1071,6 +1071,11 @@ reg = <0>; remote-endpoint = <&rgb_in_vop>; }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; }; }; @@ -1084,6 +1089,38 @@ status = "disabled"; }; + dsi: dsi@ff640000 { + compatible = "rockchip,rk3506-mipi-dsi"; + reg = <0xff640000 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSI_HOST>; + clock-names = "pclk"; + resets = <&cru SRST_P_DSI_HOST>; + reset-names = "apb"; + phys = <&dsi_dphy>; + phy-names = "dphy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + dsi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_dsi>; + status = "disabled"; + }; + }; + }; + }; + tsadc: tsadc@ff650000 { compatible = "rockchip,rk3506-tsadc"; reg = <0xff650000 0x400>; @@ -1107,6 +1144,21 @@ reg = <0xff660000 0x10000>; }; + dsi_dphy: phy@ff670000 { + compatible = "rockchip,rk3506-dsi-dphy"; + reg = <0xff670000 0x10000>, + <0xff640000 0x10000>; + reg-names = "phy", "host"; + clocks = <&cru CLK_REF_DPHY_TOP>, + <&cru PCLK_DPHY>, <&cru PCLK_DSI_HOST>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_DPHY>; + reset-names = "apb"; + #phy-cells = <0>; + status = "disabled"; + }; + crypto: crypto@ff700000 { compatible = "rockchip,crypto-v4"; reg = <0xff700000 0x2000>; From 2ab5a1deba40dd1d0d662a3e8abd36b848c148a1 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 27 Jun 2024 11:55:02 +0800 Subject: [PATCH 140/191] ARM: dts: rockchip: rk3506: add route nodes for display-subsystem Change-Id: I86350f165544598184c8d0914579e2c50a0fbdda Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 0f4acac2a111..146758da0ed2 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -278,6 +278,26 @@ compatible = "rockchip,display-subsystem"; ports = <&vop_out>; status = "disabled"; + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_rgb>; + }; + }; }; psci { From f95a2f7e84a6258293f1c1c6bc6bbb0bb7f56b38 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 18 Jun 2024 21:45:03 +0800 Subject: [PATCH 141/191] ARM: dts: rockchip: rk3506: Add otp/cpuinfo device node Change-Id: I5665185533d3ce68dbc0a2c8d3dac20a3ebd2a7d Signed-off-by: Finley Xiao --- arch/arm/boot/dts/rk3506.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 146758da0ed2..1af6cbfdc591 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -274,6 +274,12 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; }; + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vop_out>; @@ -1052,6 +1058,37 @@ status = "disabled"; }; + otp: otp@ff4f0000 { + compatible = "rockchip,rk3506-otp"; + reg = <0xff4f0000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>; + clock-names = "usr", "sbpi", "apb"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, + <&cru SRST_P_OTPC_NS>; + reset-names = "usr", "sbpi", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1e { + reg = <0x1e 0x1>; + }; + log_leakage: log-leakage@1f { + reg = <0x1f 0x1>; + }; + }; + audio_codec: audio-codec@ff4f8000 { compatible = "rockchip,rk3506-codec"; reg = <0xff4f8000 0x1000>; From 7b10e9390a3d0f23bcee994839cc4c754e119ac9 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 28 Jun 2024 14:25:48 +0800 Subject: [PATCH 142/191] ARM: dts: rockchip: rk3506: add clock configs for vop Change-Id: Ifd7b239c7d8ca5164e92ccb99de08abab7bce775 Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 1af6cbfdc591..207e67f4608e 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -1118,6 +1118,8 @@ reg-names = "regs"; rockchip,grf = <&grf>; interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; status = "disabled"; vop_out: port { From d472356882c57196a1c76ec5a62cd54d8a0938db Mon Sep 17 00:00:00 2001 From: Xuhui Lin Date: Fri, 28 Jun 2024 15:15:41 +0800 Subject: [PATCH 143/191] ARM: dts: rockchip: rk3506: Add reboot_mode Change-Id: I5ab7ab915196e42d7a21c02c35aee1a816fcd0d3 Signed-off-by: Xuhui Lin --- arch/arm/boot/dts/rk3506.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 207e67f4608e..ffd5d6308cff 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -1533,8 +1534,22 @@ }; grf_pmu: syscon@ff910000 { - compatible = "rockchip,rk3506-grf-pmu", "syscon"; + compatible = "rockchip,rk3506-grf-pmu", "syscon", "simple-mfd"; reg = <0xff910000 0x4000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; }; pwm0_4ch_0: pwm@ff930000 { From 9590d65b63866e43ebdff9afb3ae50090334ac41 Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Mon, 1 Jul 2024 11:00:13 +0800 Subject: [PATCH 144/191] ARM: dts: rockchip: rk3506: Add gamma lut reg for vop Change-Id: I2f1f1a5aa1e186575e9f9a00b4db6118ca450ccb Signed-off-by: Chaoyi Chen --- arch/arm/boot/dts/rk3506.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index ffd5d6308cff..0660c5ad05a8 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -1115,8 +1115,8 @@ vop: vop@ff600000 { compatible = "rockchip,rk3506-vop"; - reg = <0xff600000 0x200>; - reg-names = "regs"; + reg = <0xff600000 0x200>, <0xff600a00 0x400>; + reg-names = "regs", "gamma_lut"; rockchip,grf = <&grf>; interrupts = ; clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; From 81053a10eb14da8525d2cc5e174f12aca33a7584 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 1 Jul 2024 22:22:54 +0800 Subject: [PATCH 145/191] ARM: dts: rockchip: rk3506: Add FLEXBUS fspi mode Change-Id: I808e9a8d3a3314728039b8b6caf647f4971aefa3 Signed-off-by: Jon Lin --- arch/arm/boot/dts/rk3506.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index 0660c5ad05a8..eda51eb0b9e4 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -38,6 +38,7 @@ spi0 = &spi0; spi1 = &spi1; spi2 = &fspi; + spi3 = &flexbus_fspi; }; clocks { @@ -1316,6 +1317,13 @@ rockchip,dfs = <16>; status = "disabled"; }; + + flexbus_fspi: fspi { + compatible = "rockchip,flexbus-fspi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dsmc_lb_slave: dsmc-lb-slave@ff880000 { From f70ddc95cb9095c9c5f697e69a0921c17531162a Mon Sep 17 00:00:00 2001 From: Cliff Chen Date: Tue, 2 Jul 2024 14:58:15 +0800 Subject: [PATCH 146/191] ARM: dts: rockchip: rk3506: Add label for arm-pmu Change-Id: If3080573f146600d07105131666e70650064c82d Signed-off-by: Cliff Chen --- arch/arm/boot/dts/rk3506.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3506.dtsi b/arch/arm/boot/dts/rk3506.dtsi index eda51eb0b9e4..ca19464fd3f9 100644 --- a/arch/arm/boot/dts/rk3506.dtsi +++ b/arch/arm/boot/dts/rk3506.dtsi @@ -268,7 +268,7 @@ }; }; - arm-pmu { + arm_pmu: arm-pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , , From f8297356f1c34f505cb052810e0aa7f991cac40f Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Tue, 18 Jun 2024 16:15:34 +0800 Subject: [PATCH 147/191] ARM: dts: rockchip: add evb1 dts for rk3506 Change-Id: I9658a980818b74eaa18a8a256e8b0acee7ed2aa9 Signed-off-by: Huibin Hong Signed-off-by: Jon Lin --- arch/arm/boot/dts/Makefile | 6 +++- arch/arm/boot/dts/rk3503g-evb1-v10.dts | 14 +++++++++ arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 35 +++++++++++++++++++++ arch/arm/boot/dts/rk3506b-evb1-v10.dts | 14 +++++++++ arch/arm/boot/dts/rk3506g-evb1-v10.dts | 14 +++++++++ arch/arm/boot/dts/rk3506g-iotest-v10.dts | 39 ++++++++++++++++++++++++ 6 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rk3503g-evb1-v10.dts create mode 100644 arch/arm/boot/dts/rk3506-evb1-v10.dtsi create mode 100644 arch/arm/boot/dts/rk3506b-evb1-v10.dts create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10.dts create mode 100644 arch/arm/boot/dts/rk3506g-iotest-v10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 714cb2f91a4d..26530380700d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1220,7 +1220,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3308bs-evb-amic-v11-aarch32.dtb \ rk3308bs-evb-dmic-pdm-v11-aarch32.dtb \ rk3308bs-evb-mipi-display-v11-aarch32.dtb \ - rk3308hs-voice-module-board-v10-aarch32.dtb + rk3308hs-voice-module-board-v10-aarch32.dtb \ + rk3503g-evb1-v10.dtb \ + rk3506b-evb1-v10.dtb \ + rk3506g-evb1-v10.dtb \ + rk3506g-iotest-v10.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ diff --git a/arch/arm/boot/dts/rk3503g-evb1-v10.dts b/arch/arm/boot/dts/rk3503g-evb1-v10.dts new file mode 100644 index 000000000000..1acccbddf758 --- /dev/null +++ b/arch/arm/boot/dts/rk3503g-evb1-v10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3503.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3503G(QFN88) EVB1 V10 Board"; + compatible = "rockchip,rk3503g-evb1-v10", "rockchip,rk3506"; +}; diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi new file mode 100644 index 000000000000..0a0e15c96fe0 --- /dev/null +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/ { + model = "Rockchip RK3506 EVB1 V10 Board"; + compatible = "rockchip,rk3506-evb1-v10", "rockchip,rk3506"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + }; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + diff --git a/arch/arm/boot/dts/rk3506b-evb1-v10.dts b/arch/arm/boot/dts/rk3506b-evb1-v10.dts new file mode 100644 index 000000000000..14d39f2fe3c7 --- /dev/null +++ b/arch/arm/boot/dts/rk3506b-evb1-v10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506B(BGA) EVB1 V10 Board"; + compatible = "rockchip,rk3506b-evb1-v10", "rockchip,rk3506"; +}; diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts new file mode 100644 index 000000000000..09585ae7828e --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506G(QFN128) EVB1 V10 Board"; + compatible = "rockchip,rk3506g-evb1-v10", "rockchip,rk3506"; +}; diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10.dts b/arch/arm/boot/dts/rk3506g-iotest-v10.dts new file mode 100644 index 000000000000..470e053a1deb --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-iotest-v10.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506.dtsi" + +/ { + model = "Rockchip RK3506 EVB1 V10 Board"; + compatible = "rockchip,rk3506-evb1-v10", "rockchip,rk3506"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + }; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + From 9d8b672f2955e798c9a309be59ceb1a12e2227e2 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Sat, 22 Jun 2024 09:26:23 +0800 Subject: [PATCH 148/191] ARM: dts: rockchip: rk3506-evb1: add regulator for cpu Signed-off-by: Liang Chen Change-Id: I843f9fe2b6ee820b2f9550210745a981e9504828 --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 0a0e15c96fe0..0ec384c544bd 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -19,6 +19,22 @@ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ interrupts = ; }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1207000>; + regulator-init-microvolt = <1011000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; }; &fspi { From 0100c2313267d8c34c702c9571d930acb895328f Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 11:00:23 +0800 Subject: [PATCH 149/191] ARM: dts: rockchip: rk3506-evb1: add backlight Change-Id: I3b92d745226c07b1fe15a2f278f4efb537a2eb8b Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 0ec384c544bd..bb512f719422 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -11,6 +11,46 @@ bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0_4ch_2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + fiq_debugger: fiq-debugger { compatible = "rockchip,fiq-debugger"; rockchip,serial-id = <0>; @@ -49,3 +89,9 @@ }; }; +&pwm0_4ch_2 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io3_pwm0_ch2>; + status = "okay"; +}; + From cac7affd78938e7ca937a6d29dc3cb8df63a9103 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 11:01:54 +0800 Subject: [PATCH 150/191] ARM: dts: rockchip: rk3506g-evb1: add rgb 1024x600p60 panel display board Change-Id: I5784be5f799394f171274ae3a816fa8a902af31e Signed-off-by: Damon Ding --- arch/arm/boot/dts/Makefile | 1 + .../rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dts | 80 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 26530380700d..828763f65fdd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1224,6 +1224,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3503g-evb1-v10.dtb \ rk3506b-evb1-v10.dtb \ rk3506g-evb1-v10.dtb \ + rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ rk3506g-iotest-v10.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dts b/arch/arm/boot/dts/rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dts new file mode 100644 index 000000000000..0e894b1fe598 --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506G(QFN128) EVB1 V10 Board + RK EVB VOP3 RGB24BIT DISPLAY Ext Board"; + compatible = "rockchip,rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T", "rockchip,rk3506"; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&q7050ith2641aa1t_timing>; + + q7050ith2641aa1t_timing: timing0 { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <24>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgb888_pins>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "okay"; +}; From 06332253b7f8070750a6a6802b20d802131afec2 Mon Sep 17 00:00:00 2001 From: Wesley Yao Date: Sat, 22 Jun 2024 15:10:20 +0800 Subject: [PATCH 151/191] ARM: dts: rockchip: rk3506-evb1: Add flexbus related nodes Change-Id: Ib993739cf4494ce089a2a6603ae4f41d935ccd83 Signed-off-by: Wesley Yao --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index bb512f719422..db00f4393e80 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd. */ +#include + / { model = "Rockchip RK3506 EVB1 V10 Board"; compatible = "rockchip,rk3506-evb1-v10", "rockchip,rk3506"; @@ -77,6 +79,33 @@ cpu-supply = <&vdd_arm>; }; +&flexbus { + rockchip,flexbus0-opmode = ; + rockchip,flexbus1-opmode = ; + status = "disabled"; +}; + +&flexbus_adc { + pinctrl-names = "default"; + /* 12bit ADC device */ + pinctrl-0 = <&flexbus1_clk_pins + &flexbus1_d0_pins &flexbus1_d1_pins &flexbus1_d2_pins &flexbus1_d3_pins + &flexbus1_d4_pins &flexbus1_d5_pins &flexbus1_d6_pins &flexbus1_d7_pins + &flexbus1_d8_pins &flexbus1_d9_pins &flexbus1_d10_pins &flexbus1_d11_pins>; + status = "disabled"; +}; + +&flexbus_dac { + pinctrl-names = "default"; + /* 14bit DAC device */ + pinctrl-0 = <&flexbus0_clk_pins + &flexbus0_d0_pins &flexbus0_d1_pins &flexbus0_d2_pins &flexbus0_d3_pins + &flexbus0_d4_pins &flexbus0_d5_pins &flexbus0_d6_pins &flexbus0_d7_pins + &flexbus0_d8_pins &flexbus0_d9_pins &flexbus0_d10_pins &flexbus0_d11_pins + &flexbus0_d12_pins &flexbus0_d13_pins>; + status = "disabled"; +}; + &fspi { status = "okay"; From f9a1201826a86dbeedb9c1ce21cb2383909ea712 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 15:27:43 +0800 Subject: [PATCH 152/191] ARM: dts: rockchip: rk3506g-evb1: add mcu 320x480p60 panel display board Change-Id: I3df401240f7b64e9a4e4ed6a09a781621c659258 Signed-off-by: Damon Ding --- arch/arm/boot/dts/Makefile | 1 + .../dts/rk3506g-evb1-v10-mcu-k350c4516t.dts | 219 ++++++++++++++++++ 2 files changed, 220 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10-mcu-k350c4516t.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 828763f65fdd..0d533e9ba530 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1224,6 +1224,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3503g-evb1-v10.dtb \ rk3506b-evb1-v10.dtb \ rk3506g-evb1-v10.dtb \ + rk3506g-evb1-v10-mcu-k350c4516t.dtb \ rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ rk3506g-iotest-v10.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10-mcu-k350c4516t.dts b/arch/arm/boot/dts/rk3506g-evb1-v10-mcu-k350c4516t.dts new file mode 100644 index 000000000000..68de05074538 --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10-mcu-k350c4516t.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506G(QFN128) EVB1 V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; + compatible = "rockchip,rk3506g-evb1-v10-mcu-k350c4516t", "rockchip,rk3506"; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + pinctrl-names = "default"; + /* + * rgb3x8_rgb2x8_m0_pins/rgb3x8_rgb2x8_m1_pins for RGB3x8(8bit)/RGB565(8bit) + * rgb565_pins for RGB565(16bit) + */ + pinctrl-0 = <&rgb565_pins>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + * MEDIA_BUS_FMT_RGB565_2X8_LE for RGB565(8bit) + */ + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 55 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit)/RGB565(8bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * 10 (30hz) for RGB3x8(8bit) + * 70 (45hz) for RGB565(8bit) + * a0 (60hz) for RGB565(16bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 5226750 for frame rate 30Hz + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <10453500>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + mcu-timing { + mcu-pix-total = <5>; + mcu-cs-pst = <1>; + mcu-cs-pend = <4>; + mcu-rw-pst = <2>; + mcu-rw-pend = <3>; + + mcu-hold-mode = <0>; + }; +}; From 640bfe0e25e98e86b133f4aad9b92fba83c2f64f Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 16:01:04 +0800 Subject: [PATCH 153/191] ARM: dts: rockchip: rk3506g-evb1: add sii9022 bt1120/bt656 to hdmi board Change-Id: I90efe34d60f02ba5d6f8ffedf52cf66c5ea77b96 Signed-off-by: Damon Ding --- arch/arm/boot/dts/Makefile | 1 + ...k3506g-evb1-v10-sii9022-bt1120-to-hdmi.dts | 91 +++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0d533e9ba530..61500c7395f7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1226,6 +1226,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3506g-evb1-v10.dtb \ rk3506g-evb1-v10-mcu-k350c4516t.dtb \ rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ + rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dtb \ rk3506g-iotest-v10.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dts b/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dts new file mode 100644 index 000000000000..5ac3b9d4e40a --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506G(QFN128) EVB1 V10 Board + RK EVB EXT DisplayBoard SII9022A BT1120toHDMI V10"; + compatible = "rockchip,rk3506g-evb1-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3506"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io4_i2c2_scl &rm_io5_i2c2_sda>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi>; + interrupt-parent = <&gpio0>; + interrupts = ; + reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + /* + * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120 + * MEDIA_BUS_FMT_UYVY8_2X8 for bt656 + */ + bus-format = ; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&pinctrl { + sii902x { + sii902x_hdmi: sii902x-hdmi { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + /* + * bt1120_pins for bt1120 + * bt656_m0_pins/bt656_m1_pins for bt656 + */ + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "okay"; +}; From 4fa220396bd9274c91a9afce060eb0976d4596e6 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Sat, 22 Jun 2024 16:28:35 +0800 Subject: [PATCH 154/191] ARM: dts: rockchip: rk3506g-evb1: add sii9022 rgb2hdmi board Change-Id: I5d5fda731cc4658efc4822c83a429e64c4f47bce Signed-off-by: Damon Ding --- arch/arm/boot/dts/Makefile | 1 + .../dts/rk3506g-evb1-v10-sii9022-rgb2hdmi.dts | 82 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-rgb2hdmi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 61500c7395f7..ad3f9e299ce5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1227,6 +1227,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3506g-evb1-v10-mcu-k350c4516t.dtb \ rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dtb \ + rk3506g-evb1-v10-sii9022-rgb2hdmi.dtb \ rk3506g-iotest-v10.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-rgb2hdmi.dts b/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-rgb2hdmi.dts new file mode 100644 index 000000000000..25d2f2ef2e1d --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10-sii9022-rgb2hdmi.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rk3506.dtsi" +#include "rk3506-evb1-v10.dtsi" + +/ { + model = "Rockchip RK3506G(QFN128) EVB1 V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board"; + compatible = "rockchip,rk3506g-evb1-v10-sii9022-rgb2hdmi", "rockchip,rk3506"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&rm_io4_i2c2_scl &rm_io5_i2c2_sda>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi>; + interrupt-parent = <&gpio0>; + interrupts = ; + reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + bus-format = ; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&pinctrl { + sii902x { + sii902x_hdmi: sii902x-hdmi { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgb888_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vop { + status = "okay"; +}; + +&route_rgb { + status = "okay"; +}; From 3d0db8cafe91f40f9d752121206e00aa8ebeafb9 Mon Sep 17 00:00:00 2001 From: shengfei Xu Date: Wed, 26 Jun 2024 15:33:33 +0800 Subject: [PATCH 155/191] ARM: dts: rockchip: rk3506-evb1: Add power tree Change-Id: I98abe17b71cc85cbaa03bf814753a2f0ca925c8a Signed-off-by: shengfei Xu --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 73 ++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index db00f4393e80..3f267bdf213f 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -62,6 +62,53 @@ interrupts = ; }; + vcc12v_dc: vcc12v-dc { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dc>; + }; + + vcc3v3_stb: vcc3v3-stb { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_stb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_stb>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + vdd_arm: vdd-arm { compatible = "pwm-regulator"; pwms = <&pwm0_4ch_0 0 5000 1>; @@ -72,6 +119,20 @@ regulator-always-on; regulator-boot-on; regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + }; + + vcc0v9_stb: vcc0v9-stb { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_1 0 5000 1>; + regulator-name = "vcc0v9_stb"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; }; }; @@ -118,6 +179,18 @@ }; }; +&pwm0_4ch_0 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io21_pwm0_ch0>; + status = "okay"; +}; + +&pwm0_4ch_1 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io20_pwm0_ch1>; + status = "okay"; +}; + &pwm0_4ch_2 { pinctrl-names = "active"; pinctrl-0 = <&rm_io3_pwm0_ch2>; From fa7c82ad7e937b2a699d118c3c2233c7c09f1bce Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Wed, 26 Jun 2024 16:42:22 +0800 Subject: [PATCH 156/191] ARM: dts: rockchip: rk3506g-iotest: add pwm test config Use rm_io8 ~ rm_io19 pins by default. add biphasic counter iomux configs for pwm test. Change-Id: If229ec416d9edb44015556953404bb4cfb9ec7b2 Signed-off-by: Damon Ding --- .../arm/boot/dts/rk3506g-iotest-pwm-test.dtsi | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-iotest-pwm-test.dtsi diff --git a/arch/arm/boot/dts/rk3506g-iotest-pwm-test.dtsi b/arch/arm/boot/dts/rk3506g-iotest-pwm-test.dtsi new file mode 100644 index 000000000000..056729b46233 --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-iotest-pwm-test.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/ { + pwm_rockchip_test: pwm-rockchip-test { + compatible = "pwm-rockchip-test"; + pwms = <&pwm0_4ch_0 0 25000 0>, + <&pwm0_4ch_1 0 25000 0>, + <&pwm0_4ch_2 0 25000 0>, + <&pwm0_4ch_3 0 25000 0>, + <&pwm1_8ch_0 0 25000 0>, + <&pwm1_8ch_1 0 25000 0>, + <&pwm1_8ch_2 0 25000 0>, + <&pwm1_8ch_3 0 25000 0>, + <&pwm1_8ch_4 0 25000 0>, + <&pwm1_8ch_5 0 25000 0>, + <&pwm1_8ch_6 0 25000 0>, + <&pwm1_8ch_7 0 25000 0>; + pwm-names = "pwm0_0", + "pwm0_1", + "pwm0_2", + "pwm0_3", + "pwm1_0", + "pwm1_1", + "pwm1_2", + "pwm1_3", + "pwm1_4", + "pwm1_5", + "pwm1_6", + "pwm1_7"; + }; +}; + +/* use GPIO0_B0 ~ GPIO0_C3(rm_io8 ~ rm_io19) by default */ +&pwm0_4ch_0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io8_pwm0_ch0>; + assigned-clocks = <&cru CLK_PWM0>; + assigned-clock-rates = <100000000>; +}; + +&pwm0_4ch_1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io9_pwm0_ch1>; + assigned-clocks = <&cru CLK_PWM0>; + assigned-clock-rates = <100000000>; +}; + +&pwm0_4ch_2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io10_pwm0_ch2>; + assigned-clocks = <&cru CLK_PWM0>; + assigned-clock-rates = <100000000>; +}; + +&pwm0_4ch_3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io11_pwm0_ch3>; + assigned-clocks = <&cru CLK_PWM0>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io12_pwm1_ch0>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io13_pwm1_ch1>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io14_pwm1_ch2>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io15_pwm1_ch3>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_4 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io16_pwm1_ch4>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_5 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io17_pwm1_ch5>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +&pwm1_8ch_6 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io18_pwm1_ch6>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; + +#ifdef BIPHASIC_COUNTER_TEST +&pwm1_8ch_0 { + pinctrl-0 = <&rm_io12_pwm1_bip_cntr_a0 &rm_io0_pwm1_bip_cntr_b0>; +}; + +&pwm1_8ch_1 { + pinctrl-0 = <&rm_io13_pwm1_bip_cntr_a1 &rm_io1_pwm1_bip_cntr_b1>; +}; + +&pwm1_8ch_2 { + pinctrl-0 = <&rm_io14_pwm1_bip_cntr_a2 &rm_io2_pwm1_bip_cntr_b2>; +}; + +&pwm1_8ch_3 { + pinctrl-0 = <&rm_io15_pwm1_bip_cntr_a3 &rm_io3_pwm1_bip_cntr_b3>; +}; + +&pwm1_8ch_4 { + pinctrl-0 = <&rm_io16_pwm1_bip_cntr_a4 &rm_io4_pwm1_bip_cntr_b4>; +}; + +&pwm1_8ch_5 { + pinctrl-0 = <&rm_io17_pwm1_bip_cntr_a5 &rm_io5_pwm1_bip_cntr_b5>; +}; + +&pwm1_8ch_6 { + pinctrl-0 = <&rm_io18_pwm1_ch6 &rm_io6_pwm1_ch7>; +}; +#else +&pwm1_8ch_7 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&rm_io19_pwm1_ch7>; + assigned-clocks = <&cru CLK_PWM1>; + assigned-clock-rates = <100000000>; +}; +#endif From 592f3c28e52193db683cb676bbf904c79cc777fc Mon Sep 17 00:00:00 2001 From: shengfei Xu Date: Wed, 26 Jun 2024 17:34:12 +0800 Subject: [PATCH 157/191] ARM: dts: rockchip: rk3506-iotest: Add power tree Change-Id: I850f6d88cb170053b051c75d5214d1b373a994b3 Signed-off-by: shengfei Xu --- arch/arm/boot/dts/rk3506g-iotest-v10.dts | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10.dts b/arch/arm/boot/dts/rk3506g-iotest-v10.dts index 470e053a1deb..42bda06d6328 100644 --- a/arch/arm/boot/dts/rk3506g-iotest-v10.dts +++ b/arch/arm/boot/dts/rk3506g-iotest-v10.dts @@ -23,6 +23,79 @@ rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ interrupts = ; }; + + vcc12v_dc: vcc12v-dc { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dc>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_sys>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1207000>; + regulator-init-microvolt = <1011000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + }; + + vcc0v9_stb: vcc0v9-stb { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_1 0 5000 1>; + regulator-name = "vcc0v9_stb"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + }; }; &fspi { @@ -37,3 +110,14 @@ }; }; +&pwm0_4ch_0 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io21_pwm0_ch0>; + status = "okay"; +}; + +&pwm0_4ch_1 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io20_pwm0_ch1>; + status = "okay"; +}; From 456adf4ca225b1e6235f18ee3c34b6576ec96d6e Mon Sep 17 00:00:00 2001 From: Yao Xiao Date: Thu, 27 Jun 2024 10:12:02 +0800 Subject: [PATCH 158/191] ARM: dts: rk3506-evb1-10: add wifibt node Change-Id: I139dcd47c67bbe5af0cf3160a1d52135fb6598d0 Signed-off-by: Yao Xiao --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 3f267bdf213f..47ba31388cde 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -134,6 +134,40 @@ regulator-settling-time-up-us = <250>; pwm-supply = <&vcc_sys>; }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart5m0_rtsn_pins>; + pinctrl-1 = <&uart5_gpios>; + BT,power_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + wifi_chip_type = "cyw43455"; + WIFI,host_wake_irq = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; &cpu0 { @@ -179,6 +213,39 @@ }; }; +&mmc { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart5_gpios: uart5-gpios { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + &pwm0_4ch_0 { pinctrl-names = "active"; pinctrl-0 = <&rm_io21_pwm0_ch0>; @@ -197,3 +264,7 @@ status = "okay"; }; +&uart5 { + pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins>; + status = "okay"; +}; From 2eb9474a679c9b9d15069c778c553bb42af39dfb Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 27 Jun 2024 12:00:06 +0800 Subject: [PATCH 159/191] ARM: dts: rockchip: rk3506-evb1: enable display_subsystem and backlight Change-Id: I5059f6db3b0a3e307d17a309a7c1f1df66948ae9 Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 47ba31388cde..7f464805344a 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -51,6 +51,7 @@ 248 249 250 251 252 253 254 255 >; default-brightness-level = <200>; + status = "okay"; }; fiq_debugger: fiq-debugger { @@ -174,6 +175,10 @@ cpu-supply = <&vdd_arm>; }; +&display_subsystem { + status = "okay"; +}; + &flexbus { rockchip,flexbus0-opmode = ; rockchip,flexbus1-opmode = ; From 7f129e1b914b32271744112c3f2c875822f474b6 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Mon, 24 Jun 2024 15:50:03 +0800 Subject: [PATCH 160/191] ARM: dts: rockchip: add usb nodes for rk3506 evb Change-Id: I128f7de56d9485361a0ca16bb7393029b5c7f7c1 Signed-off-by: Jianwei Zheng --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 9 +++++++ arch/arm/boot/dts/rk3506b-evb1-v10.dts | 36 ++++++++++++++++++++++++++ arch/arm/boot/dts/rk3506g-evb1-v10.dts | 36 ++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 7f464805344a..3394d60efd2d 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -273,3 +273,12 @@ pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins>; status = "okay"; }; + +&usb20_otg0 { + status = "okay"; +}; + +&usb20_otg1 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3506b-evb1-v10.dts b/arch/arm/boot/dts/rk3506b-evb1-v10.dts index 14d39f2fe3c7..279fba2d3597 100644 --- a/arch/arm/boot/dts/rk3506b-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506b-evb1-v10.dts @@ -11,4 +11,40 @@ / { model = "Rockchip RK3506B(BGA) EVB1 V10 Board"; compatible = "rockchip,rk3506b-evb1-v10", "rockchip,rk3506"; + + vcc5v0_otg0: vcc5v0-otg0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg0_en>; + }; + + vcc5v0_otg1: vcc5v0-otg1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg1"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg1_en>; + }; +}; + +&pinctrl { + usb { + vcc5v0_otg0_en: vcc5v0-otg0-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg1_en: vcc5v0-otg1-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index 09585ae7828e..e48e74c970b4 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -11,4 +11,40 @@ / { model = "Rockchip RK3506G(QFN128) EVB1 V10 Board"; compatible = "rockchip,rk3506g-evb1-v10", "rockchip,rk3506"; + + vcc5v0_otg0: vcc5v0-otg0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg0_en>; + }; + + vcc5v0_otg1: vcc5v0-otg1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg1"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg1_en>; + }; +}; + +&pinctrl { + usb { + vcc5v0_otg0_en: vcc5v0-otg0-en { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg1_en: vcc5v0-otg1-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; From 15cda1fc3af30ca695e0e9a0f094a99087063fd6 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Wed, 26 Jun 2024 17:57:10 +0800 Subject: [PATCH 161/191] ARM: dts: rockchip: rk3506-evb1: add dsi support dsi display timing 720x1280@60 with 2 lanes, data rate 850 Mhz Change-Id: I5e351c3a4ec90e18ea2fb361ada544e88fb5c7c9 Signed-off-by: Hongming Zou Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 272 +++++++++++++++++++++++++ arch/arm/boot/dts/rk3506g-evb1-v10.dts | 27 +++ 2 files changed, 299 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 3394d60efd2d..db39b88f4cc7 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd. */ +#include #include / { @@ -179,6 +180,277 @@ status = "okay"; }; +&dsi { + status = "disabled"; + rockchip,lane-rate = <850>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + prepare-delay-ms = <5>; + reset-delay-ms = <1>; + init-delay-ms = <80>; + disable-delay-ms = <10>; + unprepare-delay-ms = <5>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 55 7b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 32 + 15 00 02 b2 00 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + 15 00 02 b6 02 + 15 00 02 b7 03 + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <48>; + hsync-len = <8>; + hback-porch = <52>; + vfront-porch = <16>; + vsync-len = <6>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi_in_vop { + status = "disabled"; +}; + &flexbus { rockchip,flexbus0-opmode = ; rockchip,flexbus1-opmode = ; diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index e48e74c970b4..cc503b6b01a7 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -12,6 +12,17 @@ model = "Rockchip RK3506G(QFN128) EVB1 V10 Board"; compatible = "rockchip,rk3506g-evb1-v10", "rockchip,rk3506"; + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc5v0_otg0: vcc5v0-otg0-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_otg0"; @@ -37,6 +48,22 @@ }; }; +&dsi { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi_in_vop { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; +}; + &pinctrl { usb { vcc5v0_otg0_en: vcc5v0-otg0-en { From 7e96a97da36e0dbad504ec6a1106fb94f2b81007 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 28 Jun 2024 14:27:18 +0800 Subject: [PATCH 162/191] ARM: dts: rockchip: rk3506-evb1: enable vop Change-Id: I7affead0236d18bb39a268378ea84db95acbd138 Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index db39b88f4cc7..4fac87442fd1 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -554,3 +554,7 @@ dr_mode = "host"; status = "okay"; }; + +&vop { + status = "okay"; +}; From 4a1e5235e920d6e929d4fd127f1619f8094ada09 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 28 Jun 2024 17:01:06 +0800 Subject: [PATCH 163/191] ARM: dts: rockchip: Add gmac0 support for rk3506-evb1 Change-Id: I5aab59a81f2495704733e1d4a711095d277b836a Signed-off-by: David Wu --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 4fac87442fd1..4a439fd286d5 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -490,6 +490,31 @@ }; }; +&gmac0 { + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð_rmii0_miim_pins + ð_rmii0_tx_bus2_pins + ð_rmii0_rx_bus2_pins + ð_rmii0_clk_pins>; + + phy-handle = <&rmii_phy0>; + status = "okay"; +}; + +&mdio0 { + rmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + &mmc { bus-width = <4>; cap-sd-highspeed; From 8b5191780ea110c46e1f1b304c6d0d0841b2553e Mon Sep 17 00:00:00 2001 From: Ye Zhang Date: Fri, 28 Jun 2024 17:00:47 +0800 Subject: [PATCH 164/191] ARM: dts: rockchip: rk3506-evb1-v10: Enable tsadc node Signed-off-by: Ye Zhang Change-Id: I7f8b852b4f96c3a595941e156ede310abad421f0 --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 4a439fd286d5..c94f99ee3517 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -566,6 +566,10 @@ status = "okay"; }; +&tsadc { + status = "okay"; +}; + &uart5 { pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins>; status = "okay"; From 7c31bea0de4e445198bbb08fde6c8e09f414281d Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Sat, 29 Jun 2024 08:52:27 +0800 Subject: [PATCH 165/191] ARM: dts: rockchip: Add mmc for rk3506g-iotest Signed-off-by: Shawn Lin Change-Id: I2e01d243f475642a53cd73a99b0b47c1b8290613 --- arch/arm/boot/dts/rk3506g-iotest-v10.dts | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10.dts b/arch/arm/boot/dts/rk3506g-iotest-v10.dts index 42bda06d6328..6b9c091147c5 100644 --- a/arch/arm/boot/dts/rk3506g-iotest-v10.dts +++ b/arch/arm/boot/dts/rk3506g-iotest-v10.dts @@ -53,6 +53,28 @@ vin-supply = <&vcc_sys>; }; + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + states = <3300000 1 + 1800000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_volt>; + }; + vcc_1v8: vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; @@ -110,6 +132,52 @@ }; }; +&mmc { + /* For SDMMC */ + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins &sdmmc_det>; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc3v3_sd>; + + /* For eMMC + * no-sdio; + * no-sd; + * cap-mmc-highspeed; + * cap-sd-highspeed; + * non-removable; + * mmc-hs200-1_8v; + * pinctrl-names = "default"; + * pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins>; + * vqmmc-supply = <&vccio_sd>; + * vmmc-supply = <&vcc3v3_sd>; + */ + status = "okay"; +}; + +&pinctrl { + sdmmc { + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc_volt: sdmmc-volt { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + &pwm0_4ch_0 { pinctrl-names = "active"; pinctrl-0 = <&rm_io21_pwm0_ch0>; From 2a1131cbf20e206849b288de6e4587d1589cb9a0 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Sat, 29 Jun 2024 08:53:33 +0800 Subject: [PATCH 166/191] ARM: dts: rockchip: rk3506g-iotest: set rootfs parameter Signed-off-by: Shawn Lin Change-Id: Icba37e99735d4aa4a3af622039cb89dfefd49798 --- arch/arm/boot/dts/rk3506g-iotest-v10.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10.dts b/arch/arm/boot/dts/rk3506g-iotest-v10.dts index 6b9c091147c5..4a24de1217f3 100644 --- a/arch/arm/boot/dts/rk3506g-iotest-v10.dts +++ b/arch/arm/boot/dts/rk3506g-iotest-v10.dts @@ -12,7 +12,7 @@ compatible = "rockchip,rk3506-evb1-v10", "rockchip,rk3506"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; }; fiq_debugger: fiq-debugger { From d45c23e59736d1d1dd90c1f244163002653e32f4 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 28 Jun 2024 16:13:53 +0800 Subject: [PATCH 167/191] ARM: dts: rk3506-evb1: Add es8388 sound node Signed-off-by: Sugar Zhang Change-Id: I06111e12849ad9eb5ac93dcb17c02dfc7ceaf9a9 --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index c94f99ee3517..fd14659d244b 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -55,6 +55,29 @@ status = "okay"; }; + es8388_sound: es8388-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + spk-con-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,pre-power-on-delay-ms = <30>; + rockchip,post-power-down-delay-ms = <40>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai1>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Speaker", "LOUT1", + "Speaker", "ROUT1", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Main Mic", + "RINPUT2", "Main Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctrl>; + }; + fiq_debugger: fiq-debugger { compatible = "rockchip,fiq-debugger"; rockchip,serial-id = <0>; @@ -508,6 +531,26 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io13_i2c0_scl + &rm_io14_i2c0_sda>; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io8_sai1_mclk>; + }; +}; + &mdio0 { rmii_phy0: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -535,6 +578,12 @@ }; }; + speaker { + spk_ctrl: spk-ctrl { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { uart5_gpios: uart5-gpios { rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -566,6 +615,15 @@ status = "okay"; }; +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io9_sai1_sclk + &rm_io10_sai1_lrck + &rm_io11_sai1_sdi + &rm_io12_sai1_sdo0>; +}; + &tsadc { status = "okay"; }; From 553541f2193c33e4de9a5b215ffc8f574af9adcd Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 29 Jun 2024 14:32:28 +0800 Subject: [PATCH 168/191] ARM: dts: rockchip: add can pinctrl for rk3506 evb1 Change-Id: I055a2886666d5b675f695a4cbb7e1e63b2531d2d Signed-off-by: Elaine Zhang --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index fd14659d244b..e3678d28310f 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -195,6 +195,14 @@ }; }; +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + pinctrl-0 = <&rm_io30_can0_tx &rm_io31_can0_rx>; + pinctrl-names = "default"; + status = "disabled"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; From 3baf7a68c28098394ca21abb32d9026aaa9c5d4a Mon Sep 17 00:00:00 2001 From: Zain Wang Date: Fri, 28 Jun 2024 10:11:08 +0800 Subject: [PATCH 169/191] ARM: dts: rockchip: rk3506-evb1: add keys node Change-Id: I1d38a566087545b5d635bb1659c2da7835129405 Signed-off-by: Zain Wang --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 57 ++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index e3678d28310f..d48c91e963b1 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include / { @@ -14,6 +15,38 @@ bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; }; + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <16000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <420000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <800000>; + }; + + esc-key { + label = "esc"; + linux,code = ; + press-threshold-microvolt = <1200000>; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm0_4ch_2 0 25000 0>; @@ -87,6 +120,19 @@ interrupts = ; }; + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_wake_up>; + + wake_up: wake-up { + label = "Wake-up"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + vcc12v_dc: vcc12v-dc { compatible = "regulator-fixed"; regulator-name = "vcc12v_dc"; @@ -580,6 +626,12 @@ }; &pinctrl { + gpio-keys { + key_wake_up: key-wake-up { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -632,6 +684,11 @@ &rm_io12_sai1_sdo0>; }; +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + &tsadc { status = "okay"; }; From 559c1c2a0ba7e3564c2091541e9b67a0786322c9 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Sun, 30 Jun 2024 12:06:26 +0800 Subject: [PATCH 170/191] ARM: dts: rk3506-evb1: Add gt1x node Change-Id: I2329e58a5ebea79a16bbef302f14e6f2ff2c0883 Signed-off-by: Hongming Zou Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/rk3506g-evb1-v10.dts | 6 ++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index d48c91e963b1..c09b0a05953a 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -605,6 +605,22 @@ }; }; +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io4_i2c2_scl &rm_io5_i2c2_sda>; + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + gtp_ics_slot_report; + goodix,rst-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; +}; + &mdio0 { rmii_phy0: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index cc503b6b01a7..7203584edd5f 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -17,6 +17,7 @@ enable-active-high; gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; regulator-name = "vcc3v3_lcd_n"; + regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; @@ -64,6 +65,11 @@ power-supply = <&vcc3v3_lcd_n>; }; +>1x { + power-supply = <&vcc3v3_lcd_n>; + status = "okay"; +}; + &pinctrl { usb { vcc5v0_otg0_en: vcc5v0-otg0-en { From 956afd1c168d107199ad8afe12873916bcea02cd Mon Sep 17 00:00:00 2001 From: Yao Xiao Date: Fri, 28 Jun 2024 20:19:42 +0800 Subject: [PATCH 171/191] ARM: dts: rk3506-evb1-v10: add pinctrl for sdio Change-Id: I79ab611626a297dfe42a49d5c2748109eca97800 Signed-off-by: Yao Xiao --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index c09b0a05953a..f8b60ad7bd7a 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -633,6 +633,8 @@ cap-sd-highspeed; no-sd; no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins>; ignore-pm-notify; keep-power-in-suspend; non-removable; From 4f7aeede9a2f9800bcd05c4f552727c60d4957aa Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sat, 29 Jun 2024 17:42:33 +0800 Subject: [PATCH 172/191] ARM: dts: rockchip: rk3506g-iotest: add pdm_mic_array card node Change-Id: Id3ccdac01b29695444f10acf638e18a00dd98e17 Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3506g-iotest-v10.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10.dts b/arch/arm/boot/dts/rk3506g-iotest-v10.dts index 4a24de1217f3..f4112dd32dda 100644 --- a/arch/arm/boot/dts/rk3506g-iotest-v10.dts +++ b/arch/arm/boot/dts/rk3506g-iotest-v10.dts @@ -24,6 +24,23 @@ interrupts = ; }; + pdmics: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + vcc12v_dc: vcc12v-dc { compatible = "regulator-fixed"; regulator-name = "vcc12v_dc"; @@ -161,6 +178,10 @@ status = "okay"; }; +&pdm { + status = "okay"; +}; + &pinctrl { sdmmc { /omit-if-no-ref/ From 2d159fe01910b352321a66cfd47d8c4251801623 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sat, 29 Jun 2024 17:45:32 +0800 Subject: [PATCH 173/191] ARM: dts: rockchip: rk3506g-iotest-pdm: for pdm test Change-Id: I390408b4ee527cd3db46ee6ab665205c78b86eab Signed-off-by: Jason Zhu --- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/rk3506g-iotest-v10-pdm.dts | 22 ++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rk3506g-iotest-v10-pdm.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ad3f9e299ce5..3eec4d02c842 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1228,7 +1228,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dtb \ rk3506g-evb1-v10-sii9022-rgb2hdmi.dtb \ - rk3506g-iotest-v10.dtb + rk3506g-iotest-v10.dtb \ + rk3506g-iotest-v10-pdm.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ diff --git a/arch/arm/boot/dts/rk3506g-iotest-v10-pdm.dts b/arch/arm/boot/dts/rk3506g-iotest-v10-pdm.dts new file mode 100644 index 000000000000..4506d2a0d0b0 --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-iotest-v10-pdm.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506g-iotest-v10.dts" + +&pdm_mic_array { + status = "okay"; +}; + +&pdm { + status = "okay"; + pinctrl-0 = <&rm_io24_pdm_clk0 + &rm_io25_pdm_clk1 + &rm_io26_pdm_sdi0 + &rm_io27_pdm_sdi1 + &rm_io28_pdm_sdi2 + &rm_io29_pdm_sdi3>; +}; From f3b2b42991b0efa168ff4b30b7f314aaee7ca2e8 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Mon, 1 Jul 2024 17:51:09 +0800 Subject: [PATCH 174/191] ARM: dts: rk3506-evb1: add dsm_sound/acodec_sound card node Change-Id: I968c8bf89ef72a0085eae969819a2f3872d0ea89 Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index f8b60ad7bd7a..ea226853264f 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -15,6 +15,21 @@ bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; }; + acodec_sound: acodec-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <1024>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&sai4>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + }; + }; + adc_keys: adc-keys { compatible = "adc-keys"; io-channels = <&saradc 1>; @@ -88,6 +103,22 @@ status = "okay"; }; + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&acdcdig_dsm>; + }; + }; + es8388_sound: es8388-sound { compatible = "rockchip,multicodecs-card"; rockchip,card-name = "rockchip-es8388"; @@ -241,6 +272,10 @@ }; }; +&audio_codec { + status = "okay"; +}; + &can0 { assigned-clocks = <&cru CLK_CAN0>; assigned-clock-rates = <200000000>; @@ -702,6 +737,10 @@ &rm_io12_sai1_sdo0>; }; +&sai4 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; From 2837e8e60d2f8699adedbcb395c888207929b6ba Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Mon, 1 Jul 2024 17:21:02 +0800 Subject: [PATCH 175/191] ARM: dts: rk3506-evb1-v10: enable RGA node Change-Id: I8fd1d6fe00b37b240045857301e260d31ff71f40 Signed-off-by: Yu Qiaowei --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index ea226853264f..684da9fd5dd1 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -728,6 +728,10 @@ status = "okay"; }; +&rga2 { + status = "okay"; +}; + &sai1 { status = "okay"; pinctrl-names = "default"; From 381e81b0c37e02dc7437ef9a60c156b3389f11a9 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Mon, 1 Jul 2024 17:52:14 +0800 Subject: [PATCH 176/191] ARM: dts: rk3503-evb1: enable dsm_sound card Change-Id: I4c38f51f566b68fca2c831e9389be4ca5154488f Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3503g-evb1-v10.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rk3503g-evb1-v10.dts b/arch/arm/boot/dts/rk3503g-evb1-v10.dts index 1acccbddf758..7dedeed7d10d 100644 --- a/arch/arm/boot/dts/rk3503g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3503g-evb1-v10.dts @@ -12,3 +12,15 @@ model = "Rockchip RK3503G(QFN88) EVB1 V10 Board"; compatible = "rockchip,rk3503g-evb1-v10", "rockchip,rk3506"; }; + +&acdcdig_dsm { + status = "okay"; +}; + +&dsm_sound { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; From 2a394dfc9757cdbbad735c4e12f5f753c5d520d3 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 1 Jul 2024 22:24:14 +0800 Subject: [PATCH 177/191] ARM: dts: rk3506-evb1-v10: Add FLEXBUS fspi node Change-Id: I3face3b49a98c5e0fd0ef64ed6d0837224c52b4a Signed-off-by: Jon Lin --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 684da9fd5dd1..411d4158a862 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -590,6 +590,22 @@ status = "disabled"; }; +&flexbus_fspi { + pinctrl-names = "default"; + pinctrl-0 = <&flexbus0m1_pins &flexbus0_clk_pins + &flexbus0_d0_pins &flexbus0_d1_pins + &flexbus0_d2_pins &flexbus0_d3_pins>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &fspi { status = "okay"; From fd5c38840afb88f9630981eb3a9803ba2de35850 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Sat, 29 Jun 2024 14:59:36 +0800 Subject: [PATCH 178/191] ARM: dts: rockchip: Add rk3506g-test1-v10 audio board Depends on CONFIG_I2C_GPIO Signed-off-by: Sugar Zhang Signed-off-by: Jason Zhu Signed-off-by: Jianwei Zheng Signed-off-by: William Wu Change-Id: If90642c916012daf6079a452bf453b53f5ca5599 --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/rk3506g-test1-v10-audio.dts | 511 ++++++++++++++++++ 2 files changed, 513 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rk3506g-test1-v10-audio.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3eec4d02c842..406c0d219e58 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1229,7 +1229,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dtb \ rk3506g-evb1-v10-sii9022-rgb2hdmi.dtb \ rk3506g-iotest-v10.dtb \ - rk3506g-iotest-v10-pdm.dtb + rk3506g-iotest-v10-pdm.dtb \ + rk3506g-test1-v10-audio.dtb dtb-$(CONFIG_ARCH_S3C24XX) += \ s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ diff --git a/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts new file mode 100644 index 000000000000..fe7a2d7adbaa --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506.dtsi" + +/ { + model = "Rockchip RK3506G TEST1 V10 Audio Board"; + compatible = "rockchip,rk3506g-test1-v10", "rockchip,rk3506"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0a0000 console=ttyFIQ0 ubi.mtd=4 ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + acodec_sound: acodec-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sai4-1r-adc"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <1024>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&sai4>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + }; + }; + + dsm_sound: dsm-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-dsm-sound"; + simple-audio-card,bitclock-master = <&dsm_master>; + simple-audio-card,frame-master = <&dsm_master>; + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + dsm_master: simple-audio-card,codec { + sound-dai = <&acdcdig_dsm>; + }; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + }; + + gpio_i2c0: i2c@0 { + compatible = "i2c-gpio"; + gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_i2c0_pins>; + + es8388_6: es8388@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-6"; + }; + + es8388_7: es8388@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-7"; + }; + }; + + gpio_i2c1: i2c@1 { + compatible = "i2c-gpio"; + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>, /* sda */ + <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_i2c1_pins>; + + es8388_8: es8388@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai2>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai2>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_mclk_pins>; + sound-name-prefix = "ES8388-8"; + }; + + es8388_9: es8388@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai3>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai3>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&sai3_mclk_pins>; + sound-name-prefix = "ES8388-9"; + }; + }; + + /* SAI0 1TX + 4RX */ + sai0_es8388x4_sound: sai0-es8388x4-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "sai0-1t4r-es8388x4"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&es8388_0>, <&es8388_1>, + <&es8388_2>, <&es8388_3>; + rockchip,audio-routing = + "Speaker", "ES8388-0 LOUT1", + "Speaker", "ES8388-0 ROUT1", + "ES8388-0 LINPUT1", "Main Mic", /* From ES8388-4 */ + "ES8388-0 LINPUT2", "Main Mic", /* From ES8388-4 */ + "ES8388-1 LINPUT1", "Main Mic", /* From ES8388-5 */ + "ES8388-1 LINPUT2", "Main Mic", /* From ES8388-5 */ + "ES8388-2 LINPUT1", "Main Mic", /* From ES8388-6 */ + "ES8388-2 LINPUT2", "Main Mic", /* From ES8388-6 */ + "ES8388-3 LINPUT1", "Main Mic", /* From ES8388-7 */ + "ES8388-3 LINPUT2", "Main Mic"; /* From ES8388-7 */ + }; + + /* SAI1 4TX + 1RX */ + sai1_es8388x4_sound: sai1-es8388x4-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "sai1-4t1r-es8388x4"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai1>; + rockchip,codec = <&es8388_4>, <&es8388_5>, + <&es8388_6>, <&es8388_7>; + rockchip,audio-routing = + "Speaker", "ES8388-4 LOUT1", + "Speaker", "ES8388-4 ROUT1", + "Speaker", "ES8388-5 LOUT1", + "Speaker", "ES8388-5 ROUT1", + "Speaker", "ES8388-6 LOUT1", + "Speaker", "ES8388-6 ROUT1", + "Speaker", "ES8388-7 LOUT1", + "Speaker", "ES8388-7 ROUT1", + "ES8388-4 LINPUT1", "Main Mic", /* From ES8388-0 */ + "ES8388-4 LINPUT2", "Main Mic"; /* From ES8388-0 */ + }; + + /* SAI2 1TX + 1RX */ + sai2_es8388x1_sound: sai2-es8388x1-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "sai2-1t1r-es8388x1"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai2>; + rockchip,codec = <&es8388_8>; + rockchip,audio-routing = + "Speaker", "ES8388-8 LOUT1", + "Speaker", "ES8388-8 ROUT1", + "ES8388-8 LINPUT1", "Main Mic", /* From ES8388-8 */ + "ES8388-8 LINPUT2", "Main Mic"; /* From ES8388-8 */ + }; + + /* SAI3 1TX + 1RX */ + sai3_es8388x1_sound: sai3-es8388x1-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "sai3-1t1r-es8388x1"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai3>; + rockchip,codec = <&es8388_9>; + rockchip,audio-routing = + "Speaker", "ES8388-9 LOUT1", + "Speaker", "ES8388-9 ROUT1", + "ES8388-9 LINPUT1", "Main Mic", /* From ES8388-9 */ + "ES8388-9 LINPUT2", "Main Mic"; /* From ES8388-9 */ + }; + + spdif_rx_dc: spdif-rx-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + spdif_rx_sound: spdif-rx-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "spdif-rx-sound"; + simple-audio-card,cpu { + sound-dai = <&spdif_rx>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_rx_dc>; + }; + }; + + spdif_tx_dc: spdif-tx-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + spdif_tx_sound: spdif-tx-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx_dc>; + }; + }; + + vcc12v_dc: vcc12v-dc { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dc>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0_4ch_0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1207000>; + regulator-init-microvolt = <1011000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + }; + + vcc5v0_otg0: vcc5v0-otg0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg0_en>; + }; +}; + +&acdcdig_dsm { + status = "disabled"; + pa-ctl-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_audm1_ln_pins + &dsm_audm1_lp_pins + &dsm_spk_ctrl>; +}; + +&audio_codec { + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io18_i2c0_scl + &rm_io19_i2c0_sda>; + + es8388_0: es8388@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io2_sai0_mclk>; + sound-name-prefix = "ES8388-0"; + }; + + es8388_1: es8388@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-1"; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io25_i2c1_scl + &rm_io26_i2c1_sda>; + + es8388_2: es8388@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-2"; + }; + + es8388_3: es8388@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-3"; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io30_i2c2_scl + &rm_io31_i2c2_sda>; + + es8388_4: es8388@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-4"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io8_sai1_mclk>; + }; + + es8388_5: es8388@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x10>; + clocks = <&mclkout_sai1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "ES8388-5"; + }; +}; + +&pinctrl { + acodec-dsm { + /omit-if-no-ref/ + dsm_spk_ctrl: dsm-spk-ctrl { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-i2c { + /omit-if-no-ref/ + gpio_i2c0_pins: gpio-i2c0-pins { + rockchip,pins = + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* sda */ + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; /* scl */ + }; + + /omit-if-no-ref/ + gpio_i2c1_pins: gpio-i2c1-pins { + rockchip,pins = + <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* sda */ + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; /* scl */ + }; + }; + + usb { + vcc5v0_otg0_en: vcc5v0-otg0-en { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0_4ch_0 { + pinctrl-names = "active"; + pinctrl-0 = <&rm_io21_pwm0_ch0>; + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io0_sai0_lrck + &rm_io1_sai0_sclk + &rm_io3_sai0_sdo + &rm_io4_sai0_sdi0 + &rm_io5_sai0_sdi1 + &rm_io6_sai0_sdi2 + &rm_io7_sai0_sdi3>; +}; + +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io9_sai1_sclk + &rm_io10_sai1_lrck + &rm_io11_sai1_sdi + &rm_io12_sai1_sdo0 + &rm_io13_sai1_sdo1 + &rm_io14_sai1_sdo2 + &rm_io15_sai1_sdo3>; +}; + +&sai2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck_pins + &sai2m0_sclk_pins + &sai2m0_sdi_pins + &sai2m0_sdo_pins>; +}; + +&sai3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai3_lrck_pins + &sai3_sclk_pins + &sai3_sdi_pins + &sai3_sdo_pins>; +}; + +&sai4 { + status = "okay"; +}; + +&spdif_rx { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io17_spdif_rx>; +}; + +&spdif_tx { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io16_spdif_tx>; +}; + +&usb20_otg0 { + status = "okay"; +}; From 297d9a4773392e79a14f7f84348c340b20e2a058 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 28 Jun 2024 16:19:17 +0800 Subject: [PATCH 179/191] ARM: dts: rockchip: rk3506-evb1: add reserved-memory for display and drm_logo memory config Change-Id: I9cb948f2cdddc29ead70cd2045824a44d8566e2e Signed-off-by: Damon Ding --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 411d4158a862..ec4ccb8d0fba 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -164,6 +164,24 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + linux,cma-default; + }; + + drm_logo: drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0>; + }; + }; + vcc12v_dc: vcc12v-dc { compatible = "regulator-fixed"; regulator-name = "vcc12v_dc"; @@ -289,6 +307,7 @@ }; &display_subsystem { + logo-memory-region = <&drm_logo>; status = "okay"; }; From a63ddd3753b8c90564cf927e6909ba27c298b1ed Mon Sep 17 00:00:00 2001 From: Lin Jinhan Date: Wed, 3 Jul 2024 15:48:44 +0800 Subject: [PATCH 180/191] ARM: dts: rk3506-evb1-v10: enable rng node Signed-off-by: Lin Jinhan Change-Id: I259d11700cf1f5097d3c2d2e0c3a19661f5ed97f --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index ec4ccb8d0fba..ad357cc6253c 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -767,6 +767,10 @@ status = "okay"; }; +&rng { + status = "okay"; +}; + &sai1 { status = "okay"; pinctrl-names = "default"; From 33ab8bc7b36ed2fbcb1449b5e5f3aeea6476a9e4 Mon Sep 17 00:00:00 2001 From: Cliff Chen Date: Tue, 2 Jul 2024 14:30:12 +0800 Subject: [PATCH 181/191] ARM: dts: rockchip: Add rk3506-amp.dtsi Change-Id: Iaf7f31e72988f5326c60a915e5b0db7305598250 Signed-off-by: Cliff Chen --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3506-amp.dtsi | 89 ++++++++++++++++++++++ arch/arm/boot/dts/rk3506g-evb1-v10-amp.dts | 9 +++ 3 files changed, 99 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506-amp.dtsi create mode 100644 arch/arm/boot/dts/rk3506g-evb1-v10-amp.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 406c0d219e58..3d2f9c0ebc26 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1224,6 +1224,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3503g-evb1-v10.dtb \ rk3506b-evb1-v10.dtb \ rk3506g-evb1-v10.dtb \ + rk3506g-evb1-v10-amp.dtb \ rk3506g-evb1-v10-mcu-k350c4516t.dtb \ rk3506g-evb1-v10-rgb-Q7050ITH2641AA1T.dtb \ rk3506g-evb1-v10-sii9022-bt1120-to-hdmi.dtb \ diff --git a/arch/arm/boot/dts/rk3506-amp.dtsi b/arch/arm/boot/dts/rk3506-amp.dtsi new file mode 100644 index 000000000000..17b7b8f36c3a --- /dev/null +++ b/arch/arm/boot/dts/rk3506-amp.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include + +#define CPU_GET_AFFINITY(cluster, cpu) (cpu) + +/ { + cpus { + /delete-node/ cpu@f02; + }; + + rockchip_amp: rockchip-amp { + compatible = "rockchip,amp"; + clocks = <&cru HCLK_M0>, <&cru STCLK_M0>, + <&cru SCLK_UART4>, <&cru PCLK_UART4>, + <&cru PCLK_TIMER>, <&cru CLK_TIMER0_CH5>; + + pinctrl-names = "default"; + pinctrl-0 = <&rm_io27_uart4_tx>, <&rm_io28_uart4_rx>; + + amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4>; + amp-irqs = /bits/ 64 < + /* GPIO EXT */ + GIC_AMP_IRQ_CFG_ROUTE(35, 0xd0, CPU_GET_AFFINITY(0, 2)) + GIC_AMP_IRQ_CFG_ROUTE(39, 0xd0, CPU_GET_AFFINITY(0, 2)) + GIC_AMP_IRQ_CFG_ROUTE(43, 0xd0, CPU_GET_AFFINITY(0, 2)) + GIC_AMP_IRQ_CFG_ROUTE(47, 0xd0, CPU_GET_AFFINITY(0, 2)) + GIC_AMP_IRQ_CFG_ROUTE(51, 0xd0, CPU_GET_AFFINITY(0, 2)) + /* UART4 */ + GIC_AMP_IRQ_CFG_ROUTE(70, 0xd0, CPU_GET_AFFINITY(0, 2)) + /* MAILBOX */ + GIC_AMP_IRQ_CFG_ROUTE(174, 0xd0, CPU_GET_AFFINITY(0, 2))>; + + status = "okay"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* remote amp core address */ + amp_shmem_reserved: amp-shmem@3b00000 { + reg = <0x03b00000 0x100000>; + no-map; + }; + + rpmsg_reserved: rpmsg@3c00000 { + reg = <0x03c00000 0x100000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@3d00000 { + compatible = "shared-dma-pool"; + reg = <0x03d00000 0x100000>; + no-map; + }; + + /* mcu address */ + mcu_reserved: mcu@fff80000 { + reg = <0xfff80000 0xc000>; + no-map; + }; + }; + + rpmsg: rpmsg@3c00000 { + compatible = "rockchip,rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox0 0 &mailbox0 3>; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x3c00000 0x100000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>; +}; + +&mailbox0 { + rockchip,txpoll-period-ms = <1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10-amp.dts b/arch/arm/boot/dts/rk3506g-evb1-v10-amp.dts new file mode 100644 index 000000000000..de109795df91 --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-v10-amp.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3506g-evb1-v10.dts" +#include "rk3506-amp.dtsi" From 0bbcfa2c126f1b6eec17ade2a7416d122f24753d Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 3 Jul 2024 19:56:35 +0800 Subject: [PATCH 182/191] ARM: dts: rockchip: rk3506-evb1-v10: Enable usb2 phy Signed-off-by: William Wu Change-Id: I5ab6698176c18a747ccc9d415b3579c564f25ed0 --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index ad357cc6253c..940456b91f24 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -798,6 +798,18 @@ status = "okay"; }; +&u2phy_otg0 { + status = "okay"; +}; + +&u2phy_otg1 { + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + &usb20_otg0 { status = "okay"; }; From 325f3652077ae68c287aacce6e6cbf12ddce0662 Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Sat, 29 Jun 2024 16:42:37 +0800 Subject: [PATCH 183/191] ARM: dts: rockchip: Support usb2phy for rk3506g-evb1 This patch enable usb2phy for rk3506g-evb1 and support to use extcon usb gpio driver for usb2phy vbus and id detection. Change-Id: I389cf3801a302ff70b1db673803472e493888294 Signed-off-by: Jianwei Zheng Signed-off-by: William Wu --- arch/arm/boot/dts/rk3506g-evb1-v10.dts | 34 ++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index 7203584edd5f..8dc6c487f0ca 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -12,6 +12,14 @@ model = "Rockchip RK3506G(QFN128) EVB1 V10 Board"; compatible = "rockchip,rk3506g-evb1-v10", "rockchip,rk3506"; + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_extcon_vbus>; + status = "okay"; + }; + vcc3v3_lcd_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; enable-active-high; @@ -30,7 +38,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_sys>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_otg0_en>; }; @@ -44,6 +53,7 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_sys>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_otg1_en>; }; @@ -72,12 +82,32 @@ &pinctrl { usb { - vcc5v0_otg0_en: vcc5v0-otg0-en { + usb_extcon_vbus: usb-extcon-vbus { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_otg0_en: vcc5v0-otg0-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_otg1_en: vcc5v0-otg1-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; + +&u2phy_otg0 { + vbus-supply = <&vcc5v0_otg0>; + rockchip,gpio-vbus-det; + status = "okay"; +}; + +&u2phy_otg1 { + phy-supply = <&vcc5v0_otg1>; + status = "okay"; +}; + +&usb2phy { + extcon = <&extcon_usb>; + status = "okay"; +}; From cdff835f978aff0c3edd8f86b8b1c28601a5c1a2 Mon Sep 17 00:00:00 2001 From: Hongming Zou Date: Wed, 3 Jul 2024 19:18:46 +0800 Subject: [PATCH 184/191] ARM: dts: rockchip: rk3506g-evb1: enable logo display for mipi board Change-Id: I50dcc7e86869008eff24f3e20da55fc12c19ac3d Signed-off-by: Hongming Zou --- arch/arm/boot/dts/rk3506g-evb1-v10.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index 8dc6c487f0ca..3058b2386ab7 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -96,6 +96,10 @@ }; }; +&route_dsi { + status = "okay"; +}; + &u2phy_otg0 { vbus-supply = <&vcc5v0_otg0>; rockchip,gpio-vbus-det; From 830a37fb671c5fb121fcaa10c6f19fc6ada167d4 Mon Sep 17 00:00:00 2001 From: ZiHan Huang Date: Wed, 3 Jul 2024 15:25:52 +0800 Subject: [PATCH 185/191] ARM: dts: rockchip: rk3506-evb1: Additional reservation cma buf Change-Id: Idd169c243f898986d9b14a813a4f9b31c1811f2b Signed-off-by: ZiHan Huang --- arch/arm/boot/dts/rk3506g-evb1-v10.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index 3058b2386ab7..6dcd42c300d4 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -59,6 +59,10 @@ }; }; +&cma { + size = <0x1600000>; +}; + &dsi { status = "okay"; }; From 492fbe5004f0ef7bfe8807ebc0a35ea3fc002ec9 Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Fri, 5 Jul 2024 14:41:05 +0800 Subject: [PATCH 186/191] ARM: dts: rockchip: rk3506g-test1: add pdm_mic_array sound card with es7202 Change-Id: I34585bfbe48b748d0eff5212e4e93f15cf50c5b6 Signed-off-by: Jason Zhu --- arch/arm/boot/dts/rk3506g-test1-v10-audio.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts index fe7a2d7adbaa..915fe72540ae 100644 --- a/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts +++ b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts @@ -124,6 +124,15 @@ }; }; + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,pdm-mic-array"; + rockchip,cpu = <&pdm>; + rockchip,codec = <&es7202_0>, <&es7202_1>, + <&es7202_2>, <&es7202_3>; + }; + /* SAI0 1TX + 4RX */ sai0_es8388x4_sound: sai0-es8388x4-sound { compatible = "rockchip,multicodecs-card"; @@ -326,6 +335,38 @@ pinctrl-0 = <&rm_io18_i2c0_scl &rm_io19_i2c0_sda>; + es7202_0: es7202@30 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + reg = <0x30>; + sound-name-prefix = "ES7202-0"; + }; + + es7202_1: es7202@31 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + reg = <0x31>; + sound-name-prefix = "ES7202-1"; + }; + + es7202_2: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + reg = <0x32>; + sound-name-prefix = "ES7202-2"; + }; + + es7202_3: es7202@34 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + reg = <0x34>; + sound-name-prefix = "ES7202-3"; + }; + es8388_0: es8388@11 { #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; @@ -411,6 +452,16 @@ }; }; +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&rm_io11_pdm_clk0 + &rm_io12_pdm_sdi0 + &rm_io13_pdm_sdi1 + &rm_io14_pdm_sdi2 + &rm_io15_pdm_sdi3>; +}; + &pinctrl { acodec-dsm { /omit-if-no-ref/ From 565a719e03f87bf91dc0e97d0848d6b26bd610bf Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Thu, 4 Jul 2024 11:45:41 +0800 Subject: [PATCH 187/191] ARM: dts: rockchip: rk3506-evb1: add ramoops Change-Id: I02bc9343d060e4d4b1bb48f10dba572a6b1866c2 Signed-off-by: Huibin Hong --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 940456b91f24..88d3fde2b671 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -180,6 +180,17 @@ compatible = "rockchip,drm-logo"; reg = <0x0 0x0>; }; + + ramoops: ramoops@880000 { + compatible = "ramoops"; + reg = <0x880000 0x80000>; + boot-log-size = <0x10000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x70000>; + pmsg-size = <0x0>; + ftrace-size = <0x0>; + record-size = <0x0>; + }; }; vcc12v_dc: vcc12v-dc { From ea58eb40b7edaeb7778fac7b107166ffaa63febd Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Fri, 5 Jul 2024 11:54:40 +0800 Subject: [PATCH 188/191] ARM: dts: rockchip: add flexbus cif for rk3506 evb1 Signed-off-by: Zefa Chen Change-Id: I43fbf4beeb184e3fc3093f6e113cca551479e776 --- .../boot/dts/rk3506g-evb1-flexbus-cif.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/arm/boot/dts/rk3506g-evb1-flexbus-cif.dtsi diff --git a/arch/arm/boot/dts/rk3506g-evb1-flexbus-cif.dtsi b/arch/arm/boot/dts/rk3506g-evb1-flexbus-cif.dtsi new file mode 100644 index 000000000000..43f26080cf0f --- /dev/null +++ b/arch/arm/boot/dts/rk3506g-evb1-flexbus-cif.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +&flexbus { + rockchip,flexbus0-opmode = ; + rockchip,flexbus1-opmode = ; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + + clocks = <&cru CLK_REF_OUT1>; + clock-names = "xvclk"; + power-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ref_clk1_pins>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + + port { + gc2145_out: endpoint { + remote-endpoint = <&cif_in_cam>; + vsync-active = <0>; + hsync-active = <1>; + pclk-sample = <1>; + bus-width = <8>; + }; + }; + }; +}; + +&flexbus_cif { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&flexbus1_d1_pins &flexbus1_d2_pins &flexbus1_d3_pins &flexbus1_d4_pins + &flexbus1_d5_pins &flexbus1_d6_pins &flexbus1_d7_pins &flexbus1_d8_pins + &flexbus1_d12_pins &flexbus1_d13_pins &flexbus1_clk_pins>; + ports { + port@0 { + cif_in_cam: endpoint@0 { + remote-endpoint = <&gc2145_out>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; + }; +}; From 1cf81ee6b9ef8317497f1734361b8d8e91038a7d Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 5 Jul 2024 18:57:23 +0800 Subject: [PATCH 189/191] ARM: dts: rk3506g-evb1-v10: Enable es8388-sound Signed-off-by: Sugar Zhang Change-Id: I1836d10b674a908efdd062d2e4472f762ab303af --- arch/arm/boot/dts/rk3506-evb1-v10.dtsi | 4 ++-- arch/arm/boot/dts/rk3506g-evb1-v10.dts | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi index 88d3fde2b671..1525f479811f 100644 --- a/arch/arm/boot/dts/rk3506-evb1-v10.dtsi +++ b/arch/arm/boot/dts/rk3506-evb1-v10.dtsi @@ -120,6 +120,7 @@ }; es8388_sound: es8388-sound { + status = "disabled"; compatible = "rockchip,multicodecs-card"; rockchip,card-name = "rockchip-es8388"; spk-con-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; @@ -673,7 +674,7 @@ &rm_io14_i2c0_sda>; es8388: es8388@11 { - status = "okay"; + status = "disabled"; #sound-dai-cells = <0>; compatible = "everest,es8388", "everest,es8323"; reg = <0x11>; @@ -783,7 +784,6 @@ }; &sai1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rm_io9_sai1_sclk &rm_io10_sai1_lrck diff --git a/arch/arm/boot/dts/rk3506g-evb1-v10.dts b/arch/arm/boot/dts/rk3506g-evb1-v10.dts index 6dcd42c300d4..6ed47bd045c0 100644 --- a/arch/arm/boot/dts/rk3506g-evb1-v10.dts +++ b/arch/arm/boot/dts/rk3506g-evb1-v10.dts @@ -79,6 +79,14 @@ power-supply = <&vcc3v3_lcd_n>; }; +&es8388 { + status = "okay"; +}; + +&es8388_sound { + status = "okay"; +}; + >1x { power-supply = <&vcc3v3_lcd_n>; status = "okay"; @@ -104,6 +112,10 @@ status = "okay"; }; +&sai1 { + status = "okay"; +}; + &u2phy_otg0 { vbus-supply = <&vcc5v0_otg0>; rockchip,gpio-vbus-det; From f048e9102d2d59a225d64cfeb317015363505d3d Mon Sep 17 00:00:00 2001 From: Jianwei Zheng Date: Fri, 5 Jul 2024 17:02:32 +0800 Subject: [PATCH 190/191] ARM: dts: rockchip: rk3506g-test1-v10-audio: Add extcon for usb 1. Add extcon usb vbus_det/id gpios for otg0. 2. Fix the vbus control gpio for otg0. 3. Add vbus control gpio for otg1. 4. Set host mode for otg1. Change-Id: Ia075889449559539c7a2e41a3c50e2b928a46ad0 Signed-off-by: Jianwei Zheng Signed-off-by: William Wu --- arch/arm/boot/dts/rk3506g-test1-v10-audio.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts index 915fe72540ae..1b2ba7f11260 100644 --- a/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts +++ b/arch/arm/boot/dts/rk3506g-test1-v10-audio.dts @@ -45,6 +45,15 @@ }; }; + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + id-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_extcon_vbus &usb_extcon_id>; + status = "okay"; + }; + fiq_debugger: fiq-debugger { compatible = "rockchip,fiq-debugger"; rockchip,serial-id = <0>; @@ -301,6 +310,21 @@ gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_otg0_en>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_otg1: vcc5v0-otg1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg1_en>; + vin-supply = <&vcc_sys>; }; }; @@ -487,9 +511,21 @@ }; usb { + usb_extcon_id: usb-extcon-id { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_extcon_vbus: usb-extcon-vbus { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_otg0_en: vcc5v0-otg0-en { rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; + + vcc5v0_otg1_en: vcc5v0-otg1-en { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; @@ -557,6 +593,28 @@ pinctrl-0 = <&rm_io16_spdif_tx>; }; +&u2phy_otg0 { + vbus-supply = <&vcc5v0_otg0>; + rockchip,gpio-vbus-det; + rockchip,gpio-id-det; + status = "okay"; +}; + +&u2phy_otg1 { + phy-supply = <&vcc5v0_otg1>; + status = "okay"; +}; + &usb20_otg0 { status = "okay"; }; + +&usb20_otg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + extcon = <&extcon_usb>; + status = "okay"; +}; From be9616a9ff96f49b484837dc9dcb25d99ea50ab5 Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Fri, 12 Jul 2024 11:18:14 +0800 Subject: [PATCH 191/191] ARM: rk3506_defconfig: Enable CONFIG_ROCKCHIP_MINI_KERNEL -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -# CONFIG_STRICT_MODULE_RWX is not set -CONFIG_VIDEOBUF2_CMA_SG -CONFIG_VIDEOBUF2_DMA_CONTIG -CONFIG_VIDEOBUF2_VMALLOC -CONFIG_VIDEOBUF2_DMA_SG -CONFIG_DRM_EDID -CONFIG_DRM_DP -CONFIG_ROCKCHIP_DRM_DEBUG -CONFIG_SND_PCM_ELD -CONFIG_SND_SOC_HDMI_CODEC +CONFIG_DTC_OMIT_DISABLED=y +CONFIG_DTC_OMIT_EMPTY=y +CONFIG_MMC_QUEUE_DEPTH=1 before: text data bss dec hex filename 4113328 1882232 96904 6092464 5cf6b0 vmlinux after: text data bss dec hex filename 4090837 1838576 97992 6027405 5bf88d vmlinux Change-Id: Ie247122d435f7da79081b034822355f45f217f3f Signed-off-by: Tao Huang --- arch/arm/configs/rk3506_defconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/rk3506_defconfig b/arch/arm/configs/rk3506_defconfig index b9fc803913c9..2a38f7ad83ac 100644 --- a/arch/arm/configs/rk3506_defconfig +++ b/arch/arm/configs/rk3506_defconfig @@ -49,7 +49,6 @@ CONFIG_NEON=y CONFIG_JUMP_LABEL=y # CONFIG_STACKPROTECTOR_STRONG is not set # CONFIG_STRICT_KERNEL_RWX is not set -# CONFIG_STRICT_MODULE_RWX is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y @@ -124,7 +123,10 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_SMSC is not set # CONFIG_NET_VENDOR_SOCIONEXT is not set CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_ETHTOOL=y +CONFIG_STMMAC_FULL=y # CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_ROCKCHIP_TOOL=y # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set @@ -181,6 +183,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_DRM=y CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_ROCKCHIP=y +CONFIG_ROCKCHIP_VOP=y CONFIG_ROCKCHIP_DW_MIPI_DSI=y CONFIG_ROCKCHIP_RGB=y CONFIG_DRM_PANEL_SIMPLE=y @@ -219,6 +222,7 @@ CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_MMC=y +CONFIG_MMC_QUEUE_DEPTH=1 CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_RTC_CLASS=y @@ -229,6 +233,7 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set CONFIG_STAGING=y +CONFIG_ROCKCHIP_CLK_OUT=y # CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_CPU_RK3506=y @@ -243,6 +248,7 @@ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y CONFIG_RK_CONSOLE_THREAD=y CONFIG_ROCKCHIP_DEBUG=y +CONFIG_ROCKCHIP_MINI_KERNEL=y CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_USERSPACE=y