From af0532f8a6f0fa9248acbd9b7d3451a92b8f0c3d Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 17 May 2022 10:50:44 +0800 Subject: [PATCH] drm/rockchip: vop2: remove the clk limit for dp interfce When a video port just connect to dp and without hdmi, it still can use hdmi phy pll as clk source if the pixel clk more than 600MHz. Signed-off-by: Zhang Yubing Change-Id: I975a0faaad867361c0888b795e9369ca1381634f --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 9cbef7e33704..8d2c87b630cb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3670,7 +3670,7 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp, hdmi1_phy_pll->vp_mask |= BIT(vp->id); } else if (output_if_is_dp(vcstate->output_if)) { - if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE || vp->id == 2) { + if (vp->id == 2) { vop2_clk_set_parent(vp->dclk, vp->dclk_parent); return 0; }