From af40bf26048513d87d7559314e7198ca6d6d82c7 Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Mon, 25 Feb 2019 16:53:37 +0800
Subject: [PATCH] clk: rockchip: rk1808: add cpll as critical clk

Change-Id: Ibf02b6ed9916e774d7a82f33ac7f96e3395e4e88
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk1808.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c
index e589ed1f0390..17a9704cacef 100644
--- a/drivers/clk/rockchip/clk-rk1808.c
+++ b/drivers/clk/rockchip/clk-rk1808.c
@@ -1160,6 +1160,7 @@ static const char *const rk1808_critical_clocks[] __initconst = {
 	"pclk_ddr_grf",
 	"aclk_gic",
 	"hsclk_imem",
+	"cpll",
 };
 
 static void __iomem *rk1808_cru_base;