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arm64: dts: mediatek: mt2712: fix validation errors

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[ Upstream commit 3baac7291effb501c4d52df7019ebf52011e5772 ]

1. Fixup infracfg clock controller binding
   It also acts as reset controller so #reset-cells is required.
2. Use -pins suffix for pinctrl

This fixes:
arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: syscon@10001000: '#reset-cells' is a required property
        from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: pinctrl@1000b000: 'eth_default', 'eth_sleep', 'usb0_iddig', 'usb1_iddig' do not match any of the regexes: 'pinctrl-[0-9]+', 'pins$'
        from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240301074741.8362-1-zajec5@gmail.com
[Angelo: Added Fixes tags]
Fixes: 5d4839709c ("arm64: dts: mt2712: Add clock controller device nodes")
Fixes: 1724f4cc51 ("arm64: dts: Add USB3 related nodes for MT2712")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Rafał Miłecki
2024-03-01 08:47:41 +01:00
committed by Greg Kroah-Hartman
parent 1aea205a42
commit af45b5bc30
2 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View File

@@ -128,7 +128,7 @@
}; };
&pio { &pio {
eth_default: eth_default { eth_default: eth-default-pins {
tx_pins { tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>, pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>, <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@@ -155,7 +155,7 @@
}; };
}; };
eth_sleep: eth_sleep { eth_sleep: eth-sleep-pins {
tx_pins { tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>, pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>, <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@@ -181,14 +181,14 @@
}; };
}; };
usb0_id_pins_float: usb0_iddig { usb0_id_pins_float: usb0-iddig-pins {
pins_iddig { pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>; pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up; bias-pull-up;
}; };
}; };
usb1_id_pins_float: usb1_iddig { usb1_id_pins_float: usb1-iddig-pins {
pins_iddig { pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>; pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up; bias-pull-up;

3
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@@ -249,10 +249,11 @@
#clock-cells = <1>; #clock-cells = <1>;
}; };
infracfg: syscon@10001000 { infracfg: clock-controller@10001000 {
compatible = "mediatek,mt2712-infracfg", "syscon"; compatible = "mediatek,mt2712-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>; reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
pericfg: syscon@10003000 { pericfg: syscon@10003000 {