From afd6026f71d747b3e278f9dfcbb8d8fec5eb5c1f Mon Sep 17 00:00:00 2001
From: Wyon Bi <bivvy.bi@rock-chips.com>
Date: Thu, 25 Nov 2021 19:20:12 +0800
Subject: [PATCH] drm/rockchip: vop2: Support set clock defaults for vp node

Parse and set assigned clocks configuration at the child node level.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I745090ebc2a3531c51557600fdb69867d7216684
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 84dddeee1db4..cf2a4f9feb1d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/clk-conf.h>
 #include <linux/iopoll.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -8288,6 +8289,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
 			else
 				vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
 
+			ret = of_clk_set_defaults(child, false);
+			if (ret) {
+				DRM_DEV_ERROR(dev, "Failed to set clock defaults %d\n", ret);
+				return ret;
+			}
+
 			DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n",
 				     vp_id, vop2->vps[vp_id].plane_mask,
 				     vop2->vps[vp_id].primary_plane_phy_id);