From b06291815db243f44e07c5f5f9a57bb6e9fda973 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 10 Mar 2020 10:53:12 +0800 Subject: [PATCH] ARM: dts: rv1126: add SPI0 and SPI1 node Change-Id: I15c9c665291a586204b71fcf7066928745887717 Signed-off-by: Jon Lin --- arch/arm/boot/dts/rv1126.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi index 855cd1545671..f7284895ceed 100644 --- a/arch/arm/boot/dts/rv1126.dtsi +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -33,6 +33,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; + spi0 = &spi0; + spi1 = &spi1; }; cpus { @@ -590,6 +592,21 @@ status = "disabled"; }; + spi0: spi@ff450000 { + compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; + reg = <0xff450000 0x1000>; + interrupts = ; + #address-cells = <1>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 1>, <&dmac 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>; + pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>; + status = "disabled"; + }; + pvtm@ff470000 { compatible = "rockchip,rv1126-pmu-pvtm"; reg = <0xff470000 0x100>; @@ -862,6 +879,21 @@ status = "disabled"; }; + spi1: spi@ff5b0000 { + compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; + reg = <0xff5b0000 0x1000>; + interrupts = ; + #address-cells = <1>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 3>, <&dmac 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>; + pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>; + status = "disabled"; + }; + otp: otp@ff5c0000 { compatible = "rockchip,rv1126-otp"; reg = <0xff5c0000 0x1000>;