diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8b2ff82971de..1d7385950ecc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1185,6 +1185,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1126b-evb1-v10-spi-nor.dtb \ rv1126b-evb1-v11.dtb \ rv1126b-evb1-v11-dual-4k.dtb \ + rv1126b-evb1-v11-fastboot-emmc.dtb \ + rv1126b-evb1-v11-fastboot-spi-nand.dtb \ + rv1126b-evb1-v11-fastboot-spi-nor.dtb \ + rv1126b-evb1-v11-spi-nor.dtb \ rv1126b-evb2-v10.dtb \ rv1126b-evb2-v10-dv.dtb \ rv1126b-evb2-v10-mcu-k350c4516t.dtb \ diff --git a/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-emmc.dts b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-emmc.dts new file mode 100644 index 000000000000..e4a315bcacda --- /dev/null +++ b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rv1126b-evb1-v11-fastboot-emmc.dts" + +/ { + model = "Rockchip RV1126B EVB1 V11 Fastboot Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (40 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4b440000 (20 * 0x00100000)>; +}; diff --git a/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nand.dts b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nand.dts new file mode 100644 index 000000000000..f990ca8a3170 --- /dev/null +++ b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nand.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rv1126b-evb1-v11-fastboot-spi-nand.dts" + +/ { + model = "Rockchip RV1126B EVB1 V11 Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot-spi-nand", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (40 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4b440000 (20 * 0x00100000)>; +}; diff --git a/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nor.dts b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nor.dts new file mode 100644 index 000000000000..0ca3ad2b1e16 --- /dev/null +++ b/arch/arm/boot/dts/rv1126b-evb1-v11-fastboot-spi-nor.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts" + +/ { + model = "Rockchip RV1126B EVB1 V11 Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot-spi-nand", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (20 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4a040000 (10 * 0x00100000)>; +}; diff --git a/arch/arm/boot/dts/rv1126b-evb1-v11-spi-nor.dts b/arch/arm/boot/dts/rv1126b-evb1-v11-spi-nor.dts new file mode 100644 index 000000000000..5eeb37710ff2 --- /dev/null +++ b/arch/arm/boot/dts/rv1126b-evb1-v11-spi-nor.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "arm64/rockchip/rv1126b-evb1-v11-spi-nor.dts" diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5f5f1fed4985..47539cacff71 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -386,6 +386,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-dual-4k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-emmc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-spi-nor.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-dv.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi index c8c75f842ae1..e41db79c3879 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-eink.dtsi @@ -50,6 +50,10 @@ }; &ebc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vo_ebc_pins>; + pinctrl-1 = <&vo_ebc_sleep>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi index a5b4dcb02218..28a04ad0bc97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi @@ -5817,6 +5817,57 @@ <3 RK_PD7 2 &pcfg_pull_none>; }; + /omit-if-no-ref/ + vo_ebc_sleep: vo_ebc-sleep { + rockchip,pins = + /* vo_ebc_gdclk */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_gdoe */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_gdsp */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sdce0 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sdclk */ + <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo0 */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo1 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo2 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo3 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo4 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo5 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo6 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo7 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo8 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo9 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo10 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo11 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo12 */ + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo13 */ + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo14 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sddo15 */ + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sdle */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* vo_ebc_sdoe */ + <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + /omit-if-no-ref/ vo_ebc_extern: vo_ebc-extern { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-emmc.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-emmc.dts new file mode 100644 index 000000000000..1e0f1d088361 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-emmc.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "rv1126b-evb1-v10-fastboot-emmc.dts" +#include "rv1126b-evb1-v11.dtsi" + +/ { + model = "Rockchip RV1126B EVB1 V11 Arm64 Fastboot Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (40 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4b440000 (20 * 0x00100000)>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nand.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nand.dts new file mode 100644 index 000000000000..92cff9680881 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nand.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "rv1126b-evb1-v10-fastboot-spi-nand.dts" +#include "rv1126b-evb1-v11.dtsi" + +/ { + model = "Rockchip RV1126B EVB1 V11 Arm64 Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot-spi-nand", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (40 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4b440000 (20 * 0x00100000)>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts new file mode 100644 index 000000000000..eb1d0ee5ad79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "rv1126b-evb1-v10-fastboot-spi-nor.dts" +#include "rv1126b-evb1-v11.dtsi" + +/ { + model = "Rockchip RV1126B EVB1 V11 Arm64 Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot-spi-nor", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (20 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4a040000 (10 * 0x00100000)>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-spi-nor.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-spi-nor.dts new file mode 100644 index 000000000000..8adb7b6cfe4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-spi-nor.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "rv1126b-evb1-v10-spi-nor.dts" +#include "rv1126b-evb1-v11.dtsi" + +/ { + model = "Rockchip RV1126B EVB1 V11 Board"; + compatible = "rockchip,rv1126b-evb1-v11-spi-nor", "rockchip,rv1126b"; + +}; diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi index 0d5fa19bd673..63010f4a4be0 100644 --- a/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi @@ -2708,85 +2708,85 @@ bt1120_pins: bt1120-pins { rockchip,pins = /* vo_lcdc_clk */ - <5 RK_PD3 1 &pcfg_pull_none>, + <5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>, /* vo_lcdc_d3 */ - <5 RK_PA3 1 &pcfg_pull_none>, + <5 RK_PA3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d4 */ - <5 RK_PA4 1 &pcfg_pull_none>, + <5 RK_PA4 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d5 */ - <5 RK_PA5 1 &pcfg_pull_none>, + <5 RK_PA5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d6 */ - <5 RK_PA6 1 &pcfg_pull_none>, + <5 RK_PA6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d7 */ - <5 RK_PA7 1 &pcfg_pull_none>, + <5 RK_PA7 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d10 */ - <5 RK_PB2 1 &pcfg_pull_none>, + <5 RK_PB2 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d11 */ - <5 RK_PB3 1 &pcfg_pull_none>, + <5 RK_PB3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d12 */ - <5 RK_PB4 1 &pcfg_pull_none>, + <5 RK_PB4 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d13 */ - <5 RK_PB5 1 &pcfg_pull_none>, + <5 RK_PB5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d14 */ - <5 RK_PB6 1 &pcfg_pull_none>, + <5 RK_PB6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d15 */ - <5 RK_PB7 1 &pcfg_pull_none>, + <5 RK_PB7 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d19 */ - <5 RK_PC3 1 &pcfg_pull_none>, + <5 RK_PC3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d20 */ - <5 RK_PC4 1 &pcfg_pull_none>, + <5 RK_PC4 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d21 */ - <5 RK_PC5 1 &pcfg_pull_none>, + <5 RK_PC5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d22 */ - <5 RK_PC6 1 &pcfg_pull_none>, + <5 RK_PC6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d23 */ - <5 RK_PC7 1 &pcfg_pull_none>; + <5 RK_PC7 1 &pcfg_pull_none_drv_level_2_75>; }; /omit-if-no-ref/ bt656_m0_pins: bt656-m0-pins { rockchip,pins = /* vo_lcdc_clk */ - <5 RK_PD3 1 &pcfg_pull_none>, + <5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>, /* vo_lcdc_d3 */ - <5 RK_PA3 1 &pcfg_pull_none>, + <5 RK_PA3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d4 */ - <5 RK_PA4 1 &pcfg_pull_none>, + <5 RK_PA4 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d5 */ - <5 RK_PA5 1 &pcfg_pull_none>, + <5 RK_PA5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d6 */ - <5 RK_PA6 1 &pcfg_pull_none>, + <5 RK_PA6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d7 */ - <5 RK_PA7 1 &pcfg_pull_none>, + <5 RK_PA7 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d10 */ - <5 RK_PB2 1 &pcfg_pull_none>, + <5 RK_PB2 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d11 */ - <5 RK_PB3 1 &pcfg_pull_none>, + <5 RK_PB3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d12 */ - <5 RK_PB4 1 &pcfg_pull_none>; + <5 RK_PB4 1 &pcfg_pull_none_drv_level_2_75>; }; /omit-if-no-ref/ bt656_m1_pins: bt656-m1-pins { rockchip,pins = /* vo_lcdc_clk */ - <5 RK_PD3 1 &pcfg_pull_none>, + <5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>, /* vo_lcdc_d13 */ - <5 RK_PB5 1 &pcfg_pull_none>, + <5 RK_PB5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d14 */ - <5 RK_PB6 1 &pcfg_pull_none>, + <5 RK_PB6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d15 */ - <5 RK_PB7 1 &pcfg_pull_none>, + <5 RK_PB7 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d19 */ - <5 RK_PC3 1 &pcfg_pull_none>, + <5 RK_PC3 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d20 */ - <5 RK_PC4 1 &pcfg_pull_none>, + <5 RK_PC4 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d21 */ - <5 RK_PC5 1 &pcfg_pull_none>, + <5 RK_PC5 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d22 */ - <5 RK_PC6 1 &pcfg_pull_none>, + <5 RK_PC6 1 &pcfg_pull_none_drv_level_2_75>, /* vo_lcdc_d23 */ - <5 RK_PC7 1 &pcfg_pull_none>; + <5 RK_PC7 1 &pcfg_pull_none_drv_level_2_75>; }; /omit-if-no-ref/ diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 4015073bbb39..7432329d9d9f 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -819,37 +819,66 @@ static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, u8 *bandwidth) { + u32 max_link_rate; u8 data; int ret; - ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); - if (ret == 1 && data >= DP_EDP_14) { - u32 max_link_rate; + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps + */ + ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); + if (ret < 0) + return ret; - /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ - if (!dp->nr_link_rate_table) { - dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", data); + *bandwidth = data; - ret = analogix_dp_init_link_rate_table(dp); - if (ret) { - dev_err(dp->dev, "failed to read link rate table: %d\n", ret); - return ret; + /* + * As the Table 4-24 in eDP 1.4 spec, the Sink device can only support + * Main-Link rate selection via SUPPORTED_LINK_RATES when the value of + * DPCD MAX_LINK_RATE is 00h. If MAX_LINK_RATE and SUPPORTED_LINK_RATES + * are both non-zero, the Sink device can support both methods. + * + * In practice, if MAX_LINK_RATE is not 00h and SUPPORTED_LINK_RATES + * contains non-zero values, sometimes the sink device can only support + * to set link rate via LINK_BW_SET. In such case, there will be errors + * if set the link rate read from SUPPORTED_LINK_RATES to LINK_RATE_SET. + * + * The panel vendor may explain this is to ensure the same Sink firmware + * remains compatible across different versions of the eDP spec. Or the + * Main-Link rate selection method has not been fully verified. + * + * In order to avoid these unexpected cases, MAX_LINK_RATE/LINK_BW_SET + * method will be selected first if MAX_LINK_RATE is non-zero for eDP + * panels that support 1.4 or higher. + */ + if (*bandwidth == 0) { + ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); + if (ret == 1 && data >= DP_EDP_14) { + /* + * As the Table 4-23 in eDP 1.4 spec, the link rate table is required + * for eDP 1.4 Sink devices. + */ + if (!dp->nr_link_rate_table) { + dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", + data); + + ret = analogix_dp_init_link_rate_table(dp); + if (ret) { + dev_err(dp->dev, "failed to read link rate table: %d\n", + ret); + return ret; + } } + max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; + *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); + } else { + dev_err(dp->dev, "eDP version: 0x%02x MAX_LINK_RATE should be non-zero\n", + data); + return -EINVAL; } - max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; - *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); - } else { - /* - * For DP rev.1.1, Maximum link rate of Main Link lanes - * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps - * For DP rev.1.2, Maximum link rate of Main Link lanes - * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps - */ - ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); - if (ret < 0) - return ret; - - *bandwidth = data; } return 0; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index e30ea74eda67..58d40e5687b2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -772,8 +772,6 @@ static int vop_convert_afbc_format(uint32_t format) DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); return -EINVAL; } - - return -EINVAL; } static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) @@ -4842,7 +4840,7 @@ static void vop_tv_config_update(struct drm_crtc *crtc, if (vop_data->feature & VOP_FEATURE_OUTPUT_10BIT) brightness = interpolate(0, -128, 100, 127, s->tv_state->brightness); - else if (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 6) /* px30 vopb */ + else if (vop->version == VOP_VERSION_PX30_BIG || vop->version >= VOP_VERSION_RK3506) brightness = interpolate(0, -64, 100, 63, s->tv_state->brightness); else brightness = interpolate(0, -32, 100, 31, s->tv_state->brightness); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 2c1b41c5e093..ff5a9316cdbc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2434,8 +2434,6 @@ static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format) DRM_WARN_ONCE("unsupported AFBC format %p4cc\n", &format); return VOP2_AFBC_FMT_INVALID; } - - return VOP2_AFBC_FMT_INVALID; } static enum vop2_tiled_format vop2_convert_tiled_format(uint32_t format) @@ -2460,8 +2458,6 @@ static enum vop2_tiled_format vop2_convert_tiled_format(uint32_t format) DRM_WARN_ONCE("unsupported tiled format %p4cc\n", &format); return VOP2_TILED_FMT_INVALID; } - - return VOP2_TILED_FMT_INVALID; } static enum vop3_tiled_format vop3_convert_tiled_format(uint32_t format, uint32_t tile_mode) @@ -2492,8 +2488,6 @@ static enum vop3_tiled_format vop3_convert_tiled_format(uint32_t format, uint32_ DRM_WARN_ONCE("unsupported tiled format %p4cc\n", &format); return VOP3_TILED_FMT_INVALID; } - - return VOP3_TILED_FMT_INVALID; } static enum vop2_wb_format vop2_convert_wb_format(uint32_t format) @@ -5356,12 +5350,6 @@ static void vop2_disable(struct drm_crtc *crtc) /* Disable axi irq when all vp is disabled */ vop2_axi_disable_irqs(vop2); - /* - * Reset AXI to get a clean state, which is conducive to recovering - * from exceptions when enable at next time(such as iommu page fault) - */ - vop2_clk_reset(vop2->axi_rst); - if (vop2->is_iommu_enabled) { /* * vop2 standby complete, so iommu detach is safe. @@ -5384,6 +5372,12 @@ static void vop2_disable(struct drm_crtc *crtc) if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3576) vop2_power_off_all_pd(vop2); + /* + * Reset AXI to get a clean state, which is conducive to recovering + * from exceptions when enable at next time(such as iommu page fault) + */ + vop2_clk_reset(vop2->axi_rst); + vop2->is_enabled = false; pm_runtime_put_sync(vop2->dev); diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index de46f441b323..7e80542e562e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -47,6 +47,8 @@ #define RV1126B_GRF_VOP_LCDC_CON 0x30b9c #define RV1126B_VOP_MCU_SEL(v) HIWORD_UPDATE(v, 15, 15) +#define RV1126B_VOP_DCLK_DLL_NUM(v) HIWORD_UPDATE(v, 8, 14) +#define RV1126B_VOP_DCLK_DLL_SEL(v) HIWORD_UPDATE(v, 1, 1) #define RK3288_GRF_SOC_CON6 0x025c #define RK3288_LVDS_LCDC_SEL(x) HIWORD_UPDATE(x, 3, 3) @@ -1252,6 +1254,14 @@ static const struct rockchip_rgb_data rv1126_rgb = { static void rv1126b_rgb_enable(struct rockchip_rgb *rgb) { + struct drm_crtc *crtc = rgb->encoder.crtc; + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); + + if (s->output_if == VOP_OUTPUT_IF_BT1120 || s->output_if == VOP_OUTPUT_IF_BT656) { + regmap_write(rgb->grf, RV1126B_GRF_VOP_LCDC_CON, RV1126B_VOP_DCLK_DLL_SEL(1)); + regmap_write(rgb->grf, RV1126B_GRF_VOP_LCDC_CON, RV1126B_VOP_DCLK_DLL_NUM(0x15)); + } + regmap_write(rgb->grf, RV1126B_GRF_VOP_LCDC_CON, RV1126B_VOP_MCU_SEL(rgb->data_sync_bypass)); } diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 787cf7c789dd..427643e37948 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -2001,7 +2001,7 @@ static const struct vop_ctrl rv1126b_ctrl_data = { .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), - .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), + .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0x7f, 0), .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), @@ -2219,7 +2219,7 @@ static const struct vop_ctrl rk3506_ctrl_data = { .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), - .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), + .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0x7f, 0), .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), diff --git a/drivers/media/platform/rockchip/aiisp/aiisp.c b/drivers/media/platform/rockchip/aiisp/aiisp.c index 85591f813469..7a9b77d9d5ff 100644 --- a/drivers/media/platform/rockchip/aiisp/aiisp.c +++ b/drivers/media/platform/rockchip/aiisp/aiisp.c @@ -655,6 +655,9 @@ static int rkaiisp_init_pool(struct rkaiisp_device *aidev, struct rkaiisp_ispbuf if (aidev->exealgo == AIYNR) { stride = ((ispbuf->iir_width + 3) / 4 * 8 * 11 + 7) >> 3; size = stride * (ispbuf->iir_height + 3) / 4; + } else if (aidev->mem_mode == COMBO_MEMODE) { + stride = ((ispbuf->iir_width + 7) / 8 * 15 * 11 + 7) >> 3; + size = stride * (ispbuf->iir_height + 7) / 8; } else { stride = ((ispbuf->iir_width + 1) / 2 * 15 * 11 + 7) >> 3; size = stride * (ispbuf->iir_height + 1) / 2; @@ -1941,6 +1944,13 @@ static long rkaiisp_ioctl_default(struct file *file, void *fh, case RKAIISP_CMD_GET_YNRBUF_INFO: ret = rkaiisp_get_ynrbuf_info(aidev, arg); break; + case RKAIISP_CMD_SET_MEMORY_MODE: { + enum rkaiisp_mem_mode *mem_mode = (enum rkaiisp_mem_mode *)arg; + + aidev->mem_mode = *mem_mode; + ret = 0; + } + break; default: ret = -EINVAL; } diff --git a/drivers/media/platform/rockchip/aiisp/aiisp.h b/drivers/media/platform/rockchip/aiisp/aiisp.h index 7ee816c91a6c..6b5c390fcbf2 100644 --- a/drivers/media/platform/rockchip/aiisp/aiisp.h +++ b/drivers/media/platform/rockchip/aiisp/aiisp.h @@ -147,6 +147,7 @@ struct rkaiisp_device { enum rkaiisp_exemode exemode; enum rkaiisp_model_mode model_mode; enum rkaiisp_hwstate hwstate; + enum rkaiisp_mem_mode mem_mode; u32 para_size; u32 max_runcnt; u32 model_runcnt; diff --git a/include/uapi/linux/rk-aiisp-config.h b/include/uapi/linux/rk-aiisp-config.h index ebbbb8f0b09f..1aab05f8206b 100644 --- a/include/uapi/linux/rk-aiisp-config.h +++ b/include/uapi/linux/rk-aiisp-config.h @@ -35,6 +35,9 @@ #define RKAIISP_CMD_GET_YNRBUF_INFO \ _IOR('V', BASE_VIDIOC_PRIVATE + 5, struct rkaiisp_ynrbuf_info) +#define RKAIISP_CMD_SET_MEMORY_MODE \ + _IOW('V', BASE_VIDIOC_PRIVATE + 6, enum rkaiisp_mem_mode) + /**********************EVENT_PRIVATE***************************/ #define RKAIISP_V4L2_EVENT_AIISP_DONE (V4L2_EVENT_PRIVATE_START + 1) @@ -80,6 +83,11 @@ enum rkaiisp_exemode { BOTHEVENT_IN_KERNEL }; +enum rkaiisp_mem_mode { + SINGLE_MEMODE, + COMBO_MEMODE, +}; + struct rkaiisp_airms_st { int sequence; int inbuf_idx; diff --git a/net/rfkill/rfkill-bt.c b/net/rfkill/rfkill-bt.c index 5efaecd227e6..6b8e8378443a 100644 --- a/net/rfkill/rfkill-bt.c +++ b/net/rfkill/rfkill-bt.c @@ -57,6 +57,7 @@ #define BT_UNBLOCK false #define BT_SLEEP true #define BT_WAKEUP false +#define BT_PORT_NAME_LEN 64 enum { IOMUX_FNORMAL = 0, @@ -72,6 +73,7 @@ struct rfkill_rk_data { struct delayed_work bt_sleep_delay_work; int irq_req; bool enable_power_key; + char btdev_port[BT_PORT_NAME_LEN]; }; static struct rfkill_rk_data *g_rfkill = NULL; @@ -571,6 +573,27 @@ static ssize_t bluesleep_write_proc_powerupkey(struct file *file, return count; } +static ssize_t bluetooth_read_proc_btport(struct file *file, + char __user *buffer, size_t count, loff_t *offset) +{ + struct rfkill_rk_data *rfkill = g_rfkill; + + if (!rfkill) + return -EFAULT; + + return simple_read_from_buffer(buffer, count, offset, rfkill->btdev_port, BT_PORT_NAME_LEN); +} + +static ssize_t bluetooth_write_proc_btport(struct file *file, + const char __user *buffer, size_t count, loff_t *offset) +{ + struct rfkill_rk_data *rfkill = g_rfkill; + + if (!rfkill) + return -EFAULT; + return simple_write_to_buffer(rfkill->btdev_port, BT_PORT_NAME_LEN, offset, buffer, count); +} + #ifdef CONFIG_OF static int bluetooth_platdata_parse_dt(struct device *dev, struct rfkill_rk_platform_data *data) @@ -578,12 +601,20 @@ static int bluetooth_platdata_parse_dt(struct device *dev, struct device_node *node = dev->of_node; int gpio; enum of_gpio_flags flags; + const char *port_name; if (!node) return -ENODEV; memset(data, 0, sizeof(*data)); + if (!of_property_read_string(node, "bt_port", &port_name)) { + strscpy(g_rfkill->btdev_port, port_name, BT_PORT_NAME_LEN); + } else { + LOG("can't get dts bt_port prop"); + g_rfkill->btdev_port[0] = 0x00; + } + if (of_find_property(node, "wifi-bt-power-toggle", NULL)) { data->power_toggle = true; LOG("%s: get property wifi-bt-power-toggle.\n", __func__); @@ -673,6 +704,11 @@ static const struct proc_ops bluesleep_powerupkey = { .proc_write = bluesleep_write_proc_powerupkey, }; +static const struct proc_ops bluetooth_port = { + .proc_read = bluetooth_read_proc_btport, + .proc_write = bluetooth_write_proc_btport, +}; + static int rfkill_rk_register_power_key(struct device *dev) { int ret = 0; @@ -707,6 +743,11 @@ static int rfkill_rk_probe(struct platform_device *pdev) struct proc_dir_entry *ent; DBG("Enter %s\n", __func__); + rfkill = devm_kzalloc(&pdev->dev, sizeof(*rfkill), GFP_KERNEL); + if (!rfkill) + return -ENOMEM; + + g_rfkill = rfkill; if (!pdata) { #ifdef CONFIG_OF @@ -729,13 +770,8 @@ static int rfkill_rk_probe(struct platform_device *pdev) pdata->name = (char *)bt_name; pdata->type = RFKILL_TYPE_BLUETOOTH; - rfkill = devm_kzalloc(&pdev->dev, sizeof(*rfkill), GFP_KERNEL); - if (!rfkill) - return -ENOMEM; - rfkill->pdata = pdata; rfkill->pdev = pdev; - g_rfkill = rfkill; bluetooth_dir = proc_mkdir("bluetooth", NULL); if (!bluetooth_dir) { @@ -743,6 +779,14 @@ static int rfkill_rk_probe(struct platform_device *pdev) return -ENOMEM; } + /* read/write proc entries */ + ent = proc_create("btport", 0660, bluetooth_dir, &bluetooth_port); + if (!ent) { + LOG("Unable to create /proc/%s/btport entry", PROC_DIR); + ret = -ENOMEM; + goto fail_alloc; + } + sleep_dir = proc_mkdir("sleep", bluetooth_dir); if (!sleep_dir) { LOG("Unable to create /proc/%s directory", PROC_DIR);