diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index f44e1295d564..2a365af62770 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -1677,7 +1677,6 @@ static void set_phy_by_mode(unsigned int mode)
 		default:
 			hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb8282);
 			hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x28b0ff3b);
-			hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0800);
 			break;
 		}
 		break;
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
index 4fa293ee04ed..1f79e27472b1 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
@@ -63,13 +63,6 @@
 
 void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 {
-	/*todo */
-	hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 29, 1);
-	hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
-	hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 29, 1);
-	hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
-	hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x3, 24, 2);
-	return;
 	switch (clk) {
 	case 5940000:
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004f7);
@@ -79,7 +72,9 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
@@ -115,7 +110,9 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
index e1b5573a7ddb..c91fa5eff0ce 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
@@ -67,7 +67,7 @@ void init_reg_map(unsigned int type);
 	do {							\
 		unsigned int st = 0, cnt = 10;			\
 		while (cnt--) {                                 \
-			udelay(5);				\
+			udelay(50);				\
 			st = !!(hd_read_reg(reg) & (1 << 31));	\
 			if (st)					\
 				break;				\