mirror of
https://github.com/hardkernel/linux.git
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Merge tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "Lots of work all over, Intel improving DG2 support, amdkfd CRIU support, msm new hw support, and faster fbdev support. dma-buf: - rename dma-buf-map to iosys-map core: - move buddy allocator to core - add pci/platform init macros - improve EDID parser deep color handling - EDID timing type 7 support - add GPD Win Max quirk - add yes/no helpers to string_helpers - flatten syncobj chains - add nomodeset support to lots of drivers - improve fb-helper clipping support - add default property value interface fbdev: - improve fbdev ops speed ttm: - add a backpointer from ttm bo->ttm resource dp: - move displayport headers - add a dp helper module bridge: - anx7625 atomic support, HDCP support panel: - split out panel-lvds and lvds bindings - find panels in OF subnodes privacy: - add chromeos privacy screen support fb: - hot unplug fw fb on forced removal simpledrm: - request region instead of marking ioresource busy - add panel oreintation property udmabuf: - fix oops with 0 pages amdgpu: - power management code cleanup - Enable freesync video mode by default - RAS code cleanup - Improve VRAM access for debug using SDMA - SR-IOV rework special register access and fixes - profiling power state request ioctl - expose IP discovery via sysfs - Cyan skillfish updates - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates - expose benchmark tests via debugfs - add module param to disable XGMI for testing - GPU reset debugfs register dumping support amdkfd: - CRIU support - SDMA queue fixes radeon: - UVD suspend fix - iMac backlight fix i915: - minimal parallel submission for execlists - DG2-G12 subplatform added - DG2 programming workarounds - DG2 accelerated migration support - flat CCS and CCS engine support for XeHP - initial small BAR support - drop fake LMEM support - ADL-N PCH support - bigjoiner updates - introduce VMA resources and async unbinding - register definitions cleanups - multi-FBC refactoring - DG1 OPROM over SPI support - ADL-N platform enabling - opregion mailbox #5 support - DP MST ESI improvements - drm device based logging - async flip optimisation for DG2 - CPU arch abstraction fixes - improve GuC ADS init to work on aarch64 - tweak TTM LRU priority hint - GuC 69.0.3 support - remove short term execbuf pins nouveau: - higher DP/eDP bitrates - backlight fixes msm: - dpu + dp support for sc8180x - dp support for sm8350 - dpu + dsi support for qcm2290 - 10nm dsi phy tuning support - bridge support for dp encoder - gpu support for additional 7c3 SKUs ingenic: - HDMI support for JZ4780 - aux channel EDID support ast: - AST2600 support - add wide screen support - create DP/DVI connectors omapdrm: - fix implicit dma_buf fencing vc4: - add CSC + full range support - better display firmware handoff panfrost: - add initial dual-core GPU support stm: - new revision support - fb handover support mediatek: - transfer display binding document to yaml format. - add mt8195 display device binding. - allow commands to be sent during video mode. - add wait_for_event for crtc disable by cmdq. tegra: - YUV format support rcar-du: - LVDS support for M3-W+ (R8A77961) exynos: - BGR pixel format for FIMD device" * tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm: (1529 commits) drm/i915/display: Do not re-enable PSR after it was marked as not reliable drm/i915/display: Fix HPD short pulse handling for eDP drm/amdgpu: Use drm_mode_copy() drm/radeon: Use drm_mode_copy() drm/amdgpu: Use ternary operator in `vcn_v1_0_start()` drm/amdgpu: Remove pointless on stack mode copies drm/amd/pm: fix indenting in __smu_cmn_reg_print_error() drm/amdgpu/dc: fix typos in comments drm/amdgpu: fix typos in comments drm/amd/pm: fix typos in comments drm/amdgpu: Add stolen reserved memory for MI25 SRIOV. drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations. drm/amdkfd: evict svm bo worker handle error drm/amdgpu/vcn: fix vcn ring test failure in igt reload test drm/amdgpu: only allow secure submission on rings which support that drm/amdgpu: fixed the warnings reported by kernel test robot drm/amd/display: 3.2.177 drm/amd/display: [FW Promotion] Release 0.0.108.0 drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2 drm/amd/display: Wait for hubp read line for Pollock ...
This commit is contained in:
Linus Torvalds
@@ -206,6 +206,8 @@ union drm_amdgpu_bo_list {
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#define AMDGPU_CTX_OP_FREE_CTX 2
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#define AMDGPU_CTX_OP_QUERY_STATE 3
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#define AMDGPU_CTX_OP_QUERY_STATE2 4
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#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
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#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
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/* GPU reset status */
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#define AMDGPU_CTX_NO_RESET 0
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@@ -238,10 +240,18 @@ union drm_amdgpu_bo_list {
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#define AMDGPU_CTX_PRIORITY_HIGH 512
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#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
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/* select a stable profiling pstate for perfmon tools */
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#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
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#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
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#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
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#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
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#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
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#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
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struct drm_amdgpu_ctx_in {
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/** AMDGPU_CTX_OP_* */
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__u32 op;
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/** For future use, no flags defined so far */
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/** Flags */
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__u32 flags;
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__u32 ctx_id;
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/** AMDGPU_CTX_PRIORITY_* */
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@@ -262,6 +272,11 @@ union drm_amdgpu_ctx_out {
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/** Reset status since the last call of the ioctl. */
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__u32 reset_status;
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} state;
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struct {
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__u32 flags;
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__u32 _pad;
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} pstate;
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};
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union drm_amdgpu_ctx {
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@@ -728,6 +743,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_DMCUB 0x14
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/* Subquery id: Query TOC firmware version */
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#define AMDGPU_INFO_FW_TOC 0x15
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/* Subquery id: Query CAP firmware version */
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#define AMDGPU_INFO_FW_CAP 0x16
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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@@ -1134,6 +1151,8 @@ struct drm_amdgpu_info_video_caps {
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#define AMDGPU_FAMILY_NV 143 /* Navi10 */
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#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
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#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
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#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
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#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
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#if defined(__cplusplus)
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}
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@@ -663,41 +663,73 @@ struct drm_mode_fb_cmd {
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#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
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#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
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/**
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* struct drm_mode_fb_cmd2 - Frame-buffer metadata.
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*
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* This struct holds frame-buffer metadata. There are two ways to use it:
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*
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* - User-space can fill this struct and perform a &DRM_IOCTL_MODE_ADDFB2
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* ioctl to register a new frame-buffer. The new frame-buffer object ID will
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* be set by the kernel in @fb_id.
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* - User-space can set @fb_id and perform a &DRM_IOCTL_MODE_GETFB2 ioctl to
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* fetch metadata about an existing frame-buffer.
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*
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* In case of planar formats, this struct allows up to 4 buffer objects with
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* offsets and pitches per plane. The pitch and offset order is dictated by the
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* format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as:
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*
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* YUV 4:2:0 image with a plane of 8 bit Y samples followed by an
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* interleaved U/V plane containing 8 bit 2x2 subsampled colour difference
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* samples.
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*
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* So it would consist of a Y plane at ``offsets[0]`` and a UV plane at
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* ``offsets[1]``.
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*
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* To accommodate tiled, compressed, etc formats, a modifier can be specified.
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* For more information see the "Format Modifiers" section. Note that even
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* though it looks like we have a modifier per-plane, we in fact do not. The
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* modifier for each plane must be identical. Thus all combinations of
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* different data layouts for multi-plane formats must be enumerated as
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* separate modifiers.
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*
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* All of the entries in @handles, @pitches, @offsets and @modifier must be
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* zero when unused. Warning, for @offsets and @modifier zero can't be used to
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* figure out whether the entry is used or not since it's a valid value (a zero
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* offset is common, and a zero modifier is &DRM_FORMAT_MOD_LINEAR).
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*/
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struct drm_mode_fb_cmd2 {
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/** @fb_id: Object ID of the frame-buffer. */
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__u32 fb_id;
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/** @width: Width of the frame-buffer. */
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__u32 width;
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/** @height: Height of the frame-buffer. */
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__u32 height;
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__u32 pixel_format; /* fourcc code from drm_fourcc.h */
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__u32 flags; /* see above flags */
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/**
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* @pixel_format: FourCC format code, see ``DRM_FORMAT_*`` constants in
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* ``drm_fourcc.h``.
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*/
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__u32 pixel_format;
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/**
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* @flags: Frame-buffer flags (see &DRM_MODE_FB_INTERLACED and
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* &DRM_MODE_FB_MODIFIERS).
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*/
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__u32 flags;
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/*
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* In case of planar formats, this ioctl allows up to 4
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* buffer objects with offsets and pitches per plane.
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* The pitch and offset order is dictated by the fourcc,
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* e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as:
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*
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* YUV 4:2:0 image with a plane of 8 bit Y samples
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* followed by an interleaved U/V plane containing
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* 8 bit 2x2 subsampled colour difference samples.
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*
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* So it would consist of Y as offsets[0] and UV as
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* offsets[1]. Note that offsets[0] will generally
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* be 0 (but this is not required).
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*
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* To accommodate tiled, compressed, etc formats, a
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* modifier can be specified. The default value of zero
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* indicates "native" format as specified by the fourcc.
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* Vendor specific modifier token. Note that even though
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* it looks like we have a modifier per-plane, we in fact
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* do not. The modifier for each plane must be identical.
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* Thus all combinations of different data layouts for
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* multi plane formats must be enumerated as separate
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* modifiers.
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/**
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* @handles: GEM buffer handle, one per plane. Set to 0 if the plane is
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* unused. The same handle can be used for multiple planes.
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*/
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__u32 handles[4];
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__u32 pitches[4]; /* pitch for each plane */
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__u32 offsets[4]; /* offset of each plane */
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__u64 modifier[4]; /* ie, tiling, compress */
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/** @pitches: Pitch (aka. stride) in bytes, one per plane. */
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__u32 pitches[4];
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/** @offsets: Offset into the buffer in bytes, one per plane. */
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__u32 offsets[4];
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/**
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* @modifier: Format modifier, one per plane. See ``DRM_FORMAT_MOD_*``
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* constants in ``drm_fourcc.h``. All planes must use the same
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* modifier. Ignored unless &DRM_MODE_FB_MODIFIERS is set in @flags.
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*/
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__u64 modifier[4];
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};
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#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
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@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
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/**
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* When the EXEC_OBJECT_PINNED flag is specified this is populated by
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* the user with the GTT offset at which this object will be pinned.
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*
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* When the I915_EXEC_NO_RELOC flag is specified this must contain the
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* presumed_offset of the object.
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*
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* During execbuffer2 the kernel populates it with the value of the
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* current GTT offset of the object, for future presumed_offset writes.
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*
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* See struct drm_i915_gem_create_ext for the rules when dealing with
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* alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
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* minimum page sizes, like DG2.
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*/
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__u64 offset;
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@@ -3144,11 +3150,40 @@ struct drm_i915_gem_create_ext {
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*
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* The (page-aligned) allocated size for the object will be returned.
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*
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* Note that for some devices we have might have further minimum
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* page-size restrictions(larger than 4K), like for device local-memory.
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* However in general the final size here should always reflect any
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* rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
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* extension to place the object in device local-memory.
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*
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* DG2 64K min page size implications:
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*
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* On discrete platforms, starting from DG2, we have to contend with GTT
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* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
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* objects. Specifically the hardware only supports 64K or larger GTT
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* page sizes for such memory. The kernel will already ensure that all
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* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
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* sizes underneath.
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*
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* Note that the returned size here will always reflect any required
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* rounding up done by the kernel, i.e 4K will now become 64K on devices
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* such as DG2.
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*
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* Special DG2 GTT address alignment requirement:
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*
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* The GTT alignment will also need to be at least 2M for such objects.
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*
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* Note that due to how the hardware implements 64K GTT page support, we
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* have some further complications:
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*
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* 1) The entire PDE (which covers a 2MB virtual address range), must
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* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
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* PDE is forbidden by the hardware.
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*
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* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
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* objects.
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*
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* To keep things simple for userland, we mandate that any GTT mappings
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* must be aligned to and rounded up to 2MB. The kernel will internally
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* pad them out to the next 2MB boundary. As this only wastes virtual
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* address space and avoids userland having to copy any needlessly
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* complicated PDE sharing scheme (coloring) and only affects DG2, this
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* is deemed to be a good compromise.
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*/
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__u64 size;
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/**
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@@ -67,16 +67,21 @@ struct drm_msm_timespec {
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__s64 tv_nsec; /* nanoseconds */
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};
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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#define MSM_PARAM_CHIP_ID 0x03
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#define MSM_PARAM_MAX_FREQ 0x04
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#define MSM_PARAM_TIMESTAMP 0x05
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#define MSM_PARAM_GMEM_BASE 0x06
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#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */
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#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
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#define MSM_PARAM_FAULTS 0x09
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#define MSM_PARAM_SUSPENDS 0x0a
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/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
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* "RW" indicates a param that can be both read (GET_PARAM) and written
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* (SET_PARAM)
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*/
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#define MSM_PARAM_GPU_ID 0x01 /* RO */
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#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
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#define MSM_PARAM_CHIP_ID 0x03 /* RO */
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#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
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#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
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#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
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#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
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#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
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#define MSM_PARAM_FAULTS 0x09 /* RO */
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#define MSM_PARAM_SUSPENDS 0x0a /* RO */
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#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
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/* For backwards compat. The original support for preemption was based on
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* a single ring per priority level so # of priority levels equals the #
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@@ -227,6 +232,7 @@ struct drm_msm_gem_submit_bo {
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#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
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#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
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#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
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#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
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#define MSM_SUBMIT_FLAGS ( \
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MSM_SUBMIT_NO_IMPLICIT | \
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MSM_SUBMIT_FENCE_FD_IN | \
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@@ -234,6 +240,7 @@ struct drm_msm_gem_submit_bo {
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MSM_SUBMIT_SUDO | \
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MSM_SUBMIT_SYNCOBJ_IN | \
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MSM_SUBMIT_SYNCOBJ_OUT | \
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MSM_SUBMIT_FENCE_SN_IN | \
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0)
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#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
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@@ -253,7 +260,7 @@ struct drm_msm_gem_submit_syncobj {
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*/
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struct drm_msm_gem_submit {
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__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
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__u32 fence; /* out */
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__u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
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__u32 nr_bos; /* in, number of submit_bo's */
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__u32 nr_cmds; /* in, number of submit_cmd's */
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__u64 bos; /* in, ptr to array of submit_bo's */
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@@ -333,9 +340,7 @@ struct drm_msm_submitqueue_query {
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};
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#define DRM_MSM_GET_PARAM 0x00
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/* placeholder:
|
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#define DRM_MSM_SET_PARAM 0x01
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*/
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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#define DRM_MSM_GEM_CPU_PREP 0x04
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@@ -351,6 +356,7 @@ struct drm_msm_submitqueue_query {
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#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
|
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|
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@@ -84,14 +84,14 @@ struct drm_panfrost_wait_bo {
|
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__s64 timeout_ns; /* absolute */
|
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};
|
||||
|
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/* Valid flags to pass to drm_panfrost_create_bo */
|
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#define PANFROST_BO_NOEXEC 1
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#define PANFROST_BO_HEAP 2
|
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|
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/**
|
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* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
|
||||
*
|
||||
* There are currently no values for the flags argument, but it may be
|
||||
* used in a future extension.
|
||||
* The flags argument is a bit mask of PANFROST_BO_* flags.
|
||||
*/
|
||||
struct drm_panfrost_create_bo {
|
||||
__u32 size;
|
||||
|
||||
@@ -32,9 +32,11 @@
|
||||
* - 1.4 - Indicate new SRAM EDC bit in device properties
|
||||
* - 1.5 - Add SVM API
|
||||
* - 1.6 - Query clear flags in SVM get_attr API
|
||||
* - 1.7 - Checkpoint Restore (CRIU) API
|
||||
* - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
|
||||
*/
|
||||
#define KFD_IOCTL_MAJOR_VERSION 1
|
||||
#define KFD_IOCTL_MINOR_VERSION 6
|
||||
#define KFD_IOCTL_MINOR_VERSION 8
|
||||
|
||||
struct kfd_ioctl_get_version_args {
|
||||
__u32 major_version; /* from KFD */
|
||||
@@ -194,6 +196,8 @@ struct kfd_ioctl_dbg_wave_control_args {
|
||||
__u32 buf_size_in_bytes; /*including gpu_id and buf_size */
|
||||
};
|
||||
|
||||
#define KFD_INVALID_FD 0xffffffff
|
||||
|
||||
/* Matching HSA_EVENTTYPE */
|
||||
#define KFD_IOC_EVENT_SIGNAL 0
|
||||
#define KFD_IOC_EVENT_NODECHANGE 1
|
||||
@@ -462,12 +466,89 @@ enum kfd_smi_event {
|
||||
};
|
||||
|
||||
#define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
|
||||
#define KFD_SMI_EVENT_MSG_SIZE 96
|
||||
|
||||
struct kfd_ioctl_smi_events_args {
|
||||
__u32 gpuid; /* to KFD */
|
||||
__u32 anon_fd; /* from KFD */
|
||||
};
|
||||
|
||||
/**************************************************************************************************
|
||||
* CRIU IOCTLs (Checkpoint Restore In Userspace)
|
||||
*
|
||||
* When checkpointing a process, the userspace application will perform:
|
||||
* 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts
|
||||
* all the queues.
|
||||
* 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges)
|
||||
* 3. UNPAUSE op to un-evict all the queues
|
||||
*
|
||||
* When restoring a process, the CRIU userspace application will perform:
|
||||
*
|
||||
* 1. RESTORE op to restore process contents
|
||||
* 2. RESUME op to start the process
|
||||
*
|
||||
* Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User
|
||||
* application needs to perform an UNPAUSE operation after calling PROCESS_INFO.
|
||||
*/
|
||||
|
||||
enum kfd_criu_op {
|
||||
KFD_CRIU_OP_PROCESS_INFO,
|
||||
KFD_CRIU_OP_CHECKPOINT,
|
||||
KFD_CRIU_OP_UNPAUSE,
|
||||
KFD_CRIU_OP_RESTORE,
|
||||
KFD_CRIU_OP_RESUME,
|
||||
};
|
||||
|
||||
/**
|
||||
* kfd_ioctl_criu_args - Arguments perform CRIU operation
|
||||
* @devices: [in/out] User pointer to memory location for devices information.
|
||||
* This is an array of type kfd_criu_device_bucket.
|
||||
* @bos: [in/out] User pointer to memory location for BOs information
|
||||
* This is an array of type kfd_criu_bo_bucket.
|
||||
* @priv_data: [in/out] User pointer to memory location for private data
|
||||
* @priv_data_size: [in/out] Size of priv_data in bytes
|
||||
* @num_devices: [in/out] Number of GPUs used by process. Size of @devices array.
|
||||
* @num_bos [in/out] Number of BOs used by process. Size of @bos array.
|
||||
* @num_objects: [in/out] Number of objects used by process. Objects are opaque to
|
||||
* user application.
|
||||
* @pid: [in/out] PID of the process being checkpointed
|
||||
* @op [in] Type of operation (kfd_criu_op)
|
||||
*
|
||||
* Return: 0 on success, -errno on failure
|
||||
*/
|
||||
struct kfd_ioctl_criu_args {
|
||||
__u64 devices; /* Used during ops: CHECKPOINT, RESTORE */
|
||||
__u64 bos; /* Used during ops: CHECKPOINT, RESTORE */
|
||||
__u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */
|
||||
__u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */
|
||||
__u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */
|
||||
__u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */
|
||||
__u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */
|
||||
__u32 pid; /* Used during ops: PROCESS_INFO, RESUME */
|
||||
__u32 op;
|
||||
};
|
||||
|
||||
struct kfd_criu_device_bucket {
|
||||
__u32 user_gpu_id;
|
||||
__u32 actual_gpu_id;
|
||||
__u32 drm_fd;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct kfd_criu_bo_bucket {
|
||||
__u64 addr;
|
||||
__u64 size;
|
||||
__u64 offset;
|
||||
__u64 restored_offset; /* During restore, updated offset for BO */
|
||||
__u32 gpu_id; /* This is the user_gpu_id */
|
||||
__u32 alloc_flags;
|
||||
__u32 dmabuf_fd;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/* CRIU IOCTLs - END */
|
||||
/**************************************************************************************************/
|
||||
|
||||
/* Register offset inside the remapped mmio page
|
||||
*/
|
||||
enum kfd_mmio_remap {
|
||||
@@ -596,7 +677,7 @@ struct kfd_ioctl_svm_args {
|
||||
__u32 op;
|
||||
__u32 nattr;
|
||||
/* Variable length array of attributes */
|
||||
struct kfd_ioctl_svm_attribute attrs[0];
|
||||
struct kfd_ioctl_svm_attribute attrs[];
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -679,16 +760,16 @@ struct kfd_ioctl_set_xnack_mode_args {
|
||||
#define AMDKFD_IOC_WAIT_EVENTS \
|
||||
AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
|
||||
|
||||
#define AMDKFD_IOC_DBG_REGISTER \
|
||||
#define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \
|
||||
AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
|
||||
|
||||
#define AMDKFD_IOC_DBG_UNREGISTER \
|
||||
#define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \
|
||||
AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
|
||||
|
||||
#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
|
||||
#define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \
|
||||
AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
|
||||
|
||||
#define AMDKFD_IOC_DBG_WAVE_CONTROL \
|
||||
#define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \
|
||||
AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
|
||||
|
||||
#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
|
||||
@@ -742,7 +823,10 @@ struct kfd_ioctl_set_xnack_mode_args {
|
||||
#define AMDKFD_IOC_SET_XNACK_MODE \
|
||||
AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args)
|
||||
|
||||
#define AMDKFD_IOC_CRIU_OP \
|
||||
AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args)
|
||||
|
||||
#define AMDKFD_COMMAND_START 0x01
|
||||
#define AMDKFD_COMMAND_END 0x22
|
||||
#define AMDKFD_COMMAND_END 0x23
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user