From b16cbb21d7fbf495038fbe40f2bdd250c1d34071 Mon Sep 17 00:00:00 2001 From: Luo Wei Date: Fri, 15 Nov 2024 18:56:40 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3576-vehicle-evb: edp-vp0 use vpll default Signed-off-by: Luo Wei Change-Id: If69dd8af979156aeb6d1ca575592fcfbaab7cac8 --- .../rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi | 7 ++++++- .../rockchip/rk3576-vehicle-serdes-mfd-display-maxim.dtsi | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi index 5d61d53f29ee..9705b8822547 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi @@ -1696,9 +1696,14 @@ assigned-clock-rates = <1150000000>; }; +//edp +&vp0 { + assigned-clocks = <&cru DCLK_VP0_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + //dsi &vp1 { assigned-clocks = <&cru DCLK_VP1_SRC>; assigned-clock-parents = <&cru PLL_VPLL>; }; - diff --git a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-serdes-mfd-display-maxim.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-serdes-mfd-display-maxim.dtsi index 434ce162f879..53d377081ab1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-serdes-mfd-display-maxim.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-serdes-mfd-display-maxim.dtsi @@ -1696,9 +1696,14 @@ assigned-clock-rates = <1150000000>; }; +//edp +&vp0 { + assigned-clocks = <&cru DCLK_VP0_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + //dsi &vp1 { assigned-clocks = <&cru DCLK_VP1_SRC>; assigned-clock-parents = <&cru PLL_VPLL>; }; -