From b1b915251b4a66fb8d80238ffbda58b366704be1 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 27 Nov 2017 15:09:07 +0800 Subject: [PATCH] clk: rockchip: rk3288: Add ids for pclk_vip_in and pclk_vip Change-Id: Id7c4b9a69ca22ae5eaee75929adb5ec0c1f0165c Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3288.c | 4 ++-- include/dt-bindings/clock/rk3288-cru.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index e5c8dfccc7cc..acc1af8eb48a 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -799,8 +799,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { * Other ungrouped clocks. */ - GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS), - INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS), + GATE(PCLK_VIP_IN, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS), + INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS), GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), }; diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 33a645ec1c86..b60ced10d3f2 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -174,6 +174,8 @@ #define PCLK_EFUSE256 369 #define PCLK_EFUSE1024 370 #define PCLK_ISP_IN 371 +#define PCLK_VIP 372 +#define PCLK_VIP_IN 373 /* hclk gates */ #define HCLK_GPS 448