From b20870d86912eb8020d86b893076785b2dadca22 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 26 Jun 2023 15:01:20 +0800 Subject: [PATCH] nvme-pci: add NVME_QUIRK_LIMIT_IOQD32 to fix Phison E15 NVMe controller Phison E15 NVMe controller is known to be broken when doing a high loading test. Limit io queue depth to 32 is suggested by vendor. Signed-off-by: Shawn Lin Change-Id: Ie2a89197311a6a7b59281ff12caf545ae0ab37bf --- drivers/nvme/host/nvme.h | 5 +++++ drivers/nvme/host/pci.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h index 86336496c65c..9324a38ac871 100644 --- a/drivers/nvme/host/nvme.h +++ b/drivers/nvme/host/nvme.h @@ -155,6 +155,11 @@ enum nvme_quirks { * Reports garbage in the namespace identifiers (eui64, nguid, uuid). */ NVME_QUIRK_BOGUS_NID = (1 << 18), + + /* + * Limit io queue depth to 32 + */ + NVME_QUIRK_LIMIT_IOQD32 = (1 << 31), }; /* diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index c222d7bf6ce1..0cefbe95ed88 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2394,6 +2394,9 @@ static int nvme_pci_enable(struct nvme_dev *dev) dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); + if (dev->ctrl.quirks & NVME_QUIRK_LIMIT_IOQD32) + io_queue_depth = 32; + dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, io_queue_depth); dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ @@ -3236,6 +3239,8 @@ static const struct pci_device_id nvme_id_table[] = { .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | NVME_QUIRK_DISABLE_WRITE_ZEROES| NVME_QUIRK_IGNORE_DEV_SUBNQN, }, + { PCI_DEVICE(0x1987, 0x5013), /* Phison E13 */ + .driver_data = NVME_QUIRK_LIMIT_IOQD32}, { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | NVME_QUIRK_BOGUS_NID, },