From b20b529fc13f61af657c913e70e82295edbcc183 Mon Sep 17 00:00:00 2001 From: Wu Liangqing Date: Wed, 26 Feb 2020 09:41:38 +0800 Subject: [PATCH] arm64: rockchip: px30: remove firmware_android and support ddr4 board Change-Id: I3b73f79f47fc2b3f73cb04ddf76af4e7c055c12a Signed-off-by: Wu Liangqing --- .../dts/rockchip/px30-ddr4p416dd6-timing.dtsi | 216 ++++++++++++++++++ .../dts/rockchip/px30-evb-ddr3-v10-avb.dts | 20 +- .../boot/dts/rockchip/px30-evb-ddr4-v10.dts | 44 ++-- 3 files changed, 237 insertions(+), 43 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/px30-ddr4p416dd6-timing.dtsi diff --git a/arch/arm64/boot/dts/rockchip/px30-ddr4p416dd6-timing.dtsi b/arch/arm64/boot/dts/rockchip/px30-ddr4p416dd6-timing.dtsi new file mode 100644 index 000000000000..fde5895db94a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ddr4p416dd6-timing.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +&ddr_timing { + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <0>; + ddr3a0_ddr4a10_de-skew = <5>; + ddr3a3_ddr4a6_de-skew = <2>; + ddr3a2_ddr4a4_de-skew = <4>; + ddr3a5_ddr4a8_de-skew = <2>; + ddr3a4_ddr4a5_de-skew = <1>; + ddr3a7_ddr4a11_de-skew = <2>; + ddr3a6_ddr4a7_de-skew = <0>; + ddr3a9_ddr4a0_de-skew = <4>; + ddr3a8_ddr4a13_de-skew = <0>; + ddr3a11_ddr4a3_de-skew = <4>; + ddr3a10_ddr4cs0_de-skew = <5>; + ddr3a13_ddr4a2_de-skew = <2>; + ddr3a12_ddr4ba1_de-skew = <2>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <4>; + ddr3ba1_ddr4a15_de-skew = <3>; + ddr3ba0_ddr4bg0_de-skew = <4>; + ddr3ras_ddr4cke_de-skew = <6>; + ddr3ba2_ddr4ba0_de-skew = <3>; + ddr3we_ddr4bg1_de-skew = <3>; + ddr3cas_ddr4a12_de-skew = <6>; + ddr3ckn_ddr4ckn_de-skew = <8>; + ddr3ckp_ddr4ckp_de-skew = <8>; + ddr3cke_ddr4a16_de-skew = <4>; + ddr3odt0_ddr4a14_de-skew = <4>; + ddr3cs0_ddr4act_de-skew = <7>; + ddr3reset_ddr4reset_de-skew = <3>; + ddr3cs1_ddr4cs1_de-skew = <5>; + ddr3odt1_ddr4odt1_de-skew = <6>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <9>; + cs0_dq0_rx_de-skew = <10>; + cs0_dq0_tx_de-skew = <10>; + cs0_dq1_rx_de-skew = <11>; + cs0_dq1_tx_de-skew = <10>; + cs0_dq2_rx_de-skew = <8>; + cs0_dq2_tx_de-skew = <10>; + cs0_dq3_rx_de-skew = <9>; + cs0_dq3_tx_de-skew = <9>; + cs0_dq4_rx_de-skew = <10>; + cs0_dq4_tx_de-skew = <10>; + cs0_dq5_rx_de-skew = <10>; + cs0_dq5_tx_de-skew = <10>; + cs0_dq6_rx_de-skew = <10>; + cs0_dq6_tx_de-skew = <10>; + cs0_dq7_rx_de-skew = <10>; + cs0_dq7_tx_de-skew = <10>; + cs0_dqs0_rx_de-skew = <5>; + cs0_dqs0p_tx_de-skew = <11>; + cs0_dqs0n_tx_de-skew = <11>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <9>; + cs0_dq8_rx_de-skew = <8>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <10>; + cs0_dq9_tx_de-skew = <9>; + cs0_dq10_rx_de-skew = <8>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <9>; + cs0_dq11_tx_de-skew = <10>; + cs0_dq12_rx_de-skew = <9>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <8>; + cs0_dq13_tx_de-skew = <9>; + cs0_dq14_rx_de-skew = <9>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <9>; + cs0_dq15_tx_de-skew = <9>; + cs0_dqs1_rx_de-skew = <5>; + cs0_dqs1p_tx_de-skew = <11>; + cs0_dqs1n_tx_de-skew = <11>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <10>; + cs0_dq16_rx_de-skew = <10>; + cs0_dq16_tx_de-skew = <9>; + cs0_dq17_rx_de-skew = <10>; + cs0_dq17_tx_de-skew = <9>; + cs0_dq18_rx_de-skew = <9>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <10>; + cs0_dq19_tx_de-skew = <9>; + cs0_dq20_rx_de-skew = <10>; + cs0_dq20_tx_de-skew = <10>; + cs0_dq21_rx_de-skew = <10>; + cs0_dq21_tx_de-skew = <9>; + cs0_dq22_rx_de-skew = <9>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <10>; + cs0_dq23_tx_de-skew = <9>; + cs0_dqs2_rx_de-skew = <5>; + cs0_dqs2p_tx_de-skew = <10>; + cs0_dqs2n_tx_de-skew = <10>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <9>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <9>; + cs0_dq25_tx_de-skew = <8>; + cs0_dq26_rx_de-skew = <9>; + cs0_dq26_tx_de-skew = <8>; + cs0_dq27_rx_de-skew = <9>; + cs0_dq27_tx_de-skew = <9>; + cs0_dq28_rx_de-skew = <9>; + cs0_dq28_tx_de-skew = <9>; + cs0_dq29_rx_de-skew = <9>; + cs0_dq29_tx_de-skew = <9>; + cs0_dq30_rx_de-skew = <10>; + cs0_dq30_tx_de-skew = <9>; + cs0_dq31_rx_de-skew = <10>; + cs0_dq31_tx_de-skew = <9>; + cs0_dqs3_rx_de-skew = <6>; + cs0_dqs3p_tx_de-skew = <10>; + cs0_dqs3n_tx_de-skew = <10>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <9>; + cs1_dq0_rx_de-skew = <10>; + cs1_dq0_tx_de-skew = <10>; + cs1_dq1_rx_de-skew = <11>; + cs1_dq1_tx_de-skew = <10>; + cs1_dq2_rx_de-skew = <8>; + cs1_dq2_tx_de-skew = <10>; + cs1_dq3_rx_de-skew = <9>; + cs1_dq3_tx_de-skew = <9>; + cs1_dq4_rx_de-skew = <10>; + cs1_dq4_tx_de-skew = <10>; + cs1_dq5_rx_de-skew = <10>; + cs1_dq5_tx_de-skew = <10>; + cs1_dq6_rx_de-skew = <10>; + cs1_dq6_tx_de-skew = <10>; + cs1_dq7_rx_de-skew = <10>; + cs1_dq7_tx_de-skew = <10>; + cs1_dqs0_rx_de-skew = <5>; + cs1_dqs0p_tx_de-skew = <11>; + cs1_dqs0n_tx_de-skew = <11>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <9>; + cs1_dq8_rx_de-skew = <8>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <10>; + cs1_dq9_tx_de-skew = <9>; + cs1_dq10_rx_de-skew = <8>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <9>; + cs1_dq11_tx_de-skew = <10>; + cs1_dq12_rx_de-skew = <9>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <8>; + cs1_dq13_tx_de-skew = <9>; + cs1_dq14_rx_de-skew = <9>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <9>; + cs1_dq15_tx_de-skew = <9>; + cs1_dqs1_rx_de-skew = <5>; + cs1_dqs1p_tx_de-skew = <11>; + cs1_dqs1n_tx_de-skew = <11>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <10>; + cs1_dq16_rx_de-skew = <10>; + cs1_dq16_tx_de-skew = <9>; + cs1_dq17_rx_de-skew = <10>; + cs1_dq17_tx_de-skew = <9>; + cs1_dq18_rx_de-skew = <9>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <10>; + cs1_dq19_tx_de-skew = <9>; + cs1_dq20_rx_de-skew = <10>; + cs1_dq20_tx_de-skew = <10>; + cs1_dq21_rx_de-skew = <10>; + cs1_dq21_tx_de-skew = <9>; + cs1_dq22_rx_de-skew = <9>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <10>; + cs1_dq23_tx_de-skew = <9>; + cs1_dqs2_rx_de-skew = <5>; + cs1_dqs2p_tx_de-skew = <10>; + cs1_dqs2n_tx_de-skew = <10>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <9>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <9>; + cs1_dq25_tx_de-skew = <8>; + cs1_dq26_rx_de-skew = <9>; + cs1_dq26_tx_de-skew = <8>; + cs1_dq27_rx_de-skew = <9>; + cs1_dq27_tx_de-skew = <9>; + cs1_dq28_rx_de-skew = <9>; + cs1_dq28_tx_de-skew = <9>; + cs1_dq29_rx_de-skew = <9>; + cs1_dq29_tx_de-skew = <9>; + cs1_dq30_rx_de-skew = <10>; + cs1_dq30_tx_de-skew = <9>; + cs1_dq31_rx_de-skew = <10>; + cs1_dq31_tx_de-skew = <9>; + cs1_dqs3_rx_de-skew = <6>; + cs1_dqs3p_tx_de-skew = <10>; + cs1_dqs3n_tx_de-skew = <10>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts index 1a9eedcb328c..f55c0cad179f 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10-avb.dts @@ -11,22 +11,6 @@ compatible = "rockchip,px30-evb-ddr3-v10-avb", "rockchip,px30"; }; -&firmware_android { - compatible = "android,firmware"; - boot_devices = "ff390000.dwmmc,ff3b0000.nandc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; +&chosen { + bootargs_ext = "androidboot.boot_devices=ff390000.dwmmc,ff3b0000.nandc"; }; - diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts index 792057d68b00..4ceb01d3d916 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts @@ -12,7 +12,7 @@ #include #include "px30.dtsi" #include "px30-android.dtsi" - +#include "px30-ddr4p416dd6-timing.dtsi" / { model = "Rockchip PX30 evb ddr4 board"; compatible = "rockchip,px30-evb-ddr4-v10", "rockchip,px30"; @@ -79,7 +79,7 @@ 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 + 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 @@ -274,6 +274,10 @@ }; }; +&chosen { + bootargs_ext = "androidboot.boot_devices=ff390000.dwmmc,ff3b0000.nandc"; +}; + &dsi_in_vopb { status = "okay"; }; @@ -296,6 +300,15 @@ cpu-supply = <&vdd_arm>; }; +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -441,13 +454,13 @@ vcc_1v0: LDO_REG1 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; regulator-initial-mode = <0x1>; regulator-name = "vcc_1v0"; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; + regulator-suspend-microvolt = <2500000>; }; }; @@ -608,6 +621,7 @@ gt1x: gt1x@14 { compatible = "goodix,gt1x"; reg = <0x14>; + power-supply = <&vcc3v3_lcd>; goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; }; @@ -810,23 +824,3 @@ status = "okay"; }; -&firmware_android { - compatible = "android,firmware"; - fstab { - compatible = "android,fstab"; - system { - compatible = "android,system"; - dev = "/dev/block/by-name/system"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait"; - }; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait"; - }; - }; -};