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clk: tl1: fix stack overflow when set rate for dsu clock [1/1]
PD#SWPL-8546 Problem: stack overflow Solution: remove clk_set_rate in dsu clock notifier Verify: tl1 X301 Change-Id: Ie4b2fe929446ade505c714d11c1474146d188ac2 Signed-off-by: Sandy Luo <sandy.luo@amlogic.com> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
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@@ -487,7 +487,7 @@ static struct clk_mux tl1_dsu_fixed_source_sel0 = {
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.ops = &clk_mux_ops,
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.parent_names = dsu_fixed_source_sel_parent_names,
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.num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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},
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};
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@@ -972,10 +972,6 @@ static int tl1_dsu_sel0_clk_notifier_cb(struct notifier_block *nb,
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switch (event) {
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case PRE_RATE_CHANGE:
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/* switch to tl1_dsu_fixed_sel1, set it to 1G (default 24M) */
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ret = clk_set_rate(tl1_dsu_fixed_sel1.hw.clk, 1000000000);
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if (ret < 0)
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return ret;
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parent_clk = tl1_dsu_fixed_sel1.hw.clk;
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break;
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case POST_RATE_CHANGE:
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@@ -1095,6 +1091,13 @@ static void __init tl1_clkc_init(struct device_node *np)
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parent_hw = clk_hw_get_parent(&tl1_cpu_clk.mux.hw);
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parent_clk = parent_hw->clk;
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ret = clk_notifier_register(parent_clk, &tl1_cpu_clk.clk_nb);
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/* set tl1_dsu_fixed_sel1 to 1G (default 24M) */
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ret = clk_set_rate(tl1_dsu_fixed_sel1.hw.clk, 1000000000);
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if (ret < 0) {
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pr_err("set tl1_dsu_fixed_sel1 to 1G failed\n");
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return;
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}
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/*
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* when change tl1_dsu_fixed_sel0, switch to
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* tl1_dsu_fixed_sel1 to avoid crash
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