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tvafe: add 0x87, 0x11b support in pq trust list [1/1]

Browse Source 
PD#SWPL-13775

Problem:
pq need update 0x87, 0x11b reg

Solution:
1.add 0x87, 0x11b support in pq trust list
2.update 0x87,0xfa,0x12e reg init setting for tl1
3.add dump regs for debug

Verify:
x301

Change-Id: I532d164f0fb7b01e817d19ece1498b970d40193e
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-09-04 14:50:58 +08:00
committed by Tao Zeng
parent 722f778afc
commit b2ac7eef33
5 changed files with 53 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/amlogic/media/vin/tvin/tvafe/tvafe_cvd.c
View File

@@ -147,6 +147,9 @@ static int ignore_443_358;
module_param(ignore_443_358, int, 0644);
MODULE_PARM_DESC(ignore_443_358, "ignore_443_358\n");
unsigned int cvd_reg87_pal;
static unsigned int acd_vde_config = 0x00170107;
static unsigned int acd_h_config = 0x8e035e;
module_param(acd_h_config, uint, 0664);
MODULE_PARM_DESC(acd_h_config, "acd_h_config");
@@ -512,6 +515,9 @@ static void tvafe_cvd2_write_mode_reg(struct tvafe_cvd2_s *cvd2,
}
}
cvd_reg87_pal = R_APB_REG(CVD2_REG_87);
acd_vde_config = R_APB_REG(ACD_REG_2E);
/* enable CVD2 */
W_APB_BIT(CVD2_RESET_REGISTER, 0, SOFT_RST_BIT, SOFT_RST_WID);
}
@@ -1994,8 +2000,7 @@ void tvafe_cvd2_set_default_de(struct tvafe_cvd2_s *cvd2)
return;
}
/*write default de to register*/
W_APB_REG(ACD_REG_2E, (rf_acd_table[cvd2->config_fmt-
TVIN_SIG_FMT_CVBS_NTSC_M][0x2e]));
W_APB_REG(ACD_REG_2E, acd_vde_config);
if (tvafe_dbg_print & TVAFE_DBG_SMR)
tvafe_pr_info("%s set default de %s.\n",
__func__, tvin_sig_fmt_str(cvd2->config_fmt));
@@ -2027,7 +2032,7 @@ static void tvafe_cvd2_reinit(struct tvafe_cvd2_s *cvd2)
#endif
/*pali to nosignal,restore default vstart-end after auto de*/
if (cvd2->config_fmt == TVIN_SIG_FMT_CVBS_PAL_I) {
W_APB_REG(ACD_REG_2E, 0x170137);
W_APB_REG(ACD_REG_2E, acd_vde_config);
if (tvafe_dbg_print & TVAFE_DBG_SMR)
pr_info("[tvafe..] %s: reset auto de.\n", __func__);
}
@@ -2380,8 +2385,8 @@ inline void tvafe_cvd2_adj_hs(struct tvafe_cvd2_s *cvd2,
W_APB_REG(CVD2_YC_SEPARATION_CONTROL, 0x12);
if (R_APB_REG(CVD2_H_LOOP_MAXSTATE) != 0xd)
W_APB_REG(CVD2_H_LOOP_MAXSTATE, 0xd);
if (R_APB_REG(CVD2_REG_87) != 0x0)
W_APB_REG(CVD2_REG_87, 0x0);
if (R_APB_REG(CVD2_REG_87) != cvd_reg87_pal)
W_APB_REG(CVD2_REG_87, cvd_reg87_pal);
W_APB_REG(ACD_REG_2D, acd_h_back);
W_APB_BIT(CVD2_ACTIVE_VIDEO_HSTART, cvd_2e,
HACTIVE_START_BIT, HACTIVE_START_WID);
@@ -2406,8 +2411,8 @@ inline void tvafe_cvd2_adj_hs(struct tvafe_cvd2_s *cvd2,
W_APB_REG(CVD2_YC_SEPARATION_CONTROL, 0x12);
if (R_APB_REG(CVD2_H_LOOP_MAXSTATE) != 0xd)
W_APB_REG(CVD2_H_LOOP_MAXSTATE, 0xd);
if (R_APB_REG(CVD2_REG_87) != 0x0)
W_APB_REG(CVD2_REG_87, 0x0);
if (R_APB_REG(CVD2_REG_87) != cvd_reg87_pal)
W_APB_REG(CVD2_REG_87, cvd_reg87_pal);
W_APB_REG(ACD_REG_2D, acd_h_back);
W_APB_BIT(CVD2_ACTIVE_VIDEO_HSTART, cvd_2e,

25
drivers/amlogic/media/vin/tvin/tvafe/tvafe_debug.c
View File

@@ -712,29 +712,22 @@ static ssize_t tvafereg_store(struct device *dev,
}
break;
case 'D':
/* if (argn < 3) {*/
/* tvafe_pr_err("syntax error.\n");*/
/* } else{*/
tvafe_pr_info("dump TOP reg----\n");
for (addr = TOP_BASE_ADD;
addr <= (TOP_BASE_ADD+0xb2); addr++)
tvafe_pr_info("[0x%x]APB[0x%04x]=0x%08x\n",
(0XC8842000+(addr<<2)), addr,
R_APB_REG(addr<<2));
addr <= (TOP_BASE_ADD + 0xb2); addr++)
tvafe_pr_info("APB[0x%04x]=0x%08x\n",
addr, R_APB_REG(addr << 2));
tvafe_pr_info("dump ACD reg----\n");
for (addr = ACD_BASE_ADD;
addr <= (ACD_BASE_ADD+0xA4); addr++)
tvafe_pr_info("[0x%x]APB[0x%04x]=0x%08x\n",
(0XC8842000+(addr<<2)), addr,
R_APB_REG(addr<<2));
addr <= (ACD_BASE_ADD + 0xa5); addr++)
tvafe_pr_info("APB[0x%04x]=0x%08x\n",
addr, R_APB_REG(addr << 2));
tvafe_pr_info("dump CVD2 reg----\n");
for (addr = CVD_BASE_ADD;
addr <= (CVD_BASE_ADD+0xf9); addr++)
tvafe_pr_info("[0x%x]APB[0x%04x]=0x%08x\n",
(0XC8842000+(addr<<2)), addr,
R_APB_REG(addr<<2));
addr <= (CVD_BASE_ADD + 0xfe); addr++)
tvafe_pr_info("APB[0x%04x]=0x%08x\n",
addr, R_APB_REG(addr << 2));
tvafe_pr_info("dump reg done----\n");
/* } */
break;
default:
tvafe_pr_err("not support.\n");

7
drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c
View File

@@ -243,11 +243,12 @@ static const unsigned int tvafe_pq_reg_trust_table[][2] = {
{CVD2_LUMA_BRIGHTNESS_ADJUSTMENT, 0xff}, /* 0x09 */
{CVD2_CHROMA_SATURATION_ADJUSTMENT, 0xff}, /* 0x0a */
{CVD2_CHROMA_HUE_PHASE_ADJUSTMENT, 0xff}, /* 0x0b */
{CVD2_REG_87, 0xc0}, /* 0x87 */
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0xff}, /* 0xb5 */
{CVD2_CHROMA_BW_MOTION, 0xff}, /* 0xe8 */
{CVD2_REG_FA, 0xa0}, /* 0xfa */
{CVD2_REG_FA, 0x80}, /* 0xfa */
{ACD_REG_1B, 0xffffffff},
{ACD_REG_1B, 0x0f000000},
{ACD_REG_25, 0xffffffff},
{ACD_REG_53, 0xffffffff},
{ACD_REG_54, 0xffffffff},
@@ -311,6 +312,8 @@ static void tvafe_pq_apb_reg_trust_write(unsigned int addr,
__func__, addr, addr,
(val & mask), (val & mask),
val, val, mask, mask);
cvd_reg87_pal = R_APB_REG(CVD2_REG_87);
}
/*

1
drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.h
View File

@@ -204,6 +204,7 @@ extern int tvafe_cpu_type(void);
extern void tvafe_clk_gate_ctrl(int status);
extern struct mutex pll_mutex;
extern unsigned int cvd_reg87_pal;
#endif /* _TVAFE_GENERAL_H */

28
drivers/amlogic/media/vin/tvin/tvafe/tvafe_pq_table.c
View File

@@ -337,8 +337,8 @@ static struct tvafe_reg_table_s cvbs_ntscm_table_tl1[] = {
{CVD2_3DCOMB_FILTER, 0x0f, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
/* fix Purple and green junctions is wider */
{CVD2_REG_FA, 0x00, 0x80},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -347,6 +347,8 @@ static struct tvafe_reg_table_s cvbs_ntscm_table_tl1[] = {
static struct tvafe_reg_table_s cvbs_ntsc443_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -357,6 +359,8 @@ static struct tvafe_reg_table_s cvbs_pali_table_tl1[] = {
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
/*chroma state adjust dynamicly*/
{CVD2_CHROMA_LOOPFILTER_STATE, 0x0a, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
{ACD_REG_89, 0x80010004, 0xffffffff},
{ACD_REG_8A, 0x100004, 0xffffffff},
{ACD_REG_8C, 0x38000, 0xffffffff},
@@ -370,6 +374,8 @@ static struct tvafe_reg_table_s cvbs_palm_table_tl1[] = {
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*for moonoscope pattern color flash*/
{ACD_REG_22, 0x2020000, 0xffffffff},
{CVD2_NOISE_THRESHOLD, 0xff, 0xff},
@@ -382,6 +388,8 @@ static struct tvafe_reg_table_s cvbs_palm_table_tl1[] = {
static struct tvafe_reg_table_s cvbs_pal60_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -390,6 +398,8 @@ static struct tvafe_reg_table_s cvbs_pal60_table_tl1[] = {
static struct tvafe_reg_table_s cvbs_palcn_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -400,6 +410,8 @@ static struct tvafe_reg_table_s cvbs_secam_table_tl1[] = {
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_B2, 0x08, 0x18},
{CVD2_CHROMA_EDGE_ENHANCEMENT, 0x22, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -408,6 +420,8 @@ static struct tvafe_reg_table_s cvbs_secam_table_tl1[] = {
static struct tvafe_reg_table_s cvbs_ntsc50_table_tl1[] = {
/* reg, val, mask */
{CVD2_VSYNC_NO_SIGNAL_THRESHOLD, 0xf0, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
/*set for wipe off vertical stripes*/
{ACD_REG_25, 0xeafb4e8e, 0xffffffff},
{0xffffffff, 0, 0},
@@ -419,6 +433,7 @@ static struct tvafe_reg_table_s rf_ntscm_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
@@ -427,6 +442,7 @@ static struct tvafe_reg_table_s rf_ntsc443_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
@@ -435,6 +451,8 @@ static struct tvafe_reg_table_s rf_pali_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
{0xffffffff, 0, 0},
};
@@ -447,6 +465,8 @@ static struct tvafe_reg_table_s rf_palm_table_tl1[] = {
{ACD_REG_22, 0x2020000, 0xffffffff},
{CVD2_NOISE_THRESHOLD, 0xff, 0xff},
{CVD2_NON_STANDARD_SIGNAL_THRESHOLD, 0x20, 0xff},
{CVD2_REG_87, 0xc0, 0xc0},
{CVD2_REG_FA, 0x00, 0xa0},
{0xffffffff, 0, 0},
};
@@ -455,6 +475,7 @@ static struct tvafe_reg_table_s rf_pal60_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
@@ -463,6 +484,7 @@ static struct tvafe_reg_table_s rf_palcn_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
@@ -471,6 +493,7 @@ static struct tvafe_reg_table_s rf_secam_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};
@@ -479,6 +502,7 @@ static struct tvafe_reg_table_s rf_ntsc50_table_tl1[] = {
{CVD2_REG_B0, 0xf0, 0xff},
{CVD2_REG_B2, 0x00, 0x18},
{CVD2_CONTROL1, 0x00, 0x0c},
{CVD2_REG_87, 0xc0, 0xc0},
{0xffffffff, 0, 0},
};