shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-04-02 03:03:00 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop: split dclk_pol from pin_pol

Browse Source 
Some vop have a difference pin_pol layout

Change-Id: I96c4dc9fbc00470828748a926d6248c5a5772c82
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This commit is contained in:
Mark Yao
2017-07-24 15:43:40 +08:00
committed by Huang, Tao
parent b5e982a2e6
commit b2d8717bea
3 changed files with 35 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -1681,8 +1681,8 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
mutex_lock(&vop->vop_lock);
vop_initial(crtc);
val = BIT(DCLK_INVERT);
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
VOP_CTRL_SET(vop, dclk_pol, 1);
val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
0 : BIT(HSYNC_POSITIVE);
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
0 : BIT(VSYNC_POSITIVE);
@@ -1698,21 +1698,25 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
case DRM_MODE_CONNECTOR_LVDS:
VOP_CTRL_SET(vop, rgb_en, 1);
VOP_CTRL_SET(vop, rgb_pin_pol, val);
VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
break;
case DRM_MODE_CONNECTOR_eDP:
VOP_CTRL_SET(vop, edp_en, 1);
VOP_CTRL_SET(vop, edp_pin_pol, val);
VOP_CTRL_SET(vop, edp_dclk_pol, 1);
break;
case DRM_MODE_CONNECTOR_HDMIA:
VOP_CTRL_SET(vop, hdmi_en, 1);
VOP_CTRL_SET(vop, hdmi_pin_pol, val);
VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
break;
case DRM_MODE_CONNECTOR_DSI:
VOP_CTRL_SET(vop, mipi_en, 1);
VOP_CTRL_SET(vop, mipi_pin_pol, val);
VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
break;
case DRM_MODE_CONNECTOR_DisplayPort:
val &= ~BIT(DCLK_INVERT);
VOP_CTRL_SET(vop, dp_dclk_pol, 0);
VOP_CTRL_SET(vop, dp_pin_pol, val);
VOP_CTRL_SET(vop, dp_en, 1);
break;

7
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -110,11 +110,17 @@ struct vop_ctrl {
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg dp_en;
struct vop_reg dclk_pol;
struct vop_reg pin_pol;
struct vop_reg rgb_dclk_pol;
struct vop_reg rgb_pin_pol;
struct vop_reg hdmi_dclk_pol;
struct vop_reg hdmi_pin_pol;
struct vop_reg edp_dclk_pol;
struct vop_reg edp_pin_pol;
struct vop_reg mipi_dclk_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg dp_dclk_pol;
struct vop_reg dp_pin_pol;
struct vop_reg dither_up;
struct vop_reg dither_down;
@@ -452,7 +458,6 @@ enum vop_pol {
HSYNC_POSITIVE = 0,
VSYNC_POSITIVE = 1,
DEN_NEGATIVE = 2,
DCLK_INVERT = 3
};
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))

33
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -196,12 +196,18 @@ static const struct vop_ctrl rk3288_ctrl_data = {
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
.pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
.dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
.rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
.hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
.edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
.dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
.pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
.dp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 19, 3, 0, 1),
.dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
.rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 19, 3, 0, 1),
.rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
.hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 23, 3, 0, 1),
.hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
.edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 0, 1),
.edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
.mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 0, 1),
.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
@@ -605,10 +611,14 @@ static const struct vop_ctrl rk3328_ctrl_data = {
.sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
.sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
.sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),
.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28),
.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
.rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
.hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
.dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
@@ -724,7 +734,8 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),