From b3912fea8ae97594c8844c1079f2ea36d44972a7 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 25 Sep 2020 10:53:44 +0800 Subject: [PATCH] clk: rockchip: rk3568: export PCLK_CORE_PVTM clock id mark pclk_core_pre as critical. Signed-off-by: Elaine Zhang Change-Id: I7da6a93dc1352acb2b336006bd1e30c49b8d6074 --- drivers/clk/rockchip/clk-rk3568.c | 3 +++ include/dt-bindings/clock/rk3568-cru.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index c68caaa3e742..711a4cc33d00 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -531,6 +531,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(1), 11, GFLAGS), GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 0, RK3568_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, + RK3568_CLKGATE_CON(1), 9, GFLAGS), /* PD_GPU */ COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, @@ -1584,6 +1586,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { static const char *const rk3568_cru_critical_clocks[] __initconst = { "armclk", + "pclk_core_pre", "aclk_bus", "pclk_bus", "aclk_top_high", diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index d7d2be75edbf..8066b7a6c8c3 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -461,8 +461,9 @@ #define SCLK_EMMC_DRV 400 #define SCLK_EMMC_SAMPLE 401 #define PCLK_EDPPHY_GRF 402 +#define PCLK_CORE_PVTM 403 -#define CLK_NR_CLKS (PCLK_EDPPHY_GRF + 1) +#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) /* pmu soft-reset indices */ /* pmucru_softrst_con0 */