From b3a247a0ba1202e8932eebbe8efe1c2b982cf065 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 6 Jul 2023 09:36:17 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie Fixes: 13639746faf3 ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562") Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78 Signed-off-by: Jon Lin Signed-off-by: Tao Huang --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index fdf81f534870..730dcb706bd8 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -628,7 +628,7 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) writel(0xf0, priv->mmio + (0xa << 2)); /* CKDRV output swing adjust to 650mv */ - rockchip_combphy_updatel(priv, GENMASK(4, 1), 0xb, 0xd << 2); + rockchip_combphy_updatel(priv, GENMASK(4, 1), 0xb << 1, 0xd << 2); } break; default: