From b4fa954b4ccff0c4ae879e9e665a676d626d3c5a Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Wed, 1 Jun 2022 10:28:10 +0000 Subject: [PATCH] clk: rockchip: rk3588: fix 32-bit compile warning "warn: should 'fout_hz << s' be a 64 bit type?" Signed-off-by: Joseph Chen Change-Id: I3b842974c2c1709878702c35963df74acd7f4d2f --- drivers/clk/rockchip/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index a785decbaaa8..692334c58928 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -351,7 +351,7 @@ rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) { for (s = 0; s <= 6; s++) { - fvco = fout_hz << s; + fvco = (u64)fout_hz << s; if (fvco < fvco_min || fvco > fvco_max) continue; for (p = 2; p <= 4; p++) { @@ -369,7 +369,7 @@ rockchip_rk3588_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); } else { for (s = 0; s <= 6; s++) { - fvco = fout_hz << s; + fvco = (u64)fout_hz << s; if (fvco < fvco_min || fvco > fvco_max) continue; for (p = 1; p <= 4; p++) {