mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-09 12:17:12 +09:00
modify for rga.h independ
This commit is contained in:
@@ -83,10 +83,10 @@ matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
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u32
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RGA_dst_act_addr_temp(const struct rga_req *msg)
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{
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u32 pw;
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u32 x_off, y_off;
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u32 stride;
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u32 p;
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uint32_t pw;
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uint32_t x_off, y_off;
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uint32_t stride;
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uint32_t p;
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pw = RGA_pixel_width_init(msg->dst.format);
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stride = (msg->dst.vir_w * pw + 3) & (~3);
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@@ -100,11 +100,10 @@ RGA_dst_act_addr_temp(const struct rga_req *msg)
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}
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void
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RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)
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RGA_set_cmd_info(uint8_t cmd_mode, uint32_t cmd_addr)
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{
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u32 reg = 0;
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uint32_t reg = 0;
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//reg = rRGA_SYS_CTRL;
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reg |= ((cmd_mode & 1) << 1);
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rRGA_SYS_CTRL = reg;
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rRGA_CMD_ADDR = cmd_addr;
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@@ -113,8 +112,8 @@ RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)
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void
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RGA_start(void)
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{
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u32 reg = 0;
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u8 cmd_mode;
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uint32_t reg = 0;
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uint8_t cmd_mode;
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reg = rRGA_SYS_CTRL;
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cmd_mode = (reg >> 2) & 1;
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@@ -138,7 +137,7 @@ RGA_start(void)
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void
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RGA_soft_reset(void)
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{
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u32 reg = 0;
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uint32_t reg = 0;
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reg = rRGA_SYS_CTRL;
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reg |= 1;
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@@ -185,7 +184,7 @@ void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info)
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}
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#endif
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void rga_start_cmd_AXI(u8 *base, u32 num)
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void rga_start_cmd_AXI(uint8_t *base, uint32_t num)
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{
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rRGA_SYS_CTRL = 0x4;
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rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE);
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@@ -196,8 +195,8 @@ void rga_start_cmd_AXI(u8 *base, u32 num)
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void rga_check_cmd_finish(void)
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{
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u8 int_flag;
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u8 error_flag;
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uint8_t int_flag;
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uint8_t error_flag;
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int_flag = 0;
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error_flag = 0;
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@@ -222,9 +221,9 @@ void rga_check_cmd_finish(void)
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void rga_start_cmd_AHB(u8 *base)
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void rga_start_cmd_AHB(uint8_t *base)
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{
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u32 *base_p32;
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uint32_t *base_p32;
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base_p32 = (u32 *)base;
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*base_p32 = (*base_p32 | (1<<29));
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@@ -237,7 +236,7 @@ void rga_start_cmd_AHB(u8 *base)
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void rga_check_cmd_AHB_finish(void)
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{
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u8 int_flag;
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uint8_t int_flag;
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int_flag = 0;
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while(!int_flag)
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@@ -253,11 +252,11 @@ uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
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{
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struct rga_req *mp;
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u32 w_ratio, h_ratio;
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u32 stride;
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uint32_t w_ratio, h_ratio;
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uint32_t stride;
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u32 daw, dah;
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u32 pl;
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uint32_t daw, dah;
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uint32_t pl;
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daw = dah = 0;
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@@ -1,11 +1,6 @@
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#ifndef _RGA_DRIVER_H_
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#define _RGA_DRIVER_H_
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#include "rga_type.h"
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#include <linux/types.h>
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#include <linux/miscdevice.h>
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#include <linux/platform_device.h>
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#define RGA_BLIT_SYNC 0x5017
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#define RGA_BLIT_ASYNC 0x5018
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@@ -118,31 +113,31 @@ enum
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typedef struct rga_img_info_t
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{
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uint32 yrgb_addr; /* yrgb mem addr */
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uint32 uv_addr; /* cb/cr mem addr */
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uint32 v_addr; /* cr mem addr */
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uint32 format; //definition by RK_FORMAT
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unsigned int yrgb_addr; /* yrgb mem addr */
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unsigned int uv_addr; /* cb/cr mem addr */
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unsigned int v_addr; /* cr mem addr */
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unsigned int format; //definition by RK_FORMAT
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UWORD16 act_w;
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UWORD16 act_h;
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UWORD16 x_offset;
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UWORD16 y_offset;
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unsigned short act_w;
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unsigned short act_h;
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unsigned short x_offset;
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unsigned short y_offset;
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UWORD16 vir_w;
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UWORD16 vir_h;
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unsigned short vir_w;
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unsigned short vir_h;
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UWORD16 endian_mode; //for BPP
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UWORD16 alpha_swap;
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unsigned short endian_mode; //for BPP
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unsigned short alpha_swap;
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}
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rga_img_info_t;
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typedef struct mdp_img_act
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{
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UWORD16 w; // width
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UWORD16 h; // height
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WORD16 x_off; // x offset for the vir
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WORD16 y_off; // y offset for the vir
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unsigned short w; // width
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unsigned short h; // height
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short x_off; // x offset for the vir
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short y_off; // y offset for the vir
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}
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mdp_img_act;
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@@ -150,24 +145,24 @@ mdp_img_act;
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typedef struct RANGE
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{
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UWORD16 min;
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UWORD16 max;
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unsigned short min;
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unsigned short max;
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}
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RANGE;
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typedef struct POINT
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{
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UWORD16 x;
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UWORD16 y;
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unsigned short x;
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unsigned short y;
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}
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POINT;
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typedef struct RECT
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{
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WORD16 xmin;
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WORD16 xmax; // width - 1
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WORD16 ymin;
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WORD16 ymax; // height - 1
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unsigned short xmin;
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unsigned short xmax; // width - 1
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unsigned short ymin;
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unsigned short ymax; // height - 1
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} RECT;
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typedef struct RGB
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@@ -182,8 +177,8 @@ typedef struct RGB
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typedef struct MMU
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{
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unsigned char mmu_en;
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uint32 base_addr;
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uint32 mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
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uint32_t base_addr;
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uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
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} MMU;
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@@ -206,94 +201,94 @@ COLOR_FILL;
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typedef struct FADING
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{
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UBYTE b;
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UBYTE g;
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UBYTE r;
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UBYTE res;
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uint8_t b;
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uint8_t g;
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uint8_t r;
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uint8_t res;
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}
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FADING;
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typedef struct line_draw_t
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{
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POINT start_point; /* LineDraw_start_point */
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POINT end_point; /* LineDraw_end_point */
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uint32 color; /* LineDraw_color */
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uint32 flag; /* (enum) LineDrawing mode sel */
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uint32 line_width; /* range 1~16 */
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POINT start_point; /* LineDraw_start_point */
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POINT end_point; /* LineDraw_end_point */
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uint32_t color; /* LineDraw_color */
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uint32_t flag; /* (enum) LineDrawing mode sel */
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uint32_t line_width; /* range 1~16 */
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}
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line_draw_t;
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struct rga_req {
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UBYTE render_mode; /* (enum) process mode sel */
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uint8_t render_mode; /* (enum) process mode sel */
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rga_img_info_t src; /* src image info */
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rga_img_info_t dst; /* dst image info */
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rga_img_info_t pat; /* patten image info */
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rga_img_info_t src; /* src image info */
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rga_img_info_t dst; /* dst image info */
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rga_img_info_t pat; /* patten image info */
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uint32 rop_mask_addr; /* rop4 mask addr */
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uint32 LUT_addr; /* LUT addr */
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uint32_t rop_mask_addr; /* rop4 mask addr */
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uint32_t LUT_addr; /* LUT addr */
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RECT clip; /* dst clip window default value is dst_vir */
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/* value from [0, w-1] / [0, h-1]*/
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RECT clip; /* dst clip window default value is dst_vir */
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/* value from [0, w-1] / [0, h-1]*/
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int32_t sina; /* dst angle default value 0 16.16 scan from table */
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int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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int32_t sina; /* dst angle default value 0 16.16 scan from table */
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int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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uint16_t alpha_rop_flag; /* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 PD_enable) */
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/* ([4] = 1 alpha cal_mode_sel) */
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/* ([5] = 1 dither_enable) */
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/* ([6] = 1 gradient fill mode sel) */
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/* ([7] = 1 AA_enable) */
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uint16_t alpha_rop_flag; /* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 PD_enable) */
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/* ([4] = 1 alpha cal_mode_sel) */
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/* ([5] = 1 dither_enable) */
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/* ([6] = 1 gradient fill mode sel) */
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/* ([7] = 1 AA_enable) */
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uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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uint32 color_key_max; /* color key max */
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uint32 color_key_min; /* color key min */
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uint32_t color_key_max; /* color key max */
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uint32_t color_key_min; /* color key min */
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uint32 fg_color; /* foreground color */
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uint32 bg_color; /* background color */
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uint32_t fg_color; /* foreground color */
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uint32_t bg_color; /* background color */
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COLOR_FILL gr_color; /* color fill use gradient */
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COLOR_FILL gr_color; /* color fill use gradient */
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line_draw_t line_draw_info;
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FADING fading;
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uint8_t PD_mode; /* porter duff alpha mode sel */
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uint8_t PD_mode; /* porter duff alpha mode sel */
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uint8_t alpha_global_value; /* global alpha value */
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uint8_t alpha_global_value; /* global alpha value */
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uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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uint8_t endian_mode; /* 0/big endian 1/little endian*/
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uint8_t endian_mode; /* 0/big endian 1/little endian*/
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uint8_t rotate_mode; /* (enum) rotate mode */
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/* 0x0, no rotate */
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/* 0x1, rotate */
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/* 0x2, x_mirror */
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/* 0x3, y_mirror */
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uint8_t rotate_mode; /* (enum) rotate mode */
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/* 0x0, no rotate */
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/* 0x1, rotate */
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/* 0x2, x_mirror */
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/* 0x3, y_mirror */
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uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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MMU mmu_info; /* mmu information */
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MMU mmu_info; /* mmu information */
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uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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/* ([2~3] rop mode) */
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/* ([4] zero mode en) */
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/* ([5] dst alpha mode) */
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uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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/* ([2~3] rop mode) */
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/* ([4] zero mode en) */
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/* ([5] dst alpha mode) */
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uint8_t src_trans_mode;
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@@ -388,33 +383,6 @@ typedef struct rga_service_info {
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struct rga_drvdata {
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struct miscdevice miscdev;
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struct device dev;
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void *rga_base;
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int irq0;
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struct clk *pd_display;
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struct clk *aclk_lcdc;
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struct clk *hclk_lcdc;
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struct clk *aclk_ddr_lcdc;
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struct clk *hclk_cpu_display;
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struct clk *aclk_disp_matrix;
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struct clk *hclk_disp_matrix;
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struct clk *axi_clk;
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struct clk *ahb_clk;
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struct mutex mutex; // mutex
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struct delayed_work power_off_work;
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bool enable; //clk enable or disable
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void (*rga_irq_callback)(int rga_retval); //callback function used by aync call
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};
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#define RGA_BASE 0x10114000
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//General Registers
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@@ -58,13 +58,33 @@
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#define RGA_POWER_OFF_DELAY 4*HZ /* 4s */
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#define RGA_TIMEOUT_DELAY 2*HZ /* 2s */
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struct rga_drvdata {
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struct miscdevice miscdev;
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struct device dev;
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void *rga_base;
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int irq0;
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struct clk *pd_display;
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struct clk *aclk_lcdc;
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struct clk *hclk_lcdc;
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struct clk *aclk_ddr_lcdc;
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struct clk *hclk_cpu_display;
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struct clk *aclk_disp_matrix;
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struct clk *hclk_disp_matrix;
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struct clk *axi_clk;
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struct clk *ahb_clk;
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struct mutex mutex; // mutex
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struct delayed_work power_off_work;
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bool enable; //clk enable or disable
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void (*rga_irq_callback)(int rga_retval); //callback function used by aync call
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};
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static struct rga_drvdata *drvdata = NULL;
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rga_service_info rga_service;
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#if 1//def RGA_TEST
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//uint32_t dst_buf[800*480*4];
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#endif
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static int rga_blit_async(rga_session *session, struct rga_req *req);
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