From b651d43f2a243d09c57856a323abf37bb0fd7f4d Mon Sep 17 00:00:00 2001 From: Quentin Perret Date: Tue, 30 Nov 2021 13:47:02 +0000 Subject: [PATCH] ANDROID: arm64: Annotate icache_inval_pou as position-independent In preparation for re-using icache_inval_pou from the EL2 nVHE hypervisor, annotate it as position-independent. Signed-off-by: Quentin Perret Bug: 209580772 Change-Id: I66fbf42239a891bfd149c79bf77379fea124793e Signed-off-by: Will Deacon --- arch/arm64/mm/cache.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 5051b3c1a4f1..7835c22db175 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -88,7 +88,7 @@ SYM_FUNC_END(caches_clean_inval_user_pou) * - start - virtual start address of region * - end - virtual end address of region */ -SYM_FUNC_START(icache_inval_pou) +SYM_FUNC_START_PI(icache_inval_pou) alternative_if ARM64_HAS_CACHE_DIC isb ret @@ -96,7 +96,7 @@ alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3 ret -SYM_FUNC_END(icache_inval_pou) +SYM_FUNC_END_PI(icache_inval_pou) /* * dcache_clean_inval_poc(start, end)