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MALI: rockchip: upgrade bifrost DDK to g21p0-01eac0, from g18p0-01eac0

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"/sys/kernel/tracing/events/power/gpu_work_period/*" required by Android 14.0 is implemented.

NOTE:
For RK3588, the mali_csffw.bin used with this driver MUST be from DDK g21p0-01eac0 correspondingly.

Change-Id: Ifab61806a6a350ba53c5dc0296d20628c28d633a
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
This commit is contained in:
Zhen Chen
2023-06-05 10:40:56 +08:00
committed by Tao Huang
parent 6a55166690
commit b72fff5ed8
384 changed files with 36480 additions and 28455 deletions
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41
include/uapi/gpu/arm/bifrost/backend/gpu/mali_kbase_model_dummy.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2021-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2021-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -30,34 +30,31 @@
#define KBASE_DUMMY_MODEL_COUNTER_HEADER_DWORDS (4)
#if MALI_USE_CSF
#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE (65)
#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE (65)
#else /* MALI_USE_CSF */
#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE (60)
#endif /* !MALI_USE_CSF */
#define KBASE_DUMMY_MODEL_COUNTERS_PER_BIT (4)
#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE (60)
#endif /* MALI_USE_CSF */
#define KBASE_DUMMY_MODEL_COUNTERS_PER_BIT (4)
#define KBASE_DUMMY_MODEL_COUNTER_ENABLED(enable_mask, ctr_idx) \
(enable_mask & (1 << (ctr_idx / KBASE_DUMMY_MODEL_COUNTERS_PER_BIT)))
#define KBASE_DUMMY_MODEL_HEADERS_PER_BLOCK 4
#define KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK 60
#define KBASE_DUMMY_MODEL_VALUES_PER_BLOCK \
(KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK + \
KBASE_DUMMY_MODEL_HEADERS_PER_BLOCK)
#define KBASE_DUMMY_MODEL_BLOCK_SIZE \
(KBASE_DUMMY_MODEL_VALUES_PER_BLOCK * sizeof(__u32))
#define KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS 8
#define KBASE_DUMMY_MODEL_MAX_SHADER_CORES 32
#define KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK KBASE_DUMMY_MODEL_COUNTER_PER_CORE
#define KBASE_DUMMY_MODEL_VALUES_PER_BLOCK \
(KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK + KBASE_DUMMY_MODEL_HEADERS_PER_BLOCK)
#define KBASE_DUMMY_MODEL_BLOCK_SIZE (KBASE_DUMMY_MODEL_VALUES_PER_BLOCK * sizeof(__u32))
#define KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS 8
#define KBASE_DUMMY_MODEL_MAX_SHADER_CORES 32
#define KBASE_DUMMY_MODEL_MAX_FIRMWARE_BLOCKS 0
#define KBASE_DUMMY_MODEL_MAX_NUM_HARDWARE_BLOCKS \
#define KBASE_DUMMY_MODEL_MAX_NUM_HARDWARE_BLOCKS \
(1 + 1 + KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS + KBASE_DUMMY_MODEL_MAX_SHADER_CORES)
#define KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS \
#define KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS \
(KBASE_DUMMY_MODEL_MAX_NUM_HARDWARE_BLOCKS + KBASE_DUMMY_MODEL_MAX_FIRMWARE_BLOCKS)
#define KBASE_DUMMY_MODEL_COUNTER_TOTAL \
(KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS * \
KBASE_DUMMY_MODEL_COUNTER_PER_CORE)
#define KBASE_DUMMY_MODEL_MAX_VALUES_PER_SAMPLE \
#define KBASE_DUMMY_MODEL_COUNTER_TOTAL \
(KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS * KBASE_DUMMY_MODEL_COUNTER_PER_CORE)
#define KBASE_DUMMY_MODEL_MAX_VALUES_PER_SAMPLE \
(KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS * KBASE_DUMMY_MODEL_VALUES_PER_BLOCK)
#define KBASE_DUMMY_MODEL_MAX_SAMPLE_SIZE \
#define KBASE_DUMMY_MODEL_MAX_SAMPLE_SIZE \
(KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS * KBASE_DUMMY_MODEL_BLOCK_SIZE)
/*
@@ -70,8 +67,10 @@
#define DUMMY_IMPLEMENTATION_SHADER_PRESENT_TODX (0x3FFull)
#define DUMMY_IMPLEMENTATION_SHADER_PRESENT_TTUX (0x7FFull)
#define DUMMY_IMPLEMENTATION_SHADER_PRESENT_TTIX (0xFFFull)
#define DUMMY_IMPLEMENTATION_TILER_PRESENT (0x1ull)
#define DUMMY_IMPLEMENTATION_SHADER_PRESENT_TKRX (0x1FFFull)
#define DUMMY_IMPLEMENTATION_L2_PRESENT (0x1ull)
#define DUMMY_IMPLEMENTATION_TILER_PRESENT (0x1ull)
#define DUMMY_IMPLEMENTATION_STACK_PRESENT (0xFull)
#endif /* _UAPI_KBASE_MODEL_DUMMY_H_ */

23
include/uapi/gpu/arm/bifrost/csf/mali_base_csf_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -48,7 +48,6 @@
#define BASE_MEM_RESERVED_BIT_20 ((base_mem_alloc_flags)1 << 20)
/* Must be FIXABLE memory: its GPU VA will be determined at a later point,
* at which time it will be at a fixed GPU VA.
*/
@@ -61,8 +60,7 @@
/* A mask of all the flags which are only valid for allocations within kbase,
* and may not be passed from user space.
*/
#define BASEP_MEM_FLAGS_KERNEL_ONLY \
(BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE)
#define BASEP_MEM_FLAGS_KERNEL_ONLY (BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE)
/* A mask of all currently reserved flags
*/
@@ -74,8 +72,7 @@
#define BASEP_MEM_CSF_USER_IO_PAGES_HANDLE (48ul << LOCAL_PAGE_SHIFT)
#define KBASE_CSF_NUM_USER_IO_PAGES_HANDLE \
((BASE_MEM_COOKIE_BASE - BASEP_MEM_CSF_USER_IO_PAGES_HANDLE) >> \
LOCAL_PAGE_SHIFT)
((BASE_MEM_COOKIE_BASE - BASEP_MEM_CSF_USER_IO_PAGES_HANDLE) >> LOCAL_PAGE_SHIFT)
/* Valid set of just-in-time memory allocation flags */
#define BASE_JIT_ALLOC_VALID_FLAGS ((__u8)0)
@@ -92,9 +89,8 @@
/* Bitpattern describing the ::base_context_create_flags that can be
* passed to base_context_init()
*/
#define BASEP_CONTEXT_CREATE_ALLOWED_FLAGS \
(BASE_CONTEXT_CCTX_EMBEDDED | \
BASE_CONTEXT_CSF_EVENT_THREAD | \
#define BASEP_CONTEXT_CREATE_ALLOWED_FLAGS \
(BASE_CONTEXT_CCTX_EMBEDDED | BASE_CONTEXT_CSF_EVENT_THREAD | \
BASEP_CONTEXT_CREATE_KERNEL_FLAGS)
/* Flags for base tracepoint specific to CSF */
@@ -105,10 +101,9 @@
/* Enable additional CSF Firmware side tracepoints */
#define BASE_TLSTREAM_ENABLE_CSFFW_TRACEPOINTS (1 << 3)
#define BASE_TLSTREAM_FLAGS_MASK (BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | \
BASE_TLSTREAM_JOB_DUMPING_ENABLED | \
BASE_TLSTREAM_ENABLE_CSF_TRACEPOINTS | \
BASE_TLSTREAM_ENABLE_CSFFW_TRACEPOINTS)
#define BASE_TLSTREAM_FLAGS_MASK \
(BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | BASE_TLSTREAM_JOB_DUMPING_ENABLED | \
BASE_TLSTREAM_ENABLE_CSF_TRACEPOINTS | BASE_TLSTREAM_ENABLE_CSFFW_TRACEPOINTS)
/* Number of pages mapped into the process address space for a bound GPU
* command queue. A pair of input/output pages and a Hw doorbell page
@@ -177,7 +172,7 @@ enum base_kcpu_command_type {
BASE_KCPU_COMMAND_TYPE_JIT_ALLOC,
BASE_KCPU_COMMAND_TYPE_JIT_FREE,
BASE_KCPU_COMMAND_TYPE_GROUP_SUSPEND,
BASE_KCPU_COMMAND_TYPE_ERROR_BARRIER
BASE_KCPU_COMMAND_TYPE_ERROR_BARRIER,
};
/**

95
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_ioctl.h
View File

@@ -82,10 +82,23 @@
* - Relax the requirement to create a mapping with BASE_MEM_MAP_TRACKING_HANDLE
* before allocating GPU memory for the context.
* - CPU mappings of USER_BUFFER imported memory handles must be cached.
* 1.19:
* - Add NE support in queue_group_create IOCTL fields
* - Previous version retained as KBASE_IOCTL_CS_QUEUE_GROUP_CREATE_1_18 for
* backward compatibility.
* 1.20:
* - Restrict child process from doing supported file operations (like mmap, ioctl,
* read, poll) on the file descriptor of mali device file that was inherited
* from the parent process.
* 1.21:
* - Remove KBASE_IOCTL_HWCNT_READER_SETUP and KBASE_HWCNT_READER_* ioctls.
* 1.22:
* - Add comp_pri_threshold and comp_pri_ratio attributes to
* kbase_ioctl_cs_queue_group_create.
*/
#define BASE_UK_VERSION_MAJOR 1
#define BASE_UK_VERSION_MINOR 18
#define BASE_UK_VERSION_MINOR 22
/**
* struct kbase_ioctl_version_check - Check version compatibility between
@@ -134,8 +147,7 @@ struct kbase_ioctl_cs_queue_kick {
__u64 buffer_gpu_addr;
};
#define KBASE_IOCTL_CS_QUEUE_KICK \
_IOW(KBASE_IOCTL_TYPE, 37, struct kbase_ioctl_cs_queue_kick)
#define KBASE_IOCTL_CS_QUEUE_KICK _IOW(KBASE_IOCTL_TYPE, 37, struct kbase_ioctl_cs_queue_kick)
/**
* union kbase_ioctl_cs_queue_bind - Bind a GPU command queue to a group
@@ -161,8 +173,7 @@ union kbase_ioctl_cs_queue_bind {
} out;
};
#define KBASE_IOCTL_CS_QUEUE_BIND \
_IOWR(KBASE_IOCTL_TYPE, 39, union kbase_ioctl_cs_queue_bind)
#define KBASE_IOCTL_CS_QUEUE_BIND _IOWR(KBASE_IOCTL_TYPE, 39, union kbase_ioctl_cs_queue_bind)
/**
* struct kbase_ioctl_cs_queue_register_ex - Register a GPU command queue with the
@@ -254,9 +265,59 @@ union kbase_ioctl_cs_queue_group_create_1_6 {
} out;
};
#define KBASE_IOCTL_CS_QUEUE_GROUP_CREATE_1_6 \
#define KBASE_IOCTL_CS_QUEUE_GROUP_CREATE_1_6 \
_IOWR(KBASE_IOCTL_TYPE, 42, union kbase_ioctl_cs_queue_group_create_1_6)
/**
* union kbase_ioctl_cs_queue_group_create_1_18 - Create a GPU command queue group
* @in: Input parameters
* @in.tiler_mask: Mask of tiler endpoints the group is allowed to use.
* @in.fragment_mask: Mask of fragment endpoints the group is allowed to use.
* @in.compute_mask: Mask of compute endpoints the group is allowed to use.
* @in.cs_min: Minimum number of CSs required.
* @in.priority: Queue group's priority within a process.
* @in.tiler_max: Maximum number of tiler endpoints the group is allowed
* to use.
* @in.fragment_max: Maximum number of fragment endpoints the group is
* allowed to use.
* @in.compute_max: Maximum number of compute endpoints the group is allowed
* to use.
* @in.csi_handlers: Flags to signal that the application intends to use CSI
* exception handlers in some linear buffers to deal with
* the given exception types.
* @in.padding: Currently unused, must be zero
* @out: Output parameters
* @out.group_handle: Handle of a newly created queue group.
* @out.padding: Currently unused, must be zero
* @out.group_uid: UID of the queue group available to base.
*/
union kbase_ioctl_cs_queue_group_create_1_18 {
struct {
__u64 tiler_mask;
__u64 fragment_mask;
__u64 compute_mask;
__u8 cs_min;
__u8 priority;
__u8 tiler_max;
__u8 fragment_max;
__u8 compute_max;
__u8 csi_handlers;
__u8 padding[2];
/**
* @in.dvs_buf: buffer for deferred vertex shader
*/
__u64 dvs_buf;
} in;
struct {
__u8 group_handle;
__u8 padding[3];
__u32 group_uid;
} out;
};
#define KBASE_IOCTL_CS_QUEUE_GROUP_CREATE_1_18 \
_IOWR(KBASE_IOCTL_TYPE, 58, union kbase_ioctl_cs_queue_group_create_1_18)
/**
* union kbase_ioctl_cs_queue_group_create - Create a GPU command queue group
* @in: Input parameters
@@ -291,11 +352,15 @@ union kbase_ioctl_cs_queue_group_create {
__u8 fragment_max;
__u8 compute_max;
__u8 csi_handlers;
__u8 padding[2];
/**
* @in.reserved: Reserved, currently unused, must be zero.
*/
__u16 reserved;
/**
* @in.dvs_buf: buffer for deferred vertex shader
*/
__u64 dvs_buf;
__u64 padding[9];
} in;
struct {
__u8 group_handle;
@@ -304,7 +369,7 @@ union kbase_ioctl_cs_queue_group_create {
} out;
};
#define KBASE_IOCTL_CS_QUEUE_GROUP_CREATE \
#define KBASE_IOCTL_CS_QUEUE_GROUP_CREATE \
_IOWR(KBASE_IOCTL_TYPE, 58, union kbase_ioctl_cs_queue_group_create)
/**
@@ -321,8 +386,7 @@ struct kbase_ioctl_cs_queue_group_term {
#define KBASE_IOCTL_CS_QUEUE_GROUP_TERMINATE \
_IOW(KBASE_IOCTL_TYPE, 43, struct kbase_ioctl_cs_queue_group_term)
#define KBASE_IOCTL_CS_EVENT_SIGNAL \
_IO(KBASE_IOCTL_TYPE, 44)
#define KBASE_IOCTL_CS_EVENT_SIGNAL _IO(KBASE_IOCTL_TYPE, 44)
typedef __u8 base_kcpu_queue_id; /* We support up to 256 active KCPU queues */
@@ -337,8 +401,7 @@ struct kbase_ioctl_kcpu_queue_new {
__u8 padding[7];
};
#define KBASE_IOCTL_KCPU_QUEUE_CREATE \
_IOR(KBASE_IOCTL_TYPE, 45, struct kbase_ioctl_kcpu_queue_new)
#define KBASE_IOCTL_KCPU_QUEUE_CREATE _IOR(KBASE_IOCTL_TYPE, 45, struct kbase_ioctl_kcpu_queue_new)
/**
* struct kbase_ioctl_kcpu_queue_delete - Destroy a KCPU command queue
@@ -444,7 +507,7 @@ union kbase_ioctl_cs_tiler_heap_init_1_13 {
} out;
};
#define KBASE_IOCTL_CS_TILER_HEAP_INIT_1_13 \
#define KBASE_IOCTL_CS_TILER_HEAP_INIT_1_13 \
_IOWR(KBASE_IOCTL_TYPE, 48, union kbase_ioctl_cs_tiler_heap_init_1_13)
/**
@@ -503,16 +566,14 @@ union kbase_ioctl_cs_get_glb_iface {
} out;
};
#define KBASE_IOCTL_CS_GET_GLB_IFACE \
_IOWR(KBASE_IOCTL_TYPE, 51, union kbase_ioctl_cs_get_glb_iface)
#define KBASE_IOCTL_CS_GET_GLB_IFACE _IOWR(KBASE_IOCTL_TYPE, 51, union kbase_ioctl_cs_get_glb_iface)
struct kbase_ioctl_cs_cpu_queue_info {
__u64 buffer;
__u64 size;
};
#define KBASE_IOCTL_VERSION_CHECK \
_IOWR(KBASE_IOCTL_TYPE, 52, struct kbase_ioctl_version_check)
#define KBASE_IOCTL_VERSION_CHECK _IOWR(KBASE_IOCTL_TYPE, 52, struct kbase_ioctl_version_check)
#define KBASE_IOCTL_CS_CPU_QUEUE_DUMP \
_IOW(KBASE_IOCTL_TYPE, 53, struct kbase_ioctl_cs_cpu_queue_info)

7
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_csf.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2021-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,11 +22,6 @@
#ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_
#define _UAPI_KBASE_GPU_REGMAP_CSF_H_
/* IPA control registers */
#define IPA_CONTROL_BASE 0x40000
#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE + (r))
#define STATUS 0x004 /* (RO) Status register */
/* USER base address */
#define USER_BASE 0x0010000
#define USER_REG(r) (USER_BASE + (r))

27
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_jm.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,29 +22,4 @@
#ifndef _UAPI_KBASE_GPU_REGMAP_JM_H_
#define _UAPI_KBASE_GPU_REGMAP_JM_H_
/* GPU control registers */
#define LATEST_FLUSH 0x038 /* (RO) Flush ID of latest clean-and-invalidate operation */
/* Job control registers */
#define JS_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */
#define JS_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */
#define JS_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */
#define JS_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */
#define JS_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */
#define JS_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */
#define JS_CONFIG 0x18 /* (RO) Configuration settings for job slot n */
#define JS_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */
#define JS_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */
#define JS_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */
#define JS_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */
#define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */
#define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */
#define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */
#define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
#endif /* _UAPI_KBASE_GPU_REGMAP_JM_H_ */

6
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_coherency.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -23,8 +23,8 @@
#define _UAPI_KBASE_GPU_COHERENCY_H_
#define COHERENCY_ACE_LITE 0
#define COHERENCY_ACE 1
#define COHERENCY_NONE 31
#define COHERENCY_ACE 1
#define COHERENCY_NONE 31
#define COHERENCY_FEATURE_BIT(x) (1 << (x))
#endif /* _UAPI_KBASE_GPU_COHERENCY_H_ */

200
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_id.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,124 +22,156 @@
#ifndef _UAPI_KBASE_GPU_ID_H_
#define _UAPI_KBASE_GPU_ID_H_
#if defined(__linux)
#include <linux/types.h>
#endif
/* GPU_ID register */
#define KBASE_GPU_ID_VERSION_STATUS_SHIFT 0
#define KBASE_GPU_ID_VERSION_MINOR_SHIFT 4
#define KBASE_GPU_ID_VERSION_MAJOR_SHIFT 12
#define KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT 16
#define GPU_ID_VERSION_STATUS (0xFu << KBASE_GPU_ID_VERSION_STATUS_SHIFT)
#define GPU_ID_VERSION_MINOR (0xFFu << KBASE_GPU_ID_VERSION_MINOR_SHIFT)
#define GPU_ID_VERSION_MAJOR (0xFu << KBASE_GPU_ID_VERSION_MAJOR_SHIFT)
#define GPU_ID_VERSION_PRODUCT_ID (0xFFFFu << KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT)
#define GPU_ID2_VERSION_STATUS_SHIFT 0
#define GPU_ID2_VERSION_MINOR_SHIFT 4
#define GPU_ID2_VERSION_MAJOR_SHIFT 12
#define GPU_ID2_PRODUCT_MAJOR_SHIFT 16
#define GPU_ID2_ARCH_REV_SHIFT 20
#define GPU_ID2_ARCH_MINOR_SHIFT 24
#define GPU_ID2_ARCH_MAJOR_SHIFT 28
#define GPU_ID2_VERSION_STATUS (0xFu << GPU_ID2_VERSION_STATUS_SHIFT)
#define GPU_ID2_VERSION_MINOR (0xFFu << GPU_ID2_VERSION_MINOR_SHIFT)
#define GPU_ID2_VERSION_MAJOR (0xFu << GPU_ID2_VERSION_MAJOR_SHIFT)
#define GPU_ID2_PRODUCT_MAJOR (0xFu << GPU_ID2_PRODUCT_MAJOR_SHIFT)
#define GPU_ID2_ARCH_REV (0xFu << GPU_ID2_ARCH_REV_SHIFT)
#define GPU_ID2_ARCH_MINOR (0xFu << GPU_ID2_ARCH_MINOR_SHIFT)
#define GPU_ID2_ARCH_MAJOR (0xFu << GPU_ID2_ARCH_MAJOR_SHIFT)
#define GPU_ID2_PRODUCT_MODEL (GPU_ID2_ARCH_MAJOR | GPU_ID2_PRODUCT_MAJOR)
#define GPU_ID2_VERSION (GPU_ID2_VERSION_MAJOR | \
GPU_ID2_VERSION_MINOR | \
GPU_ID2_VERSION_STATUS)
#define GPU_ID2_VERSION_STATUS_SHIFT 0
#define GPU_ID2_VERSION_MINOR_SHIFT 4
#define GPU_ID2_VERSION_MAJOR_SHIFT 12
#define GPU_ID2_PRODUCT_MAJOR_SHIFT 16
#define GPU_ID2_ARCH_REV_SHIFT 20
#define GPU_ID2_ARCH_MINOR_SHIFT 24
#define GPU_ID2_ARCH_MAJOR_SHIFT 28
#define GPU_ID2_VERSION_STATUS (0xFu << GPU_ID2_VERSION_STATUS_SHIFT)
#define GPU_ID2_VERSION_MINOR (0xFFu << GPU_ID2_VERSION_MINOR_SHIFT)
#define GPU_ID2_VERSION_MAJOR (0xFu << GPU_ID2_VERSION_MAJOR_SHIFT)
#define GPU_ID2_PRODUCT_MAJOR (0xFu << GPU_ID2_PRODUCT_MAJOR_SHIFT)
#define GPU_ID2_ARCH_REV (0xFu << GPU_ID2_ARCH_REV_SHIFT)
#define GPU_ID2_ARCH_MINOR (0xFu << GPU_ID2_ARCH_MINOR_SHIFT)
#define GPU_ID2_ARCH_MAJOR (0xFu << GPU_ID2_ARCH_MAJOR_SHIFT)
#define GPU_ID2_PRODUCT_MODEL (GPU_ID2_ARCH_MAJOR | GPU_ID2_PRODUCT_MAJOR)
#define GPU_ID2_VERSION (GPU_ID2_VERSION_MAJOR | GPU_ID2_VERSION_MINOR | GPU_ID2_VERSION_STATUS)
#define GPU_ID2_ARCH_REV_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_ARCH_REV) >> GPU_ID2_ARCH_REV_SHIFT)
#define GPU_ID2_ARCH_MINOR_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_ARCH_MINOR) >> GPU_ID2_ARCH_MINOR_SHIFT)
#define GPU_ID2_ARCH_MAJOR_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_ARCH_MAJOR) >> GPU_ID2_ARCH_MAJOR_SHIFT)
#define GPU_ID2_VERSION_MINOR_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_VERSION_MINOR) >> GPU_ID2_VERSION_MINOR_SHIFT)
#define GPU_ID2_VERSION_MAJOR_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_VERSION_MAJOR) >> GPU_ID2_VERSION_MAJOR_SHIFT)
#define GPU_ID2_PRODUCT_MAJOR_GET(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_PRODUCT_MAJOR) >> GPU_ID2_PRODUCT_MAJOR_SHIFT)
/* Helper macro to construct a value consisting of arch major and revision
* using the value of gpu_id.
*/
#define ARCH_MAJOR_REV_REG(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_ARCH_MAJOR) | \
(((__u32)gpu_id) & GPU_ID2_ARCH_REV))
#define GPU_ID2_ARCH_MAJOR_REV_REG(gpu_id) \
((((__u32)gpu_id) & GPU_ID2_ARCH_MAJOR) | (((__u32)gpu_id) & GPU_ID2_ARCH_REV))
/* Helper macro to create a partial GPU_ID (new format) that defines
* a arch major and revision.
*/
#define GPU_ID2_ARCH_MAJOR_REV_MAKE(arch_major, arch_rev) \
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
#define GPU_ID2_ARCH_MAJOR_REV_MAKE(arch_major, arch_rev) \
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
(((__u32)arch_rev) << GPU_ID2_ARCH_REV_SHIFT))
/* Helper macro to create a partial GPU_ID (new format) that defines
* a product ignoring its version.
*/
#define GPU_ID2_PRODUCT_MAKE(arch_major, arch_minor, arch_rev, product_major) \
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
(((__u32)arch_minor) << GPU_ID2_ARCH_MINOR_SHIFT) | \
(((__u32)arch_rev) << GPU_ID2_ARCH_REV_SHIFT) | \
(((__u32)product_major) << GPU_ID2_PRODUCT_MAJOR_SHIFT))
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
(((__u32)arch_minor) << GPU_ID2_ARCH_MINOR_SHIFT) | \
(((__u32)arch_rev) << GPU_ID2_ARCH_REV_SHIFT) | \
(((__u32)product_major) << GPU_ID2_PRODUCT_MAJOR_SHIFT))
/* Helper macro to create a partial GPU_ID (new format) that specifies the
* revision (major, minor, status) of a product
*/
#define GPU_ID2_VERSION_MAKE(version_major, version_minor, version_status) \
((((__u32)version_major) << GPU_ID2_VERSION_MAJOR_SHIFT) | \
(((__u32)version_minor) << GPU_ID2_VERSION_MINOR_SHIFT) | \
(((__u32)version_status) << GPU_ID2_VERSION_STATUS_SHIFT))
((((__u32)version_major) << GPU_ID2_VERSION_MAJOR_SHIFT) | \
(((__u32)version_minor) << GPU_ID2_VERSION_MINOR_SHIFT) | \
(((__u32)version_status) << GPU_ID2_VERSION_STATUS_SHIFT))
/* Helper macro to create a complete GPU_ID (new format) */
#define GPU_ID2_MAKE(arch_major, arch_minor, arch_rev, product_major, \
version_major, version_minor, version_status) \
(GPU_ID2_PRODUCT_MAKE(arch_major, arch_minor, arch_rev, \
product_major) | \
GPU_ID2_VERSION_MAKE(version_major, version_minor, \
version_status))
#define GPU_ID2_MAKE(arch_major, arch_minor, arch_rev, product_major, version_major, \
version_minor, version_status) \
(GPU_ID2_PRODUCT_MAKE(arch_major, arch_minor, arch_rev, product_major) | \
GPU_ID2_VERSION_MAKE(version_major, version_minor, version_status))
/* Helper macro to create a partial GPU_ID (new format) that identifies
* a particular GPU model by its arch_major and product_major.
*/
#define GPU_ID2_MODEL_MAKE(arch_major, product_major) \
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
(((__u32)product_major) << GPU_ID2_PRODUCT_MAJOR_SHIFT))
#define GPU_ID2_MODEL_MAKE(arch_major, product_major) \
((((__u32)arch_major) << GPU_ID2_ARCH_MAJOR_SHIFT) | \
(((__u32)product_major) << GPU_ID2_PRODUCT_MAJOR_SHIFT))
/* Strip off the non-relevant bits from a product_id value and make it suitable
* for comparison against the GPU_ID2_PRODUCT_xxx values which identify a GPU
* model.
*/
#define GPU_ID2_MODEL_MATCH_VALUE(product_id) \
((((__u32)product_id) << GPU_ID2_PRODUCT_MAJOR_SHIFT) & \
GPU_ID2_PRODUCT_MODEL)
((((__u32)product_id) << GPU_ID2_PRODUCT_MAJOR_SHIFT) & GPU_ID2_PRODUCT_MODEL)
#define GPU_ID2_PRODUCT_TMIX GPU_ID2_MODEL_MAKE(6, 0)
#define GPU_ID2_PRODUCT_THEX GPU_ID2_MODEL_MAKE(6, 1)
#define GPU_ID2_PRODUCT_TSIX GPU_ID2_MODEL_MAKE(7, 0)
#define GPU_ID2_PRODUCT_TDVX GPU_ID2_MODEL_MAKE(7, 3)
#define GPU_ID2_PRODUCT_TNOX GPU_ID2_MODEL_MAKE(7, 1)
#define GPU_ID2_PRODUCT_TGOX GPU_ID2_MODEL_MAKE(7, 2)
#define GPU_ID2_PRODUCT_TTRX GPU_ID2_MODEL_MAKE(9, 0)
#define GPU_ID2_PRODUCT_TNAX GPU_ID2_MODEL_MAKE(9, 1)
#define GPU_ID2_PRODUCT_TBEX GPU_ID2_MODEL_MAKE(9, 2)
#define GPU_ID2_PRODUCT_LBEX GPU_ID2_MODEL_MAKE(9, 4)
#define GPU_ID2_PRODUCT_TBAX GPU_ID2_MODEL_MAKE(9, 5)
#define GPU_ID2_PRODUCT_TODX GPU_ID2_MODEL_MAKE(10, 2)
#define GPU_ID2_PRODUCT_TGRX GPU_ID2_MODEL_MAKE(10, 3)
#define GPU_ID2_PRODUCT_TVAX GPU_ID2_MODEL_MAKE(10, 4)
#define GPU_ID2_PRODUCT_LODX GPU_ID2_MODEL_MAKE(10, 7)
#define GPU_ID2_PRODUCT_TTUX GPU_ID2_MODEL_MAKE(11, 2)
#define GPU_ID2_PRODUCT_LTUX GPU_ID2_MODEL_MAKE(11, 3)
#define GPU_ID2_PRODUCT_TTIX GPU_ID2_MODEL_MAKE(12, 0)
#define GPU_ID2_PRODUCT_LTIX GPU_ID2_MODEL_MAKE(12, 1)
#define GPU_ID2_PRODUCT_TMIX GPU_ID2_MODEL_MAKE(6, 0)
#define GPU_ID2_PRODUCT_THEX GPU_ID2_MODEL_MAKE(6, 1)
#define GPU_ID2_PRODUCT_TSIX GPU_ID2_MODEL_MAKE(7, 0)
#define GPU_ID2_PRODUCT_TDVX GPU_ID2_MODEL_MAKE(7, 3)
#define GPU_ID2_PRODUCT_TNOX GPU_ID2_MODEL_MAKE(7, 1)
#define GPU_ID2_PRODUCT_TGOX GPU_ID2_MODEL_MAKE(7, 2)
#define GPU_ID2_PRODUCT_TTRX GPU_ID2_MODEL_MAKE(9, 0)
#define GPU_ID2_PRODUCT_TNAX GPU_ID2_MODEL_MAKE(9, 1)
#define GPU_ID2_PRODUCT_TBEX GPU_ID2_MODEL_MAKE(9, 2)
#define GPU_ID2_PRODUCT_LBEX GPU_ID2_MODEL_MAKE(9, 4)
#define GPU_ID2_PRODUCT_TBAX GPU_ID2_MODEL_MAKE(9, 5)
#define GPU_ID2_PRODUCT_TODX GPU_ID2_MODEL_MAKE(10, 2)
#define GPU_ID2_PRODUCT_TGRX GPU_ID2_MODEL_MAKE(10, 3)
#define GPU_ID2_PRODUCT_TVAX GPU_ID2_MODEL_MAKE(10, 4)
#define GPU_ID2_PRODUCT_LODX GPU_ID2_MODEL_MAKE(10, 7)
#define GPU_ID2_PRODUCT_TTUX GPU_ID2_MODEL_MAKE(11, 2)
#define GPU_ID2_PRODUCT_LTUX GPU_ID2_MODEL_MAKE(11, 3)
#define GPU_ID2_PRODUCT_TTIX GPU_ID2_MODEL_MAKE(12, 0)
#define GPU_ID2_PRODUCT_LTIX GPU_ID2_MODEL_MAKE(12, 1)
#define GPU_ID2_PRODUCT_TKRX GPU_ID2_MODEL_MAKE(13, 0)
#define GPU_ID2_PRODUCT_LKRX GPU_ID2_MODEL_MAKE(13, 1)
/**
* GPU_ID_MAKE - Helper macro to generate GPU_ID using id, major, minor, status
*
* @id: Product Major of GPU ID
* @major: Version major of GPU ID
* @minor: Version minor of GPU ID
* @status: Version status of GPU ID
#define GPU_ID_U8_COMP(val3, val2, val1, val0) \
((((__u32)val3) << 24U) | (((__u32)val2) << 16U) | (((__u32)val1) << 8U) | ((__u32)val0))
#define GPU_ID_U8_COMP_SHIFT(comp, idx) (((__u32)comp) >> (idx * 8U))
#define GPU_ID_U8_COMP_GET(comp, idx) (GPU_ID_U8_COMP_SHIFT(comp, idx) & 0xFF)
#define GPU_ID_PRODUCT_ID_MAKE(arch_major, arch_minor, arch_rev, product_major) \
GPU_ID_U8_COMP(arch_major, arch_minor, arch_rev, product_major)
#define GPU_ID_MODEL_MAKE(arch_major, product_major) GPU_ID_U8_COMP(arch_major, 0, 0, product_major)
#define GPU_ID_VERSION_MAKE(version_major, version_minor, version_status) \
GPU_ID_U8_COMP(0, version_major, version_minor, version_status)
#define GPU_ID_ARCH_MAKE(arch_major, arch_minor, arch_rev) \
GPU_ID_U8_COMP(0, arch_major, arch_minor, arch_rev)
/* Convert ID created from GPU_ID_PRODUCT_ID_MAKE() to match the format of
* GPU_ID_MODEL_MAKE()
*/
#define GPU_ID_MAKE(id, major, minor, status) \
((((__u32)id) << KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT) | \
(((__u32)major) << KBASE_GPU_ID_VERSION_MAJOR_SHIFT) | \
(((__u32)minor) << KBASE_GPU_ID_VERSION_MINOR_SHIFT) | \
(((__u32)status) << KBASE_GPU_ID_VERSION_STATUS_SHIFT))
#define GPU_ID_MODEL_MATCH_VALUE(product_id) (((__u32)product_id) & GPU_ID_MODEL_MAKE(0xFF, 0xFF))
#define GPU_ID_VERSION_ID_MAJOR_MINOR_GET(version_id) GPU_ID_U8_COMP_SHIFT(version_id, 1)
#define GPU_ID_VERSION_ID_STATUS_GET(version_id) GPU_ID_U8_COMP_GET(version_id, 0)
#define GPU_ID_VERSION_ID_MINOR_GET(version_id) GPU_ID_U8_COMP_GET(version_id, 1)
#define GPU_ID_VERSION_ID_MAJOR_GET(version_id) GPU_ID_U8_COMP_GET(version_id, 2)
#define GPU_ID_PRODUCT_TMIX GPU_ID_MODEL_MAKE(6, 0)
#define GPU_ID_PRODUCT_THEX GPU_ID_MODEL_MAKE(6, 1)
#define GPU_ID_PRODUCT_TSIX GPU_ID_MODEL_MAKE(7, 0)
#define GPU_ID_PRODUCT_TDVX GPU_ID_MODEL_MAKE(7, 3)
#define GPU_ID_PRODUCT_TNOX GPU_ID_MODEL_MAKE(7, 1)
#define GPU_ID_PRODUCT_TGOX GPU_ID_MODEL_MAKE(7, 2)
#define GPU_ID_PRODUCT_TTRX GPU_ID_MODEL_MAKE(9, 0)
#define GPU_ID_PRODUCT_TNAX GPU_ID_MODEL_MAKE(9, 1)
#define GPU_ID_PRODUCT_TBEX GPU_ID_MODEL_MAKE(9, 2)
#define GPU_ID_PRODUCT_LBEX GPU_ID_MODEL_MAKE(9, 4)
#define GPU_ID_PRODUCT_TBAX GPU_ID_MODEL_MAKE(9, 5)
#define GPU_ID_PRODUCT_TODX GPU_ID_MODEL_MAKE(10, 2)
#define GPU_ID_PRODUCT_TGRX GPU_ID_MODEL_MAKE(10, 3)
#define GPU_ID_PRODUCT_TVAX GPU_ID_MODEL_MAKE(10, 4)
#define GPU_ID_PRODUCT_LODX GPU_ID_MODEL_MAKE(10, 7)
#define GPU_ID_PRODUCT_TTUX GPU_ID_MODEL_MAKE(11, 2)
#define GPU_ID_PRODUCT_LTUX GPU_ID_MODEL_MAKE(11, 3)
#define GPU_ID_PRODUCT_TTIX GPU_ID_MODEL_MAKE(12, 0)
#define GPU_ID_PRODUCT_LTIX GPU_ID_MODEL_MAKE(12, 1)
#define GPU_ID_PRODUCT_TKRX GPU_ID_MODEL_MAKE(13, 0)
#define GPU_ID_PRODUCT_LKRX GPU_ID_MODEL_MAKE(13, 1)
#endif /* _UAPI_KBASE_GPU_ID_H_ */

69
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_regmap.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -28,71 +28,4 @@
#include "backend/mali_kbase_gpu_regmap_jm.h"
#endif /* !MALI_USE_CSF */
/* Begin Register Offsets */
/* GPU control registers */
#define GPU_CONTROL_BASE 0x0000
#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
#define GPU_IRQ_CLEAR 0x024 /* (WO) */
#define GPU_IRQ_STATUS 0x02C /* (RO) */
#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
/* Job control registers */
#define JOB_CONTROL_BASE 0x1000
#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
/* MMU control registers */
#define MEMORY_MANAGEMENT_BASE 0x2000
#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
#define MMU_AS0 0x400 /* Configuration registers for address space 0 */
/* MMU address space control registers */
#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
#define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
#define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
#define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
#define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
#define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
/* (RW) Translation table configuration for address space n, low word */
#define AS_TRANSCFG_LO 0x30
/* (RW) Translation table configuration for address space n, high word */
#define AS_TRANSCFG_HI 0x34
#endif /* _UAPI_KBASE_GPU_REGMAP_H_ */

150
include/uapi/gpu/arm/bifrost/jm/mali_base_jm_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -60,28 +60,26 @@
/* A mask of all the flags which are only valid for allocations within kbase,
* and may not be passed from user space.
*/
#define BASEP_MEM_FLAGS_KERNEL_ONLY \
(BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE | \
BASE_MEM_FLAG_MAP_FIXED | BASEP_MEM_PERFORM_JIT_TRIM)
#define BASEP_MEM_FLAGS_KERNEL_ONLY \
(BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE | BASE_MEM_FLAG_MAP_FIXED | \
BASEP_MEM_PERFORM_JIT_TRIM)
/* A mask of all currently reserved flags
*/
#define BASE_MEM_FLAGS_RESERVED \
(BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_19)
#define BASE_MEM_FLAGS_RESERVED (BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_19)
/* Similar to BASE_MEM_TILER_ALIGN_TOP, memory starting from the end of the
* initial commit is aligned to 'extension' pages, where 'extension' must be a power
* of 2 and no more than BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES
*/
#define BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP (1 << 0)
#define BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP (1 << 0)
/**
* BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE - If set, the heap info address points
* to a __u32 holding the used size in bytes;
* otherwise it points to a __u64 holding the lowest address of unused memory.
*/
#define BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE (1 << 1)
#define BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE (1 << 1)
/**
* BASE_JIT_ALLOC_VALID_FLAGS - Valid set of just-in-time memory allocation flags
@@ -109,26 +107,25 @@
*/
/* Private flag tracking whether job descriptor dumping is disabled */
#define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED \
((base_context_create_flags)(1 << 31))
#define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED ((base_context_create_flags)(1 << 31))
/* Flags for base tracepoint specific to JM */
#define BASE_TLSTREAM_FLAGS_MASK (BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | \
BASE_TLSTREAM_JOB_DUMPING_ENABLED)
#define BASE_TLSTREAM_FLAGS_MASK \
(BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | BASE_TLSTREAM_JOB_DUMPING_ENABLED)
/*
* Dependency stuff, keep it private for now. May want to expose it if
* we decide to make the number of semaphores a configurable
* option.
*/
#define BASE_JD_ATOM_COUNT 256
#define BASE_JD_ATOM_COUNT 256
/* Maximum number of concurrent render passes.
*/
#define BASE_JD_RP_COUNT (256)
/* Set/reset values for a software event */
#define BASE_JD_SOFT_EVENT_SET ((unsigned char)1)
#define BASE_JD_SOFT_EVENT_RESET ((unsigned char)0)
#define BASE_JD_SOFT_EVENT_SET ((unsigned char)1)
#define BASE_JD_SOFT_EVENT_RESET ((unsigned char)0)
/**
* struct base_jd_udata - Per-job data
@@ -156,9 +153,9 @@ struct base_jd_udata {
*/
typedef __u8 base_jd_dep_type;
#define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */
#define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */
#define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */
#define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */
#define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */
#define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */
/**
* typedef base_jd_core_req - Job chain hardware requirements.
@@ -180,7 +177,7 @@ typedef __u32 base_jd_core_req;
/* Requires fragment shaders
*/
#define BASE_JD_REQ_FS ((base_jd_core_req)1 << 0)
#define BASE_JD_REQ_FS ((base_jd_core_req)1 << 0)
/* Requires compute shaders
*
@@ -196,20 +193,20 @@ typedef __u32 base_jd_core_req;
#define BASE_JD_REQ_CS ((base_jd_core_req)1 << 1)
/* Requires tiling */
#define BASE_JD_REQ_T ((base_jd_core_req)1 << 2)
#define BASE_JD_REQ_T ((base_jd_core_req)1 << 2)
/* Requires cache flushes */
#define BASE_JD_REQ_CF ((base_jd_core_req)1 << 3)
/* Requires value writeback */
#define BASE_JD_REQ_V ((base_jd_core_req)1 << 4)
#define BASE_JD_REQ_V ((base_jd_core_req)1 << 4)
/* SW-only requirements - the HW does not expose these as part of the job slot
* capabilities
*/
/* Requires fragment job with AFBC encoding */
#define BASE_JD_REQ_FS_AFBC ((base_jd_core_req)1 << 13)
#define BASE_JD_REQ_FS_AFBC ((base_jd_core_req)1 << 13)
/* SW-only requirement: coalesce completion events.
* If this bit is set then completion of this atom will not cause an event to
@@ -223,29 +220,29 @@ typedef __u32 base_jd_core_req;
/* SW Only requirement: the job chain requires a coherent core group. We don't
* mind which coherent core group is used.
*/
#define BASE_JD_REQ_COHERENT_GROUP ((base_jd_core_req)1 << 6)
#define BASE_JD_REQ_COHERENT_GROUP ((base_jd_core_req)1 << 6)
/* SW Only requirement: The performance counters should be enabled only when
* they are needed, to reduce power consumption.
*/
#define BASE_JD_REQ_PERMON ((base_jd_core_req)1 << 7)
#define BASE_JD_REQ_PERMON ((base_jd_core_req)1 << 7)
/* SW Only requirement: External resources are referenced by this atom.
*
* This bit may not be used in combination with BASE_JD_REQ_EVENT_COALESCE and
* BASE_JD_REQ_SOFT_EVENT_WAIT.
*/
#define BASE_JD_REQ_EXTERNAL_RESOURCES ((base_jd_core_req)1 << 8)
#define BASE_JD_REQ_EXTERNAL_RESOURCES ((base_jd_core_req)1 << 8)
/* SW Only requirement: Software defined job. Jobs with this bit set will not be
* submitted to the hardware but will cause some action to happen within the
* driver
*/
#define BASE_JD_REQ_SOFT_JOB ((base_jd_core_req)1 << 9)
#define BASE_JD_REQ_SOFT_JOB ((base_jd_core_req)1 << 9)
#define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
#define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
#define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
#define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1)
#define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2)
#define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3)
/* 0x4 RESERVED for now */
@@ -257,11 +254,11 @@ typedef __u32 base_jd_core_req;
* - BASE_JD_REQ_SOFT_EVENT_RESET: this job resets the event, making it
* possible for other jobs to wait upon. It completes immediately.
*/
#define BASE_JD_REQ_SOFT_EVENT_WAIT (BASE_JD_REQ_SOFT_JOB | 0x5)
#define BASE_JD_REQ_SOFT_EVENT_SET (BASE_JD_REQ_SOFT_JOB | 0x6)
#define BASE_JD_REQ_SOFT_EVENT_RESET (BASE_JD_REQ_SOFT_JOB | 0x7)
#define BASE_JD_REQ_SOFT_EVENT_WAIT (BASE_JD_REQ_SOFT_JOB | 0x5)
#define BASE_JD_REQ_SOFT_EVENT_SET (BASE_JD_REQ_SOFT_JOB | 0x6)
#define BASE_JD_REQ_SOFT_EVENT_RESET (BASE_JD_REQ_SOFT_JOB | 0x7)
#define BASE_JD_REQ_SOFT_DEBUG_COPY (BASE_JD_REQ_SOFT_JOB | 0x8)
#define BASE_JD_REQ_SOFT_DEBUG_COPY (BASE_JD_REQ_SOFT_JOB | 0x8)
/* SW only requirement: Just In Time allocation
*
@@ -278,7 +275,7 @@ typedef __u32 base_jd_core_req;
*
* The job will complete immediately.
*/
#define BASE_JD_REQ_SOFT_JIT_ALLOC (BASE_JD_REQ_SOFT_JOB | 0x9)
#define BASE_JD_REQ_SOFT_JIT_ALLOC (BASE_JD_REQ_SOFT_JOB | 0x9)
/* SW only requirement: Just In Time free
*
@@ -288,7 +285,7 @@ typedef __u32 base_jd_core_req;
*
* The job will complete immediately.
*/
#define BASE_JD_REQ_SOFT_JIT_FREE (BASE_JD_REQ_SOFT_JOB | 0xa)
#define BASE_JD_REQ_SOFT_JIT_FREE (BASE_JD_REQ_SOFT_JOB | 0xa)
/* SW only requirement: Map external resource
*
@@ -297,7 +294,7 @@ typedef __u32 base_jd_core_req;
* passed via the jc element of the atom which is a pointer to a
* base_external_resource_list.
*/
#define BASE_JD_REQ_SOFT_EXT_RES_MAP (BASE_JD_REQ_SOFT_JOB | 0xb)
#define BASE_JD_REQ_SOFT_EXT_RES_MAP (BASE_JD_REQ_SOFT_JOB | 0xb)
/* SW only requirement: Unmap external resource
*
@@ -306,7 +303,7 @@ typedef __u32 base_jd_core_req;
* passed via the jc element of the atom which is a pointer to a
* base_external_resource_list.
*/
#define BASE_JD_REQ_SOFT_EXT_RES_UNMAP (BASE_JD_REQ_SOFT_JOB | 0xc)
#define BASE_JD_REQ_SOFT_EXT_RES_UNMAP (BASE_JD_REQ_SOFT_JOB | 0xc)
/* HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders)
*
@@ -316,7 +313,7 @@ typedef __u32 base_jd_core_req;
* In contrast to BASE_JD_REQ_CS, this does not indicate that the Job
* Chain contains 'Geometry Shader' or 'Vertex Shader' jobs.
*/
#define BASE_JD_REQ_ONLY_COMPUTE ((base_jd_core_req)1 << 10)
#define BASE_JD_REQ_ONLY_COMPUTE ((base_jd_core_req)1 << 10)
/* HW Requirement: Use the base_jd_atom::device_nr field to specify a
* particular core group
@@ -331,7 +328,7 @@ typedef __u32 base_jd_core_req;
/* SW Flag: If this bit is set then the successful completion of this atom
* will not cause an event to be sent to userspace
*/
#define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE ((base_jd_core_req)1 << 12)
#define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE ((base_jd_core_req)1 << 12)
/* SW Flag: If this bit is set then completion of this atom will not cause an
* event to be sent to userspace, whether successful or not.
@@ -408,23 +405,22 @@ typedef __u32 base_jd_core_req;
/* These requirement bits are currently unused in base_jd_core_req
*/
#define BASEP_JD_REQ_RESERVED \
(~(BASE_JD_REQ_ATOM_TYPE | BASE_JD_REQ_EXTERNAL_RESOURCES | \
BASE_JD_REQ_EVENT_ONLY_ON_FAILURE | BASEP_JD_REQ_EVENT_NEVER | \
BASE_JD_REQ_EVENT_COALESCE | \
BASE_JD_REQ_COHERENT_GROUP | BASE_JD_REQ_SPECIFIC_COHERENT_GROUP | \
BASE_JD_REQ_FS_AFBC | BASE_JD_REQ_PERMON | \
BASE_JD_REQ_SKIP_CACHE_START | BASE_JD_REQ_SKIP_CACHE_END | \
BASE_JD_REQ_JOB_SLOT | BASE_JD_REQ_START_RENDERPASS | \
BASE_JD_REQ_END_RENDERPASS | BASE_JD_REQ_LIMITED_CORE_MASK))
#define BASEP_JD_REQ_RESERVED \
(~(BASE_JD_REQ_ATOM_TYPE | BASE_JD_REQ_EXTERNAL_RESOURCES | \
BASE_JD_REQ_EVENT_ONLY_ON_FAILURE | BASEP_JD_REQ_EVENT_NEVER | \
BASE_JD_REQ_EVENT_COALESCE | BASE_JD_REQ_COHERENT_GROUP | \
BASE_JD_REQ_SPECIFIC_COHERENT_GROUP | BASE_JD_REQ_FS_AFBC | BASE_JD_REQ_PERMON | \
BASE_JD_REQ_SKIP_CACHE_START | BASE_JD_REQ_SKIP_CACHE_END | BASE_JD_REQ_JOB_SLOT | \
BASE_JD_REQ_START_RENDERPASS | BASE_JD_REQ_END_RENDERPASS | \
BASE_JD_REQ_LIMITED_CORE_MASK))
/* Mask of all bits in base_jd_core_req that control the type of the atom.
*
* This allows dependency only atoms to have flags set
*/
#define BASE_JD_REQ_ATOM_TYPE \
(BASE_JD_REQ_FS | BASE_JD_REQ_CS | BASE_JD_REQ_T | BASE_JD_REQ_CF | \
BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE)
#define BASE_JD_REQ_ATOM_TYPE \
(BASE_JD_REQ_FS | BASE_JD_REQ_CS | BASE_JD_REQ_T | BASE_JD_REQ_CF | BASE_JD_REQ_V | \
BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE)
/**
* BASE_JD_REQ_SOFT_JOB_TYPE - Mask of all bits in base_jd_core_req that
@@ -436,8 +432,7 @@ typedef __u32 base_jd_core_req;
* a dependency only job.
*/
#define BASE_JD_REQ_SOFT_JOB_OR_DEP(core_req) \
(((core_req) & BASE_JD_REQ_SOFT_JOB) || \
((core_req) & BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP)
(((core_req)&BASE_JD_REQ_SOFT_JOB) || ((core_req)&BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP)
/**
* enum kbase_jd_atom_state - Atom states
@@ -571,17 +566,17 @@ struct base_jd_fragment {
typedef __u8 base_jd_prio;
/* Medium atom priority. This is a priority higher than BASE_JD_PRIO_LOW */
#define BASE_JD_PRIO_MEDIUM ((base_jd_prio)0)
#define BASE_JD_PRIO_MEDIUM ((base_jd_prio)0)
/* High atom priority. This is a priority higher than BASE_JD_PRIO_MEDIUM and
* BASE_JD_PRIO_LOW
*/
#define BASE_JD_PRIO_HIGH ((base_jd_prio)1)
#define BASE_JD_PRIO_HIGH ((base_jd_prio)1)
/* Low atom priority. */
#define BASE_JD_PRIO_LOW ((base_jd_prio)2)
#define BASE_JD_PRIO_LOW ((base_jd_prio)2)
/* Real-Time atom priority. This is a priority higher than BASE_JD_PRIO_HIGH,
* BASE_JD_PRIO_MEDIUM, and BASE_JD_PRIO_LOW
*/
#define BASE_JD_PRIO_REALTIME ((base_jd_prio)3)
#define BASE_JD_PRIO_REALTIME ((base_jd_prio)3)
/* Invalid atom priority (max uint8_t value) */
#define BASE_JD_PRIO_INVALID ((base_jd_prio)255)
@@ -709,7 +704,7 @@ enum {
BASE_JD_SW_EVENT_JOB = (0u << 11), /* Job related event */
BASE_JD_SW_EVENT_BAG = (1u << 11), /* Bag related event */
BASE_JD_SW_EVENT_INFO = (2u << 11), /* Misc/info event */
BASE_JD_SW_EVENT_RESERVED = (3u << 11), /* Reserved event type */
BASE_JD_SW_EVENT_RESERVED = (3u << 11), /* Reserved event type */
/* Mask to extract the type from an event code */
BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11)
};
@@ -924,34 +919,29 @@ enum base_jd_event_code {
BASE_JD_EVENT_ACCESS_FLAG = 0xD8,
/* SW defined exceptions */
BASE_JD_EVENT_MEM_GROWTH_FAILED =
BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
BASE_JD_EVENT_JOB_CANCELLED =
BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
BASE_JD_EVENT_JOB_INVALID =
BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
BASE_JD_EVENT_MEM_GROWTH_FAILED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000,
BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002,
BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003,
BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_RESERVED | 0x3FF,
BASE_JD_SW_EVENT_RESERVED | 0x3FF,
BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_SUCCESS | 0x000,
BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 0x000,
BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000,
BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS |
BASE_JD_SW_EVENT_INFO | 0x000,
BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF,
BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS |
BASE_JD_SW_EVENT_RESERVED | 0x3FF,
BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_KERNEL | 0x000,
BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000,
BASE_JD_EVENT_END_RP_DONE = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x001,
BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL | 0x000,
BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL |
BASE_JD_SW_EVENT_JOB | 0x000,
BASE_JD_EVENT_END_RP_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL |
BASE_JD_SW_EVENT_JOB | 0x001,
BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT |
BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF
BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_KERNEL |
BASE_JD_SW_EVENT_RESERVED | 0x3FF
};
/**

23
include/uapi/gpu/arm/bifrost/jm/mali_kbase_jm_ioctl.h
View File

@@ -143,9 +143,16 @@
* - Relax the requirement to create a mapping with BASE_MEM_MAP_TRACKING_HANDLE
* before allocating GPU memory for the context.
* - CPU mappings of USER_BUFFER imported memory handles must be cached.
* 11.39:
* - Restrict child process from doing supported file operations (like mmap, ioctl,
* read, poll) on the file descriptor of mali device file that was inherited
* from the parent process.
* 11.40:
* - Remove KBASE_IOCTL_HWCNT_READER_SETUP and KBASE_HWCNT_READER_* ioctls.
*/
#define BASE_UK_VERSION_MAJOR 11
#define BASE_UK_VERSION_MINOR 38
#define BASE_UK_VERSION_MINOR 40
/**
* struct kbase_ioctl_version_check - Check version compatibility between
@@ -159,9 +166,7 @@ struct kbase_ioctl_version_check {
__u16 minor;
};
#define KBASE_IOCTL_VERSION_CHECK \
_IOWR(KBASE_IOCTL_TYPE, 0, struct kbase_ioctl_version_check)
#define KBASE_IOCTL_VERSION_CHECK _IOWR(KBASE_IOCTL_TYPE, 0, struct kbase_ioctl_version_check)
/**
* struct kbase_ioctl_job_submit - Submit jobs/atoms to the kernel
@@ -176,11 +181,9 @@ struct kbase_ioctl_job_submit {
__u32 stride;
};
#define KBASE_IOCTL_JOB_SUBMIT \
_IOW(KBASE_IOCTL_TYPE, 2, struct kbase_ioctl_job_submit)
#define KBASE_IOCTL_JOB_SUBMIT _IOW(KBASE_IOCTL_TYPE, 2, struct kbase_ioctl_job_submit)
#define KBASE_IOCTL_POST_TERM \
_IO(KBASE_IOCTL_TYPE, 4)
#define KBASE_IOCTL_POST_TERM _IO(KBASE_IOCTL_TYPE, 4)
/**
* struct kbase_ioctl_soft_event_update - Update the status of a soft-event
@@ -237,9 +240,7 @@ union kbase_kinstr_jm_fd {
struct kbase_kinstr_jm_fd_out out;
};
#define KBASE_IOCTL_KINSTR_JM_FD \
_IOWR(KBASE_IOCTL_TYPE, 51, union kbase_kinstr_jm_fd)
#define KBASE_IOCTL_KINSTR_JM_FD _IOWR(KBASE_IOCTL_TYPE, 51, union kbase_kinstr_jm_fd)
#define KBASE_IOCTL_VERSION_CHECK_RESERVED \
_IOWR(KBASE_IOCTL_TYPE, 52, struct kbase_ioctl_version_check)

8
include/uapi/gpu/arm/bifrost/mali_base_common_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2022-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -162,7 +162,7 @@ struct base_mem_handle {
/* A mask for all input bits, including IN/OUT bits.
*/
#define BASE_MEM_FLAGS_INPUT_MASK \
#define BASE_MEM_FLAGS_INPUT_MASK \
(((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK)
/* Special base mem handles.
@@ -206,13 +206,13 @@ typedef __u32 base_context_create_flags;
/* Bitmask used to encode a memory group ID in base_context_create_flags
*/
#define BASEP_CONTEXT_MMU_GROUP_ID_MASK \
#define BASEP_CONTEXT_MMU_GROUP_ID_MASK \
((base_context_create_flags)0xF << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)
/* Bitpattern describing the base_context_create_flags that can be
* passed to the kernel
*/
#define BASEP_CONTEXT_CREATE_KERNEL_FLAGS \
#define BASEP_CONTEXT_CREATE_KERNEL_FLAGS \
(BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED | BASEP_CONTEXT_MMU_GROUP_ID_MASK)
/* Flags for base tracepoint

91
include/uapi/gpu/arm/bifrost/mali_base_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -27,12 +27,11 @@
#define _UAPI_BASE_KERNEL_H_
#include <linux/types.h>
#include "mali_gpu_props.h"
#include "mali_base_mem_priv.h"
#include "gpu/mali_kbase_gpu_id.h"
#include "gpu/mali_kbase_gpu_coherency.h"
#define BASE_MAX_COHERENT_GROUPS 16
#if defined(PAGE_MASK) && defined(PAGE_SHIFT)
#define LOCAL_PAGE_SHIFT PAGE_SHIFT
#define LOCAL_PAGE_LSB ~PAGE_MASK
@@ -71,21 +70,23 @@
*/
typedef __u32 base_mem_alloc_flags;
#define BASE_MEM_FLAGS_MODIFIABLE_NATIVE (BASE_MEM_DONT_NEED)
#define BASE_MEM_FLAGS_MODIFIABLE_IMPORTED_UMM (BASE_MEM_COHERENT_SYSTEM | BASE_MEM_COHERENT_LOCAL)
/* A mask for all the flags which are modifiable via the base_mem_set_flags
* interface.
*/
#define BASE_MEM_FLAGS_MODIFIABLE \
(BASE_MEM_DONT_NEED | BASE_MEM_COHERENT_SYSTEM | \
BASE_MEM_COHERENT_LOCAL)
(BASE_MEM_FLAGS_MODIFIABLE_NATIVE | BASE_MEM_FLAGS_MODIFIABLE_IMPORTED_UMM)
/* A mask of all the flags that can be returned via the base_mem_get_flags()
* interface.
*/
#define BASE_MEM_FLAGS_QUERYABLE \
(BASE_MEM_FLAGS_INPUT_MASK & ~(BASE_MEM_SAME_VA | \
BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_DONT_NEED | \
BASE_MEM_IMPORT_SHARED | BASE_MEM_FLAGS_RESERVED | \
BASEP_MEM_FLAGS_KERNEL_ONLY))
#define BASE_MEM_FLAGS_QUERYABLE \
(BASE_MEM_FLAGS_INPUT_MASK & \
~(BASE_MEM_SAME_VA | BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_IMPORT_SHARED | \
BASE_MEM_FLAGS_RESERVED | BASEP_MEM_FLAGS_KERNEL_ONLY))
/**
* enum base_mem_import_type - Memory types supported by @a base_mem_import
@@ -127,22 +128,21 @@ struct base_mem_import_user_buffer {
};
/* Mask to detect 4GB boundary alignment */
#define BASE_MEM_MASK_4GB 0xfffff000UL
#define BASE_MEM_MASK_4GB 0xfffff000UL
/* Mask to detect 4GB boundary (in page units) alignment */
#define BASE_MEM_PFN_MASK_4GB (BASE_MEM_MASK_4GB >> LOCAL_PAGE_SHIFT)
#define BASE_MEM_PFN_MASK_4GB (BASE_MEM_MASK_4GB >> LOCAL_PAGE_SHIFT)
/* Limit on the 'extension' parameter for an allocation with the
* BASE_MEM_TILER_ALIGN_TOP flag set
*
* This is the same as the maximum limit for a Buffer Descriptor's chunk size
*/
#define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2 \
(21u - (LOCAL_PAGE_SHIFT))
#define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES \
#define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2 (21u - (LOCAL_PAGE_SHIFT))
#define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES \
(1ull << (BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2))
/* Bit mask of cookies used for memory allocation setup */
#define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
#define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
/* Maximum size allowed in a single KBASE_IOCTL_MEM_ALLOC call */
#define KBASE_MEM_ALLOC_MAX_SIZE ((8ull << 30) >> PAGE_SHIFT) /* 8 GB */
@@ -243,10 +243,7 @@ struct base_jit_alloc_info {
__u64 heap_info_gpu_addr;
};
enum base_external_resource_access {
BASE_EXT_RES_ACCESS_SHARED,
BASE_EXT_RES_ACCESS_EXCLUSIVE
};
enum base_external_resource_access { BASE_EXT_RES_ACCESS_SHARED, BASE_EXT_RES_ACCESS_EXCLUSIVE };
struct base_external_resource {
__u64 ext_resource;
@@ -276,8 +273,6 @@ struct base_jd_debug_copy_buffer {
struct base_external_resource extres;
};
#define GPU_MAX_JOB_SLOTS 16
/**
* DOC: User-side Base GPU Property Queries
*
@@ -402,8 +397,8 @@ struct mali_base_gpu_l2_cache_props {
};
struct mali_base_gpu_tiler_props {
__u32 bin_size_bytes; /* Max is 4*2^15 */
__u32 max_active_levels; /* Max is 2^15 */
__u32 bin_size_bytes; /* Max is 4*2^15 */
__u32 max_active_levels; /* Max is 2^15 */
};
/**
@@ -428,11 +423,11 @@ struct mali_base_gpu_thread_props {
__u32 max_threads;
__u32 max_workgroup_size;
__u32 max_barrier_size;
__u16 max_registers;
__u32 max_registers;
__u8 max_task_queue;
__u8 max_thread_group_split;
__u8 impl_tech;
__u8 padding[3];
__u8 padding;
__u32 tls_alloc;
};
@@ -591,24 +586,20 @@ struct base_gpu_props {
struct mali_base_gpu_coherent_group_info coherency_info;
};
#define BASE_MEM_GROUP_ID_GET(flags) \
((flags & BASE_MEM_GROUP_ID_MASK) >> BASEP_MEM_GROUP_ID_SHIFT)
#define BASE_MEM_GROUP_ID_GET(flags) ((flags & BASE_MEM_GROUP_ID_MASK) >> BASEP_MEM_GROUP_ID_SHIFT)
#define BASE_MEM_GROUP_ID_SET(id) \
(((base_mem_alloc_flags)((id < 0 || id >= BASE_MEM_GROUP_COUNT) ? \
BASE_MEM_GROUP_DEFAULT : \
id) \
<< BASEP_MEM_GROUP_ID_SHIFT) & \
#define BASE_MEM_GROUP_ID_SET(id) \
(((base_mem_alloc_flags)((id < 0 || id >= BASE_MEM_GROUP_COUNT) ? BASE_MEM_GROUP_DEFAULT : \
id) \
<< BASEP_MEM_GROUP_ID_SHIFT) & \
BASE_MEM_GROUP_ID_MASK)
#define BASE_CONTEXT_MMU_GROUP_ID_SET(group_id) \
(BASEP_CONTEXT_MMU_GROUP_ID_MASK & \
((base_context_create_flags)(group_id) \
<< BASEP_CONTEXT_MMU_GROUP_ID_SHIFT))
#define BASE_CONTEXT_MMU_GROUP_ID_SET(group_id) \
(BASEP_CONTEXT_MMU_GROUP_ID_MASK & \
((base_context_create_flags)(group_id) << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT))
#define BASE_CONTEXT_MMU_GROUP_ID_GET(flags) \
((flags & BASEP_CONTEXT_MMU_GROUP_ID_MASK) >> \
BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)
#define BASE_CONTEXT_MMU_GROUP_ID_GET(flags) \
((flags & BASEP_CONTEXT_MMU_GROUP_ID_MASK) >> BASEP_CONTEXT_MMU_GROUP_ID_SHIFT)
/*
* A number of bit flags are defined for requesting cpu_gpu_timeinfo. These
@@ -617,22 +608,20 @@ struct base_gpu_props {
*/
/* For monotonic (counter) timefield */
#define BASE_TIMEINFO_MONOTONIC_FLAG (1UL << 0)
#define BASE_TIMEINFO_MONOTONIC_FLAG (1U << 0)
/* For system wide timestamp */
#define BASE_TIMEINFO_TIMESTAMP_FLAG (1UL << 1)
#define BASE_TIMEINFO_TIMESTAMP_FLAG (1U << 1)
/* For GPU cycle counter */
#define BASE_TIMEINFO_CYCLE_COUNTER_FLAG (1UL << 2)
#define BASE_TIMEINFO_CYCLE_COUNTER_FLAG (1U << 2)
/* Specify kernel GPU register timestamp */
#define BASE_TIMEINFO_KERNEL_SOURCE_FLAG (1UL << 30)
#define BASE_TIMEINFO_KERNEL_SOURCE_FLAG (1U << 30)
/* Specify userspace cntvct_el0 timestamp source */
#define BASE_TIMEINFO_USER_SOURCE_FLAG (1UL << 31)
#define BASE_TIMEINFO_USER_SOURCE_FLAG (1U << 31)
#define BASE_TIMEREQUEST_ALLOWED_FLAGS (\
BASE_TIMEINFO_MONOTONIC_FLAG | \
BASE_TIMEINFO_TIMESTAMP_FLAG | \
BASE_TIMEINFO_CYCLE_COUNTER_FLAG | \
BASE_TIMEINFO_KERNEL_SOURCE_FLAG | \
BASE_TIMEINFO_USER_SOURCE_FLAG)
#define BASE_TIMEREQUEST_ALLOWED_FLAGS \
(BASE_TIMEINFO_MONOTONIC_FLAG | BASE_TIMEINFO_TIMESTAMP_FLAG | \
BASE_TIMEINFO_CYCLE_COUNTER_FLAG | BASE_TIMEINFO_KERNEL_SOURCE_FLAG | \
BASE_TIMEINFO_USER_SOURCE_FLAG)
/* Maximum number of source allocations allowed to create an alias allocation.
* This needs to be 4096 * 6 to allow cube map arrays with up to 4096 array

6
include/uapi/gpu/arm/bifrost/mali_base_mem_priv.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2010-2015, 2020-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -25,8 +25,8 @@
#include <linux/types.h>
#include "mali_base_common_kernel.h"
#define BASE_SYNCSET_OP_MSYNC (1U << 0)
#define BASE_SYNCSET_OP_CSYNC (1U << 1)
#define BASE_SYNCSET_OP_MSYNC (1U << 0)
#define BASE_SYNCSET_OP_CSYNC (1U << 1)
/*
* This structure describe a basic memory coherency operation.

111
include/uapi/gpu/arm/bifrost/mali_gpu_props.h Normal file
View File

@@ -0,0 +1,111 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
#ifndef _UAPI_MALI_GPUPROPS_H_
#define _UAPI_MALI_GPUPROPS_H_
#include <linux/types.h>
#include "mali_base_common_kernel.h"
#define BASE_MAX_COHERENT_GROUPS 16
#define GPU_MAX_JOB_SLOTS 16
/**
* struct gpu_props_user_data - structure for gpu props user buffer.
* @core_props: Core props.
* @l2_props: L2 props.
* @tiler_props: Tiler props.
* @thread_props: Thread props.
* @raw_props: Raw register values kept for backwards compatibility. Kbase
* and base should never reference values within this struct.
* @coherency_info: Coherency information.
*
* This structure is used solely for the encoding and decoding of the prop_buffer
* returned by kbase.
*/
struct gpu_props_user_data {
struct {
__u32 product_id;
__u16 version_status;
__u16 minor_revision;
__u16 major_revision;
__u32 gpu_freq_khz_max;
__u32 log2_program_counter_size;
__u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
__u64 gpu_available_memory_size;
__u8 num_exec_engines;
} core_props;
struct {
__u8 log2_line_size;
__u8 log2_cache_size;
__u8 num_l2_slices;
} l2_props;
struct {
__u32 bin_size_bytes;
__u32 max_active_levels;
} tiler_props;
struct {
__u32 max_threads;
__u32 max_workgroup_size;
__u32 max_barrier_size;
__u32 max_registers;
__u8 max_task_queue;
__u8 max_thread_group_split;
__u8 impl_tech;
__u32 tls_alloc;
} thread_props;
/* kept for backward compatibility, should not be used in the future. */
struct {
__u64 shader_present;
__u64 tiler_present;
__u64 l2_present;
__u64 stack_present;
__u64 l2_features;
__u64 core_features;
__u64 mem_features;
__u64 mmu_features;
__u32 as_present;
__u32 js_present;
__u32 js_features[GPU_MAX_JOB_SLOTS];
__u64 tiler_features;
__u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS];
__u64 gpu_id;
__u32 thread_max_threads;
__u32 thread_max_workgroup_size;
__u32 thread_max_barrier_size;
__u32 thread_features;
__u32 coherency_mode;
__u32 thread_tls_alloc;
__u64 gpu_features;
} raw_props;
struct {
__u32 num_groups;
__u32 num_core_groups;
__u32 coherency;
struct {
__u64 core_mask;
__u32 num_cores;
} group[BASE_MAX_COHERENT_GROUPS];
} coherency_info;
};
#endif /* _UAPI_MALI_GPUPROPS_H_ */

57
include/uapi/gpu/arm/bifrost/mali_kbase_hwcnt_reader.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015, 2020-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -27,25 +27,26 @@
/* The ids of ioctl commands. */
#define KBASE_HWCNT_READER 0xBE
#define KBASE_HWCNT_READER_GET_HWVER _IOR(KBASE_HWCNT_READER, 0x00, __u32)
#define KBASE_HWCNT_READER_GET_HWVER _IOR(KBASE_HWCNT_READER, 0x00, __u32)
#define KBASE_HWCNT_READER_GET_BUFFER_SIZE _IOR(KBASE_HWCNT_READER, 0x01, __u32)
#define KBASE_HWCNT_READER_DUMP _IOW(KBASE_HWCNT_READER, 0x10, __u32)
#define KBASE_HWCNT_READER_CLEAR _IOW(KBASE_HWCNT_READER, 0x11, __u32)
#define KBASE_HWCNT_READER_GET_BUFFER _IOC(_IOC_READ, KBASE_HWCNT_READER, 0x20,\
offsetof(struct kbase_hwcnt_reader_metadata, cycles))
#define KBASE_HWCNT_READER_GET_BUFFER_WITH_CYCLES _IOR(KBASE_HWCNT_READER, 0x20,\
struct kbase_hwcnt_reader_metadata)
#define KBASE_HWCNT_READER_PUT_BUFFER _IOC(_IOC_WRITE, KBASE_HWCNT_READER, 0x21,\
offsetof(struct kbase_hwcnt_reader_metadata, cycles))
#define KBASE_HWCNT_READER_PUT_BUFFER_WITH_CYCLES _IOW(KBASE_HWCNT_READER, 0x21,\
struct kbase_hwcnt_reader_metadata)
#define KBASE_HWCNT_READER_SET_INTERVAL _IOW(KBASE_HWCNT_READER, 0x30, __u32)
#define KBASE_HWCNT_READER_ENABLE_EVENT _IOW(KBASE_HWCNT_READER, 0x40, __u32)
#define KBASE_HWCNT_READER_DISABLE_EVENT _IOW(KBASE_HWCNT_READER, 0x41, __u32)
#define KBASE_HWCNT_READER_DUMP _IOW(KBASE_HWCNT_READER, 0x10, __u32)
#define KBASE_HWCNT_READER_CLEAR _IOW(KBASE_HWCNT_READER, 0x11, __u32)
#define KBASE_HWCNT_READER_GET_BUFFER \
_IOC(_IOC_READ, KBASE_HWCNT_READER, 0x20, \
offsetof(struct kbase_hwcnt_reader_metadata, cycles))
#define KBASE_HWCNT_READER_GET_BUFFER_WITH_CYCLES \
_IOR(KBASE_HWCNT_READER, 0x20, struct kbase_hwcnt_reader_metadata)
#define KBASE_HWCNT_READER_PUT_BUFFER \
_IOC(_IOC_WRITE, KBASE_HWCNT_READER, 0x21, \
offsetof(struct kbase_hwcnt_reader_metadata, cycles))
#define KBASE_HWCNT_READER_PUT_BUFFER_WITH_CYCLES \
_IOW(KBASE_HWCNT_READER, 0x21, struct kbase_hwcnt_reader_metadata)
#define KBASE_HWCNT_READER_SET_INTERVAL _IOW(KBASE_HWCNT_READER, 0x30, __u32)
#define KBASE_HWCNT_READER_ENABLE_EVENT _IOW(KBASE_HWCNT_READER, 0x40, __u32)
#define KBASE_HWCNT_READER_DISABLE_EVENT _IOW(KBASE_HWCNT_READER, 0x41, __u32)
#define KBASE_HWCNT_READER_GET_API_VERSION _IOW(KBASE_HWCNT_READER, 0xFF, __u32)
#define KBASE_HWCNT_READER_GET_API_VERSION_WITH_FEATURES \
_IOW(KBASE_HWCNT_READER, 0xFF, \
struct kbase_hwcnt_reader_api_version)
_IOW(KBASE_HWCNT_READER, 0xFF, struct kbase_hwcnt_reader_api_version)
/**
* struct kbase_hwcnt_reader_metadata_cycles - GPU clock cycles
@@ -117,8 +118,7 @@ enum prfcnt_list_type {
PRFCNT_LIST_TYPE_SAMPLE_META,
};
#define FLEX_LIST_TYPE(type, subtype) \
((__u16)(((type & 0xf) << 12) | (subtype & 0xfff)))
#define FLEX_LIST_TYPE(type, subtype) ((__u16)(((type & 0xf) << 12) | (subtype & 0xfff)))
#define FLEX_LIST_TYPE_NONE FLEX_LIST_TYPE(0, 0)
#define PRFCNT_ENUM_TYPE_BLOCK FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_ENUM, 0)
@@ -129,12 +129,9 @@ enum prfcnt_list_type {
#define PRFCNT_REQUEST_TYPE_ENABLE FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_REQUEST, 1)
#define PRFCNT_REQUEST_TYPE_SCOPE FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_REQUEST, 2)
#define PRFCNT_SAMPLE_META_TYPE_SAMPLE \
FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 0)
#define PRFCNT_SAMPLE_META_TYPE_CLOCK \
FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 1)
#define PRFCNT_SAMPLE_META_TYPE_BLOCK \
FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 2)
#define PRFCNT_SAMPLE_META_TYPE_SAMPLE FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 0)
#define PRFCNT_SAMPLE_META_TYPE_CLOCK FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 1)
#define PRFCNT_SAMPLE_META_TYPE_BLOCK FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_SAMPLE_META, 2)
/**
* struct prfcnt_item_header - Header for an item of the list.
@@ -152,6 +149,8 @@ struct prfcnt_item_header {
* @PRFCNT_BLOCK_TYPE_TILER: Tiler.
* @PRFCNT_BLOCK_TYPE_MEMORY: Memory System.
* @PRFCNT_BLOCK_TYPE_SHADER_CORE: Shader Core.
* @PRFCNT_BLOCK_TYPE_FW: Firmware.
* @PRFCNT_BLOCK_TYPE_CSG: CSG.
* @PRFCNT_BLOCK_TYPE_RESERVED: Reserved.
*/
enum prfcnt_block_type {
@@ -159,6 +158,8 @@ enum prfcnt_block_type {
PRFCNT_BLOCK_TYPE_TILER,
PRFCNT_BLOCK_TYPE_MEMORY,
PRFCNT_BLOCK_TYPE_SHADER_CORE,
PRFCNT_BLOCK_TYPE_FW,
PRFCNT_BLOCK_TYPE_CSG,
PRFCNT_BLOCK_TYPE_RESERVED = 255,
};
@@ -491,13 +492,13 @@ struct prfcnt_sample_access {
/* The ids of ioctl commands, on a reader file descriptor, magic number */
#define KBASE_KINSTR_PRFCNT_READER 0xBF
/* Ioctl ID for issuing a session operational command */
#define KBASE_IOCTL_KINSTR_PRFCNT_CMD \
#define KBASE_IOCTL_KINSTR_PRFCNT_CMD \
_IOW(KBASE_KINSTR_PRFCNT_READER, 0x00, struct prfcnt_control_cmd)
/* Ioctl ID for fetching a dumpped sample */
#define KBASE_IOCTL_KINSTR_PRFCNT_GET_SAMPLE \
#define KBASE_IOCTL_KINSTR_PRFCNT_GET_SAMPLE \
_IOR(KBASE_KINSTR_PRFCNT_READER, 0x01, struct prfcnt_sample_access)
/* Ioctl ID for release internal buffer of the previously fetched sample */
#define KBASE_IOCTL_KINSTR_PRFCNT_PUT_SAMPLE \
#define KBASE_IOCTL_KINSTR_PRFCNT_PUT_SAMPLE \
_IOW(KBASE_KINSTR_PRFCNT_READER, 0x10, struct prfcnt_sample_access)
#endif /* _UAPI_KBASE_HWCNT_READER_H_ */

26
include/uapi/gpu/arm/bifrost/mali_kbase_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2017-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2017-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,7 +22,7 @@
#ifndef _UAPI_KBASE_IOCTL_H_
#define _UAPI_KBASE_IOCTL_H_
#ifdef __cpluscplus
#ifdef __cplusplus
extern "C" {
#endif
@@ -162,7 +162,7 @@ struct kbase_ioctl_hwcnt_reader_setup {
__u32 mmu_l2_bm;
};
#define KBASE_IOCTL_HWCNT_READER_SETUP \
#define KBASE_IOCTL_HWCNT_READER_SETUP \
_IOW(KBASE_IOCTL_TYPE, 8, struct kbase_ioctl_hwcnt_reader_setup)
/**
@@ -276,7 +276,7 @@ union kbase_ioctl_mem_find_cpu_offset {
} out;
};
#define KBASE_IOCTL_MEM_FIND_CPU_OFFSET \
#define KBASE_IOCTL_MEM_FIND_CPU_OFFSET \
_IOWR(KBASE_IOCTL_TYPE, 16, union kbase_ioctl_mem_find_cpu_offset)
/**
@@ -445,7 +445,7 @@ struct kbase_ioctl_sticky_resource_map {
__u64 address;
};
#define KBASE_IOCTL_STICKY_RESOURCE_MAP \
#define KBASE_IOCTL_STICKY_RESOURCE_MAP \
_IOW(KBASE_IOCTL_TYPE, 29, struct kbase_ioctl_sticky_resource_map)
/**
@@ -459,7 +459,7 @@ struct kbase_ioctl_sticky_resource_unmap {
__u64 address;
};
#define KBASE_IOCTL_STICKY_RESOURCE_UNMAP \
#define KBASE_IOCTL_STICKY_RESOURCE_UNMAP \
_IOW(KBASE_IOCTL_TYPE, 30, struct kbase_ioctl_sticky_resource_unmap)
/**
@@ -487,7 +487,7 @@ union kbase_ioctl_mem_find_gpu_start_and_offset {
} out;
};
#define KBASE_IOCTL_MEM_FIND_GPU_START_AND_OFFSET \
#define KBASE_IOCTL_MEM_FIND_GPU_START_AND_OFFSET \
_IOWR(KBASE_IOCTL_TYPE, 31, union kbase_ioctl_mem_find_gpu_start_and_offset)
#define KBASE_IOCTL_CINSTR_GWT_START _IO(KBASE_IOCTL_TYPE, 33)
@@ -565,7 +565,7 @@ union kbase_ioctl_get_cpu_gpu_timeinfo {
} out;
};
#define KBASE_IOCTL_GET_CPU_GPU_TIMEINFO \
#define KBASE_IOCTL_GET_CPU_GPU_TIMEINFO \
_IOWR(KBASE_IOCTL_TYPE, 50, union kbase_ioctl_get_cpu_gpu_timeinfo)
/**
@@ -577,7 +577,7 @@ struct kbase_ioctl_context_priority_check {
__u8 priority;
};
#define KBASE_IOCTL_CONTEXT_PRIORITY_CHECK \
#define KBASE_IOCTL_CONTEXT_PRIORITY_CHECK \
_IOWR(KBASE_IOCTL_TYPE, 54, struct kbase_ioctl_context_priority_check)
/**
@@ -589,7 +589,7 @@ struct kbase_ioctl_set_limited_core_count {
__u8 max_core_count;
};
#define KBASE_IOCTL_SET_LIMITED_CORE_COUNT \
#define KBASE_IOCTL_SET_LIMITED_CORE_COUNT \
_IOW(KBASE_IOCTL_TYPE, 55, struct kbase_ioctl_set_limited_core_count)
/**
@@ -610,7 +610,7 @@ struct kbase_ioctl_kinstr_prfcnt_enum_info {
__u64 info_list_ptr;
};
#define KBASE_IOCTL_KINSTR_PRFCNT_ENUM_INFO \
#define KBASE_IOCTL_KINSTR_PRFCNT_ENUM_INFO \
_IOWR(KBASE_IOCTL_TYPE, 56, struct kbase_ioctl_kinstr_prfcnt_enum_info)
/**
@@ -639,7 +639,7 @@ union kbase_ioctl_kinstr_prfcnt_setup {
} out;
};
#define KBASE_IOCTL_KINSTR_PRFCNT_SETUP \
#define KBASE_IOCTL_KINSTR_PRFCNT_SETUP \
_IOWR(KBASE_IOCTL_TYPE, 57, union kbase_ioctl_kinstr_prfcnt_setup)
/***************
@@ -782,7 +782,7 @@ struct kbase_ioctl_tlstream_stats {
#define KBASE_GPUPROP_RAW_THREAD_TLS_ALLOC 83
#define KBASE_GPUPROP_TLS_ALLOC 84
#define KBASE_GPUPROP_RAW_GPU_FEATURES 85
#ifdef __cpluscplus
#ifdef __cplusplus
}
#endif