diff --git a/drivers/staging/mt7621-mmc/sd.c b/drivers/staging/mt7621-mmc/sd.c
index 518ede67b427..6f57d92b564b 100644
--- a/drivers/staging/mt7621-mmc/sd.c
+++ b/drivers/staging/mt7621-mmc/sd.c
@@ -2987,27 +2987,10 @@ static int __init mt_msdc_init(void)
 
 	printk("MTK MSDC device init.\n");
 	mtk_sd_device.dev.platform_data = &msdc0_hw;
-	if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
-//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
-		reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
-//#if defined (CONFIG_RALINK_MT7620)
-		if (ralink_soc == MT762X_SOC_MT7620A)
-			reg |= 0x1 << 18;
-//#endif
-	} else {
-//#elif defined (CONFIG_RALINK_MT7628)
-		/* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
-		reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x3c));
-		reg |= 0x1e << 16;
-		sdr_write32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x3c), reg);
 
-		reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 10);
-#if defined(CONFIG_MTK_MMC_EMMC_8BIT)
-		reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
-		msdc0_hw.data_pins      = 8,
-#endif
-//#endif
-	}
+	// Set the pins for sdxc to sdxc mode
+	//FIXME: this should be done by pinctl and not by the sd driver
+	reg = sdr_read32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
 	sdr_write32((volatile u32 *)(RALINK_SYSCTL_BASE + 0x60), reg);
 	//platform_device_register(&mtk_sd_device);
 /* end of +++ */