shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 12:17:12 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'v5.6-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Browse Source 
Removal of the simple-panel compatible and some minor
additional cleanups.

* tag 'v5.6-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Kill off "simple-panel" compatibles
  ARM: dts: rockchip: rename dwmmc node names to mmc
  ARM: dts: rockchip: add reg property to brcmf sub node for rk3188-bqedison2qc

Link: https://lore.kernel.org/r/3473489.DgqFdXXe5V@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2020-01-19 22:47:27 -08:00
parent faaa9f6e8a 8039c828a6
commit b744f09879
10 changed files with 23 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -224,7 +224,7 @@
status = "disabled";
};
sdmmc: dwmmc@10214000 {
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
@@ -238,7 +238,7 @@
status = "disabled";
};
sdio: dwmmc@10218000 {
sdio: mmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
max-frequency = <37500000>;
@@ -252,7 +252,7 @@
status = "disabled";
};
emmc: dwmmc@1021c000 {
emmc: mmc@1021c000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

3
arch/arm/boot/dts/rk3188-bqedison2qc.dts
View File

@@ -466,9 +466,12 @@
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
vmmcq-supply = <&vccio_wl>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio3>;
interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>;

6
arch/arm/boot/dts/rk322x.dtsi
View File

@@ -662,7 +662,7 @@
};
};
sdmmc: dwmmc@30000000 {
sdmmc: mmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -675,7 +675,7 @@
status = "disabled";
};
sdio: dwmmc@30010000 {
sdio: mmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -688,7 +688,7 @@
status = "disabled";
};
emmc: dwmmc@30020000 {
emmc: mmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/rk3288-evb.dtsi
View File

@@ -97,7 +97,7 @@
};
panel: panel {
compatible = "lg,lp079qx1-sp0v", "simple-panel";
compatible = "lg,lp079qx1-sp0v";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;

2
arch/arm/boot/dts/rk3288-veyron-edp.dtsi
View File

@@ -54,7 +54,7 @@
};
panel: panel {
compatible = "innolux,n116bge", "simple-panel";
compatible = "innolux,n116bge";
status = "okay";
power-supply = <&panel_regulator>;
backlight = <&backlight>;

2
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View File

@@ -71,7 +71,7 @@
};
&panel {
compatible = "auo,b101ean01", "simple-panel";
compatible = "auo,b101ean01";
/delete-node/ panel-timing;

2
arch/arm/boot/dts/rk3288-veyron-tiger.dts
View File

@@ -53,7 +53,7 @@
};
&panel {
compatible = "auo,b101ean01", "simple-panel";
compatible = "auo,b101ean01";
/delete-node/ panel-timing;

8
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -247,7 +247,7 @@
ports = <&vopl_out>, <&vopb_out>;
};
sdmmc: dwmmc@ff0c0000 {
sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
@@ -261,7 +261,7 @@
status = "disabled";
};
sdio0: dwmmc@ff0d0000 {
sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
@@ -275,7 +275,7 @@
status = "disabled";
};
sdio1: dwmmc@ff0e0000 {
sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
@@ -289,7 +289,7 @@
status = "disabled";
};
emmc: dwmmc@ff0f0000 {
emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

6
arch/arm/boot/dts/rk3xxx.dtsi
View File

@@ -231,7 +231,7 @@
status = "disabled";
};
mmc0: dwmmc@10214000 {
mmc0: mmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -245,7 +245,7 @@
status = "disabled";
};
mmc1: dwmmc@10218000 {
mmc1: mmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -259,7 +259,7 @@
status = "disabled";
};
emmc: dwmmc@1021c000 {
emmc: mmc@1021c000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x1021c000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm/boot/dts/rv1108.dtsi
View File

@@ -456,7 +456,7 @@
#reset-cells = <1>;
};
emmc: dwmmc@30110000 {
emmc: mmc@30110000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30110000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +468,7 @@
status = "disabled";
};
sdio: dwmmc@30120000 {
sdio: mmc@30120000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30120000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -480,7 +480,7 @@
status = "disabled";
};
sdmmc: dwmmc@30130000 {
sdmmc: mmc@30130000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30130000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;