diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c
index 056acbc70f4c..df431e9b4202 100644
--- a/drivers/clk/rockchip/clk-rk3506.c
+++ b/drivers/clk/rockchip/clk-rk3506.c
@@ -100,6 +100,7 @@ static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = {
 	RK3506_CPUCLK_RATE(1008000000, 1, 7),
 	RK3506_CPUCLK_RATE(903168000, 1, 7),
 	RK3506_CPUCLK_RATE(800000000, 1, 6),
+	RK3506_CPUCLK_RATE(750000000, 1, 5),
 	RK3506_CPUCLK_RATE(589824000, 1, 4),
 	RK3506_CPUCLK_RATE(400000000, 1, 3),
 	RK3506_CPUCLK_RATE(200000000, 1, 1),
@@ -160,7 +161,8 @@ static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
 		     RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
 	[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
 		     0, RK3506_PLL_CON(16),
-		     RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
+		     RK3506_MODE_CON, 4, 1,
+		     ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3506_pll_rates),
 };
 
 static struct rockchip_clk_branch rk3506_armclk __initdata =
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
index 1e952e1bbbe8..2c3cacdeebe7 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
@@ -1158,7 +1158,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
 
 			reinit_completion(&i2c->cmp);
 
-			hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
+			hdmi_writel(hdmi, *buf, I2CM_INTERFACE_WRDATA_0_3);
 			hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
 				I2CM_INTERFACE_CONTROL0);
 			hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
@@ -1183,6 +1183,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
 				continue;
 			}
 			/* write success */
+			buf++;
 			break;
 		}
 		hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5a931f086c33..d0baf6edf87e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -3597,10 +3597,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
 	}
 
 	dclk_inv = (s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
-	/* For improving signal quality, dclk need to be inverted by default on rv1106. */
-	if (vop->version == VOP_VERSION_RV1106)
-		dclk_inv = !dclk_inv;
-
 	VOP_CTRL_SET(vop, dclk_pol, dclk_inv);
 	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
 		   0 : BIT(HSYNC_POSITIVE);
@@ -3616,6 +3612,15 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
 
 	switch (s->output_type) {
 	case DRM_MODE_CONNECTOR_DPI:
+		/*
+		 * In order to ensure that the data is sampled along the rising
+		 * edge without flag DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, dclk of
+		 * bt1120/bt656/rgb need to be inverted by default on rv1106 and
+		 * rk3506.
+		 */
+		if (vop->version == VOP_VERSION_RV1106 || vop->version == VOP_VERSION_RK3506)
+			dclk_inv = !dclk_inv;
+		fallthrough;
 	case DRM_MODE_CONNECTOR_LVDS:
 		VOP_CTRL_SET(vop, rgb_en, 1);
 		VOP_CTRL_SET(vop, rgb_pin_pol, val);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index f3475256cd5e..9c2f8697cb2b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -2450,7 +2450,8 @@ static bool vop3_output_rb_swap(struct rockchip_crtc_state *vcstate)
 	 * The default component order of serial rgb3x8 formats
 	 * is BGR. So it is needed to enable RB swap.
 	 */
-	if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
+	if (bus_format == MEDIA_BUS_FMT_BGR888_1X24 ||
+	    bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
 	    bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
 		return true;
 	else