From c715781b9e24290846d0dc783ff617941f909829 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Tue, 8 Oct 2024 15:01:19 +0800 Subject: [PATCH 1/5] drm/rockchip: vop: set dclk inverted by default for bt1120/bt656/rgb on rk3506 According to rk3506 SI report, dclk of bt1120/bt656/rgb need to be inverted by default, in order to ensure that the data is sampled along the rising edge. Change-Id: I734f146b5cb33ac6f7f069509a8bb16adefe12d4 Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 5a931f086c33..d0baf6edf87e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -3597,10 +3597,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, } dclk_inv = (s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; - /* For improving signal quality, dclk need to be inverted by default on rv1106. */ - if (vop->version == VOP_VERSION_RV1106) - dclk_inv = !dclk_inv; - VOP_CTRL_SET(vop, dclk_pol, dclk_inv); val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); @@ -3616,6 +3612,15 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, switch (s->output_type) { case DRM_MODE_CONNECTOR_DPI: + /* + * In order to ensure that the data is sampled along the rising + * edge without flag DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, dclk of + * bt1120/bt656/rgb need to be inverted by default on rv1106 and + * rk3506. + */ + if (vop->version == VOP_VERSION_RV1106 || vop->version == VOP_VERSION_RK3506) + dclk_inv = !dclk_inv; + fallthrough; case DRM_MODE_CONNECTOR_LVDS: VOP_CTRL_SET(vop, rgb_en, 1); VOP_CTRL_SET(vop, rgb_pin_pol, val); From 9e3dd928787142c0b2c48dcd5cf3de6a85ba666d Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Thu, 10 Oct 2024 14:36:55 +0800 Subject: [PATCH 2/5] drm/rockchip: vop2: enable rb swap for MEDIA_BUS_FMT_BGR888_1X24 It is needed to enable rb swap to support MEDIA_BUS_FMT_BGR888_1X24, because the default 24bpp rgb output is MEDIA_BUS_FMT_RGB888_1X24. Change-Id: Ifb55f0e97f3a914b9f66b6de49e85697fdc7aeae Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index f3475256cd5e..9c2f8697cb2b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2450,7 +2450,8 @@ static bool vop3_output_rb_swap(struct rockchip_crtc_state *vcstate) * The default component order of serial rgb3x8 formats * is BGR. So it is needed to enable RB swap. */ - if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 || + if (bus_format == MEDIA_BUS_FMT_BGR888_1X24 || + bus_format == MEDIA_BUS_FMT_RGB888_3X8 || bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8) return true; else From 36f4f47e78b1109760f1c2167805a13b2da1cc2a Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Fri, 11 Oct 2024 11:52:32 +0800 Subject: [PATCH 3/5] drm/bridge: synopsys: dw-hdmi-qp: Fixed ddc write heap corruption Change-Id: Ief41e4e71be8ccc0cb5cb4f9b1e7d0a496a60704 Signed-off-by: Algea Cao --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 1e952e1bbbe8..2c3cacdeebe7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -1158,7 +1158,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, reinit_completion(&i2c->cmp); - hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); + hdmi_writel(hdmi, *buf, I2CM_INTERFACE_WRDATA_0_3); hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, I2CM_INTERFACE_CONTROL0); hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, @@ -1183,6 +1183,7 @@ static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, continue; } /* write success */ + buf++; break; } hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); From c4c905472f7aefe622468793c2676340eaa39329 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 11 Oct 2024 11:47:08 +0800 Subject: [PATCH 4/5] clk: rockchip: rk3506: Add 750MHz for cpu Change-Id: Id0b93c64aa51376bf16ea5604f356a7509e337d0 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3506.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c index 056acbc70f4c..b1162aba82f9 100644 --- a/drivers/clk/rockchip/clk-rk3506.c +++ b/drivers/clk/rockchip/clk-rk3506.c @@ -100,6 +100,7 @@ static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = { RK3506_CPUCLK_RATE(1008000000, 1, 7), RK3506_CPUCLK_RATE(903168000, 1, 7), RK3506_CPUCLK_RATE(800000000, 1, 6), + RK3506_CPUCLK_RATE(750000000, 1, 5), RK3506_CPUCLK_RATE(589824000, 1, 4), RK3506_CPUCLK_RATE(400000000, 1, 3), RK3506_CPUCLK_RATE(200000000, 1, 1), From 29918d51d62ef05126f3ff2ba1a91c66966e55fe Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 11 Oct 2024 11:48:33 +0800 Subject: [PATCH 5/5] clk: rockchip: rk3506: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN flag for v1pll Change-Id: Ieb991acf5497aefd4ad041f415bd27f19af4b10d Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-rk3506.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c index b1162aba82f9..df431e9b4202 100644 --- a/drivers/clk/rockchip/clk-rk3506.c +++ b/drivers/clk/rockchip/clk-rk3506.c @@ -161,7 +161,8 @@ static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = { RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates), [v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p, 0, RK3506_PLL_CON(16), - RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates), + RK3506_MODE_CON, 4, 1, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3506_pll_rates), }; static struct rockchip_clk_branch rk3506_armclk __initdata =