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pq: add yuv full to rgb full feature [2/2]
PD#SWPL-15366 Problem: according source type, add YUV full to RGB Full Solution: according source type, add YUV full to RGB Full Verify: TL1 Change-Id: I1afb7bc56161dee87d055a7686d99377db954be4 Signed-off-by: Yong Qin <yong.qin@amlogic.com>
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@@ -3770,6 +3770,7 @@ int signal_type_changed(struct vframe_s *vf,
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struct vframe_master_display_colour_s *p_new = NULL;
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struct vframe_master_display_colour_s cus;
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int ret;
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u32 limit_full = 0;
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if (!vf)
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return 0;
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@@ -3782,6 +3783,7 @@ int signal_type_changed(struct vframe_s *vf,
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}
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} else
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cur_mvc_type[vd_path] = 0;
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limit_full = (vf->signal_type >> 25) & 0x01;
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if ((vf->source_type == VFRAME_SOURCE_TYPE_TUNER) ||
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(vf->source_type == VFRAME_SOURCE_TYPE_CVBS) ||
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(vf->source_type == VFRAME_SOURCE_TYPE_COMP) ||
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@@ -3801,7 +3803,7 @@ int signal_type_changed(struct vframe_s *vf,
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/* default 709 limit */
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(1 << 29) /* video available */
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| (5 << 26) /* unspecified */
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| (0 << 25) /* limit */
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| (limit_full << 25) /* limit */
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| (1 << 24) /* color available */
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| (1 << 16) /* bt709 */
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| (1 << 8) /* bt709 */
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@@ -7015,7 +7017,7 @@ static void video_process(
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mtx_setting(POST2_MTX, MATRIX_NULL, MTX_OFF);
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else
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mtx_setting(POST2_MTX,
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MATRIX_YUV709_RGB, MTX_ON);
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csc_type/*MATRIX_YUV709_RGB*/, MTX_ON);
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}
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if (cur_hdr_process_mode[vd_path] !=
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@@ -6003,6 +6003,12 @@ static ssize_t amvecm_debug_store(struct class *cla,
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goto free_buf;
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}
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gmv_th = val;
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} else if (!strcmp(parm[0], "post2mtx")) {
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if (parm[1]) {
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if (kstrtoul(parm[1], 16, &val) < 0)
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goto free_buf;
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mtx_setting(POST2_MTX, val, 1);
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}
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} else
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pr_info("unsupport cmd\n");
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@@ -2750,7 +2750,20 @@ void mtx_setting(enum vpp_matrix_e mtx_sel,
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WRITE_VPP_REG(matrix_pre_offset0_1, 0x7c00600);
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WRITE_VPP_REG(matrix_pre_offset2, 0x00000600);
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break;
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case MATRIX_YUV709F_RGB:/*full to full*/
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WRITE_VPP_REG(matrix_coef00_01, 0x04000000);
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WRITE_VPP_REG(matrix_coef02_10, 0x064D0400);
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WRITE_VPP_REG(matrix_coef11_12, 0x1F411E21);
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WRITE_VPP_REG(matrix_coef20_21, 0x0400076D);
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WRITE_VPP_REG(matrix_coef22, 0x0);
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WRITE_VPP_REG(matrix_offset0_1, 0x0);
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WRITE_VPP_REG(matrix_offset2, 0x0);
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WRITE_VPP_REG(matrix_pre_offset0_1, 0x0000600);
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WRITE_VPP_REG(matrix_pre_offset2, 0x00000600);
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break;
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default:
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break;
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}
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/*pr_info("mtx_sel:%d, mtx_csc:0x%x\n", mtx_sel, mtx_csc);*/
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}
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