From b8262b15d8a5f3959d7f103b786a66758edeafa0 Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Tue, 11 Aug 2020 11:15:20 +0900 Subject: [PATCH] media: hdmitx: Update hdmi hpll generation for low pixel clock Change-Id: I83bd8688379f7e70354013c5f1a02c6995beed31 --- drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 4 ++-- drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index df9513a8ebdc..6e9dd1f4e747 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -1110,8 +1110,8 @@ next: p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10); pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n", __func__, custom_timing->frac_freq); - /* check if hpll clk output is under (100*10)MHz */ - if (p_enc[j].hpll_clk_out < 1000000) { + /* check if hpll clk output is under (140*10)MHz */ + if (p_enc[j].hpll_clk_out < 1400000) { p_enc[j].hpll_clk_out *= 4; /* control od dividers */ p_enc[j].od1 = 4; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index e9b2929fb28d..cfc0f9573b64 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -331,7 +331,7 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk) /* calculate "m" */ m1 = (clk * 0x3A) / 1422000; m2 = (clk * 0xE1) / 5405400; - m = (m1 + m2)/2; + m = ((m1 + m2) / 2) + 1; m &= 0xff; m |= 0x3b000400; hd_write_reg(P_HHI_HDMI_PLL_CNTL0, m);