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drm/rockchip: analogix_dp: use mode crtc_* timing for hardware config

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The mode contains two copies of timings, first are the plain and
origin timings, this should keep unchanged, the second are copy
from the first timing by add some computed and special fixup, this
is associate with hardware.

Change-Id: I14dd9596445d5cac0297fcf6306a82b40b31cdaa
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2024-04-16 09:48:10 +08:00
committed by Tao Huang
parent 96708c3281
commit b935b0aa0c
2 changed files with 15 additions and 15 deletions
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2
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@@ -71,7 +71,7 @@ static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp,
if (info->bpc)
bpp = 3 * info->bpc;
req_bw = mode->clock * bpp / 8;
req_bw = mode->crtc_clock * bpp / 8;
max_bw = lanes * rate;
if (req_bw > max_bw)
return false;

28
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View File

@@ -1276,22 +1276,22 @@ void analogix_dp_set_video_format(struct analogix_dp_device *dp)
const struct drm_display_mode *mode = &video->mode;
unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
hsw = mode->hsync_end - mode->hsync_start;
hfp = mode->hsync_start - mode->hdisplay;
hbp = mode->htotal - mode->hsync_end;
vsw = mode->vsync_end - mode->vsync_start;
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
hsw = mode->crtc_hsync_end - mode->crtc_hsync_start;
hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;
hbp = mode->crtc_htotal - mode->crtc_hsync_end;
vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
vfp = mode->crtc_vsync_start - mode->crtc_vdisplay;
vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
/* Set Video Format Parameters */
analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_L,
TOTAL_LINE_CFG_L(mode->vtotal));
TOTAL_LINE_CFG_L(mode->crtc_vtotal));
analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_H,
TOTAL_LINE_CFG_H(mode->vtotal >> 8));
TOTAL_LINE_CFG_H(mode->crtc_vtotal >> 8));
analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_L,
ACTIVE_LINE_CFG_L(mode->vdisplay));
ACTIVE_LINE_CFG_L(mode->crtc_vdisplay));
analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_H,
ACTIVE_LINE_CFG_H(mode->vdisplay >> 8));
ACTIVE_LINE_CFG_H(mode->crtc_vdisplay >> 8));
analogix_dp_write(dp, ANALOGIX_DP_V_F_PORCH_CFG,
V_F_PORCH_CFG(vfp));
analogix_dp_write(dp, ANALOGIX_DP_V_SYNC_WIDTH_CFG,
@@ -1299,13 +1299,13 @@ void analogix_dp_set_video_format(struct analogix_dp_device *dp)
analogix_dp_write(dp, ANALOGIX_DP_V_B_PORCH_CFG,
V_B_PORCH_CFG(vbp));
analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_L,
TOTAL_PIXEL_CFG_L(mode->htotal));
TOTAL_PIXEL_CFG_L(mode->crtc_htotal));
analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_H,
TOTAL_PIXEL_CFG_H(mode->htotal >> 8));
TOTAL_PIXEL_CFG_H(mode->crtc_htotal >> 8));
analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_L,
ACTIVE_PIXEL_CFG_L(mode->hdisplay));
ACTIVE_PIXEL_CFG_L(mode->crtc_hdisplay));
analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_H,
ACTIVE_PIXEL_CFG_H(mode->hdisplay >> 8));
ACTIVE_PIXEL_CFG_H(mode->crtc_hdisplay >> 8));
analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_L,
H_F_PORCH_CFG_L(hfp));
analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_H,