From b99f522bf7b9b65c930803eed00efcc107caadeb Mon Sep 17 00:00:00 2001 From: Weiwen Chen Date: Mon, 14 Jul 2025 17:22:41 +0800 Subject: [PATCH] arm64: dts: rockchip: add rv1126b-evb1-v11-fastboot-spi-nor.dts Signed-off-by: Weiwen Chen Change-Id: I8ff6e83cdece005e382076e26ae1613b25237682 --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rv1126b-evb1-v11-fastboot-spi-nor.dts | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 6cfbd5b45b85..47539cacff71 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -388,6 +388,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-dual-4k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-emmc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-fastboot-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-spi-nor.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb diff --git a/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts new file mode 100644 index 000000000000..eb1d0ee5ad79 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rv1126b-evb1-v11-fastboot-spi-nor.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#include "rv1126b-evb1-v10-fastboot-spi-nor.dts" +#include "rv1126b-evb1-v11.dtsi" + +/ { + model = "Rockchip RV1126B EVB1 V11 Arm64 Board"; + compatible = "rockchip,rv1126b-evb1-v11-fastboot-spi-nor", "rockchip,rv1126b"; + + chosen { + bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K"; + }; +}; + +&ramdisk_r { + reg = <0x48c40000 (20 * 0x00100000)>; +}; + +&ramdisk_c { + reg = <0x4a040000 (10 * 0x00100000)>; +};