From b9c21ec37c7b084abe98a5113e33b8499669c585 Mon Sep 17 00:00:00 2001
From: Wyon Bi <bivvy.bi@rock-chips.com>
Date: Thu, 11 Oct 2018 11:44:06 +0800
Subject: [PATCH] drm/rockchip: lvds: check PLL lock state before enable tx

Change-Id: I299d93f89ec52d3778bc2b18cb9105f9910dd5fc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_lvds.c | 11 +++++++++++
 drivers/gpu/drm/rockchip/rockchip_lvds.h |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
index af34354f44de..91f78e8f7160 100644
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
@@ -21,6 +21,7 @@
 
 #include <linux/component.h>
 #include <linux/clk.h>
+#include <linux/iopoll.h>
 #include <linux/mfd/syscon.h>
 #include <linux/of_device.h>
 #include <linux/of_graph.h>
@@ -144,6 +145,9 @@ static inline int lvds_name_to_output(const char *s)
 
 static int innov2_lvds_power_on(struct rockchip_lvds *lvds)
 {
+	u32 status;
+	int ret;
+
 	if (lvds->output == DISPLAY_OUTPUT_RGB) {
 		lvds_writel(lvds, RK3288_LVDS_CH0_REG0,
 			    RK3288_LVDS_CH0_REG0_TTL_EN |
@@ -213,6 +217,13 @@ static int innov2_lvds_power_on(struct rockchip_lvds *lvds)
 
 	writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
 	       lvds->regs + RK3288_LVDS_CFG_REGC);
+	ret = readl_poll_timeout(lvds->regs + RK3288_LVDS_CH0_REGF, status,
+				 status & RK3288_LVDS_CH0_PLL_LOCK, 500, 10000);
+	if (ret) {
+		dev_err(lvds->dev, "PLL is not lock\n");
+		return ret;
+	}
+
 	writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
 	       lvds->regs + RK3288_LVDS_CFG_REG21);
 
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/rockchip/rockchip_lvds.h
index d517d75ba365..0cc9fbe36535 100644
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.h
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h
@@ -71,6 +71,9 @@
 #define RK3288_LVDS_CH0_REGD			0x34
 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
 
+#define RK3288_LVDS_CH0_REGF			0x3c
+#define RK3288_LVDS_CH0_PLL_LOCK		BIT(1)
+
 #define RK3288_LVDS_CH0_REG20			0x80
 #define RK3288_LVDS_CH0_REG20_MSB		0x45
 #define RK3288_LVDS_CH0_REG20_LSB		0x44